2013-03-08 05:37:17 +08:00
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|
// RUN: %clang_cc1 %s -emit-llvm -o - -triple=armv7-apple-ios -std=c11 | FileCheck %s
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// There isn't really anything special about iOS; it just happens to
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// only deploy on processors with native atomics support, so it's a good
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// way to test those code-paths.
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// This work was done in pursuit of <rdar://13338582>.
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2014-12-05 09:06:59 +08:00
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// CHECK-LABEL: define void @testFloat(float*
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2013-03-08 05:37:17 +08:00
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|
void testFloat(_Atomic(float) *fp) {
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// CHECK: [[FP:%.*]] = alloca float*
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// CHECK-NEXT: [[X:%.*]] = alloca float
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// CHECK-NEXT: [[F:%.*]] = alloca float
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// CHECK-NEXT: store float* {{%.*}}, float** [[FP]]
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|
2015-02-28 05:19:58 +08:00
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// CHECK-NEXT: [[T0:%.*]] = load float*, float** [[FP]]
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2013-03-08 05:37:17 +08:00
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// CHECK-NEXT: store float 1.000000e+00, float* [[T0]], align 4
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__c11_atomic_init(fp, 1.0f);
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// CHECK-NEXT: store float 2.000000e+00, float* [[X]], align 4
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_Atomic(float) x = 2.0f;
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2015-02-28 05:19:58 +08:00
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// CHECK-NEXT: [[T0:%.*]] = load float*, float** [[FP]]
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2013-03-08 05:37:17 +08:00
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// CHECK-NEXT: [[T1:%.*]] = bitcast float* [[T0]] to i32*
|
2015-02-28 05:19:58 +08:00
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// CHECK-NEXT: [[T2:%.*]] = load atomic i32, i32* [[T1]] seq_cst, align 4
|
2013-03-08 05:37:17 +08:00
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// CHECK-NEXT: [[T3:%.*]] = bitcast i32 [[T2]] to float
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// CHECK-NEXT: store float [[T3]], float* [[F]]
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float f = *fp;
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2015-02-28 05:19:58 +08:00
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// CHECK-NEXT: [[T0:%.*]] = load float, float* [[F]], align 4
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// CHECK-NEXT: [[T1:%.*]] = load float*, float** [[FP]], align 4
|
2013-03-08 05:37:17 +08:00
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// CHECK-NEXT: [[T2:%.*]] = bitcast float [[T0]] to i32
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// CHECK-NEXT: [[T3:%.*]] = bitcast float* [[T1]] to i32*
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// CHECK-NEXT: store atomic i32 [[T2]], i32* [[T3]] seq_cst, align 4
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*fp = f;
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// CHECK-NEXT: ret void
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}
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2014-12-05 09:06:59 +08:00
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|
// CHECK: define void @testComplexFloat([[CF:{ float, float }]]*
|
2013-03-08 05:37:17 +08:00
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|
void testComplexFloat(_Atomic(_Complex float) *fp) {
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// CHECK: [[FP:%.*]] = alloca [[CF]]*, align 4
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// CHECK-NEXT: [[X:%.*]] = alloca [[CF]], align 8
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// CHECK-NEXT: [[F:%.*]] = alloca [[CF]], align 4
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// CHECK-NEXT: [[TMP0:%.*]] = alloca [[CF]], align 8
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// CHECK-NEXT: [[TMP1:%.*]] = alloca [[CF]], align 8
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// CHECK-NEXT: store [[CF]]*
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|
2015-02-28 05:19:58 +08:00
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|
// CHECK-NEXT: [[P:%.*]] = load [[CF]]*, [[CF]]** [[FP]]
|
2015-02-28 03:18:17 +08:00
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|
// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[CF]], [[CF]]* [[P]], i32 0, i32 0
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// CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [[CF]], [[CF]]* [[P]], i32 0, i32 1
|
2013-03-08 05:37:17 +08:00
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|
// CHECK-NEXT: store float 1.000000e+00, float* [[T0]]
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|
// CHECK-NEXT: store float 0.000000e+00, float* [[T1]]
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|
|
__c11_atomic_init(fp, 1.0f);
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|
2015-02-28 03:18:17 +08:00
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|
// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[CF]], [[CF]]* [[X]], i32 0, i32 0
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|
// CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [[CF]], [[CF]]* [[X]], i32 0, i32 1
|
2013-03-08 05:37:17 +08:00
|
|
|
// CHECK-NEXT: store float 2.000000e+00, float* [[T0]]
|
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|
// CHECK-NEXT: store float 0.000000e+00, float* [[T1]]
|
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|
|
_Atomic(_Complex float) x = 2.0f;
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|
2015-02-28 05:19:58 +08:00
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|
// CHECK-NEXT: [[T0:%.*]] = load [[CF]]*, [[CF]]** [[FP]]
|
2013-03-08 05:37:17 +08:00
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|
// CHECK-NEXT: [[T1:%.*]] = bitcast [[CF]]* [[T0]] to i64*
|
2015-02-28 05:19:58 +08:00
|
|
|
// CHECK-NEXT: [[T2:%.*]] = load atomic i64, i64* [[T1]] seq_cst, align 8
|
2013-03-08 05:37:17 +08:00
|
|
|
// CHECK-NEXT: [[T3:%.*]] = bitcast [[CF]]* [[TMP0]] to i64*
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// CHECK-NEXT: store i64 [[T2]], i64* [[T3]], align 8
|
2015-02-28 03:18:17 +08:00
|
|
|
// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[CF]], [[CF]]* [[TMP0]], i32 0, i32 0
|
2015-02-28 05:19:58 +08:00
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|
// CHECK-NEXT: [[R:%.*]] = load float, float* [[T0]]
|
2015-02-28 03:18:17 +08:00
|
|
|
// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[CF]], [[CF]]* [[TMP0]], i32 0, i32 1
|
2015-02-28 05:19:58 +08:00
|
|
|
// CHECK-NEXT: [[I:%.*]] = load float, float* [[T0]]
|
2015-02-28 03:18:17 +08:00
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|
|
// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[CF]], [[CF]]* [[F]], i32 0, i32 0
|
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|
|
// CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [[CF]], [[CF]]* [[F]], i32 0, i32 1
|
2013-03-08 05:37:17 +08:00
|
|
|
// CHECK-NEXT: store float [[R]], float* [[T0]]
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|
|
// CHECK-NEXT: store float [[I]], float* [[T1]]
|
|
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|
|
_Complex float f = *fp;
|
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|
|
2015-02-28 03:18:17 +08:00
|
|
|
// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[CF]], [[CF]]* [[F]], i32 0, i32 0
|
2015-02-28 05:19:58 +08:00
|
|
|
// CHECK-NEXT: [[R:%.*]] = load float, float* [[T0]]
|
2015-02-28 03:18:17 +08:00
|
|
|
// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[CF]], [[CF]]* [[F]], i32 0, i32 1
|
2015-02-28 05:19:58 +08:00
|
|
|
// CHECK-NEXT: [[I:%.*]] = load float, float* [[T0]]
|
|
|
|
|
// CHECK-NEXT: [[DEST:%.*]] = load [[CF]]*, [[CF]]** [[FP]], align 4
|
2015-02-28 03:18:17 +08:00
|
|
|
// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[CF]], [[CF]]* [[TMP1]], i32 0, i32 0
|
|
|
|
|
// CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [[CF]], [[CF]]* [[TMP1]], i32 0, i32 1
|
2013-03-08 05:37:17 +08:00
|
|
|
// CHECK-NEXT: store float [[R]], float* [[T0]]
|
|
|
|
|
// CHECK-NEXT: store float [[I]], float* [[T1]]
|
|
|
|
|
// CHECK-NEXT: [[T0:%.*]] = bitcast [[CF]]* [[TMP1]] to i64*
|
2015-02-28 05:19:58 +08:00
|
|
|
// CHECK-NEXT: [[T1:%.*]] = load i64, i64* [[T0]], align 8
|
2013-03-08 05:37:17 +08:00
|
|
|
// CHECK-NEXT: [[T2:%.*]] = bitcast [[CF]]* [[DEST]] to i64*
|
|
|
|
|
// CHECK-NEXT: store atomic i64 [[T1]], i64* [[T2]] seq_cst, align 8
|
|
|
|
|
*fp = f;
|
|
|
|
|
|
|
|
|
|
// CHECK-NEXT: ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
typedef struct { short x, y, z, w; } S;
|
2014-12-05 09:06:59 +08:00
|
|
|
// CHECK: define void @testStruct([[S:.*]]*
|
2013-03-08 05:37:17 +08:00
|
|
|
void testStruct(_Atomic(S) *fp) {
|
|
|
|
|
// CHECK: [[FP:%.*]] = alloca [[S]]*, align 4
|
|
|
|
|
// CHECK-NEXT: [[X:%.*]] = alloca [[S]], align 8
|
|
|
|
|
// CHECK-NEXT: [[F:%.*]] = alloca [[S:%.*]], align 2
|
|
|
|
|
// CHECK-NEXT: [[TMP0:%.*]] = alloca [[S]], align 8
|
|
|
|
|
// CHECK-NEXT: store [[S]]*
|
|
|
|
|
|
2015-02-28 05:19:58 +08:00
|
|
|
// CHECK-NEXT: [[P:%.*]] = load [[S]]*, [[S]]** [[FP]]
|
2015-02-28 03:18:17 +08:00
|
|
|
// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[S]], [[S]]* [[P]], i32 0, i32 0
|
Compute and preserve alignment more faithfully in IR-generation.
Introduce an Address type to bundle a pointer value with an
alignment. Introduce APIs on CGBuilderTy to work with Address
values. Change core APIs on CGF/CGM to traffic in Address where
appropriate. Require alignments to be non-zero. Update a ton
of code to compute and propagate alignment information.
As part of this, I've promoted CGBuiltin's EmitPointerWithAlignment
helper function to CGF and made use of it in a number of places in
the expression emitter.
The end result is that we should now be significantly more correct
when performing operations on objects that are locally known to
be under-aligned. Since alignment is not reliably tracked in the
type system, there are inherent limits to this, but at least we
are no longer confused by standard operations like derived-to-base
conversions and array-to-pointer decay. I've also fixed a large
number of bugs where we were applying the complete-object alignment
to a pointer instead of the non-virtual alignment, although most of
these were hidden by the very conservative approach we took with
member alignment.
Also, because IRGen now reliably asserts on zero alignments, we
should no longer be subject to an absurd but frustrating recurring
bug where an incomplete type would report a zero alignment and then
we'd naively do a alignmentAtOffset on it and emit code using an
alignment equal to the largest power-of-two factor of the offset.
We should also now be emitting much more aggressive alignment
attributes in the presence of over-alignment. In particular,
field access now uses alignmentAtOffset instead of min.
Several times in this patch, I had to change the existing
code-generation pattern in order to more effectively use
the Address APIs. For the most part, this seems to be a strict
improvement, like doing pointer arithmetic with GEPs instead of
ptrtoint. That said, I've tried very hard to not change semantics,
but it is likely that I've failed in a few places, for which I
apologize.
ABIArgInfo now always carries the assumed alignment of indirect and
indirect byval arguments. In order to cut down on what was already
a dauntingly large patch, I changed the code to never set align
attributes in the IR on non-byval indirect arguments. That is,
we still generate code which assumes that indirect arguments have
the given alignment, but we don't express this information to the
backend except where it's semantically required (i.e. on byvals).
This is likely a minor regression for those targets that did provide
this information, but it'll be trivial to add it back in a later
patch.
I partially punted on applying this work to CGBuiltin. Please
do not add more uses of the CreateDefaultAligned{Load,Store}
APIs; they will be going away eventually.
llvm-svn: 246985
2015-09-08 16:05:57 +08:00
|
|
|
// CHECK-NEXT: store i16 1, i16* [[T0]], align 8
|
2015-02-28 03:18:17 +08:00
|
|
|
// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[S]], [[S]]* [[P]], i32 0, i32 1
|
2013-03-08 05:37:17 +08:00
|
|
|
// CHECK-NEXT: store i16 2, i16* [[T0]], align 2
|
2015-02-28 03:18:17 +08:00
|
|
|
// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[S]], [[S]]* [[P]], i32 0, i32 2
|
Compute and preserve alignment more faithfully in IR-generation.
Introduce an Address type to bundle a pointer value with an
alignment. Introduce APIs on CGBuilderTy to work with Address
values. Change core APIs on CGF/CGM to traffic in Address where
appropriate. Require alignments to be non-zero. Update a ton
of code to compute and propagate alignment information.
As part of this, I've promoted CGBuiltin's EmitPointerWithAlignment
helper function to CGF and made use of it in a number of places in
the expression emitter.
The end result is that we should now be significantly more correct
when performing operations on objects that are locally known to
be under-aligned. Since alignment is not reliably tracked in the
type system, there are inherent limits to this, but at least we
are no longer confused by standard operations like derived-to-base
conversions and array-to-pointer decay. I've also fixed a large
number of bugs where we were applying the complete-object alignment
to a pointer instead of the non-virtual alignment, although most of
these were hidden by the very conservative approach we took with
member alignment.
Also, because IRGen now reliably asserts on zero alignments, we
should no longer be subject to an absurd but frustrating recurring
bug where an incomplete type would report a zero alignment and then
we'd naively do a alignmentAtOffset on it and emit code using an
alignment equal to the largest power-of-two factor of the offset.
We should also now be emitting much more aggressive alignment
attributes in the presence of over-alignment. In particular,
field access now uses alignmentAtOffset instead of min.
Several times in this patch, I had to change the existing
code-generation pattern in order to more effectively use
the Address APIs. For the most part, this seems to be a strict
improvement, like doing pointer arithmetic with GEPs instead of
ptrtoint. That said, I've tried very hard to not change semantics,
but it is likely that I've failed in a few places, for which I
apologize.
ABIArgInfo now always carries the assumed alignment of indirect and
indirect byval arguments. In order to cut down on what was already
a dauntingly large patch, I changed the code to never set align
attributes in the IR on non-byval indirect arguments. That is,
we still generate code which assumes that indirect arguments have
the given alignment, but we don't express this information to the
backend except where it's semantically required (i.e. on byvals).
This is likely a minor regression for those targets that did provide
this information, but it'll be trivial to add it back in a later
patch.
I partially punted on applying this work to CGBuiltin. Please
do not add more uses of the CreateDefaultAligned{Load,Store}
APIs; they will be going away eventually.
llvm-svn: 246985
2015-09-08 16:05:57 +08:00
|
|
|
// CHECK-NEXT: store i16 3, i16* [[T0]], align 4
|
2015-02-28 03:18:17 +08:00
|
|
|
// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[S]], [[S]]* [[P]], i32 0, i32 3
|
2013-03-08 05:37:17 +08:00
|
|
|
// CHECK-NEXT: store i16 4, i16* [[T0]], align 2
|
|
|
|
|
__c11_atomic_init(fp, (S){1,2,3,4});
|
|
|
|
|
|
2015-02-28 03:18:17 +08:00
|
|
|
// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[S]], [[S]]* [[X]], i32 0, i32 0
|
Compute and preserve alignment more faithfully in IR-generation.
Introduce an Address type to bundle a pointer value with an
alignment. Introduce APIs on CGBuilderTy to work with Address
values. Change core APIs on CGF/CGM to traffic in Address where
appropriate. Require alignments to be non-zero. Update a ton
of code to compute and propagate alignment information.
As part of this, I've promoted CGBuiltin's EmitPointerWithAlignment
helper function to CGF and made use of it in a number of places in
the expression emitter.
The end result is that we should now be significantly more correct
when performing operations on objects that are locally known to
be under-aligned. Since alignment is not reliably tracked in the
type system, there are inherent limits to this, but at least we
are no longer confused by standard operations like derived-to-base
conversions and array-to-pointer decay. I've also fixed a large
number of bugs where we were applying the complete-object alignment
to a pointer instead of the non-virtual alignment, although most of
these were hidden by the very conservative approach we took with
member alignment.
Also, because IRGen now reliably asserts on zero alignments, we
should no longer be subject to an absurd but frustrating recurring
bug where an incomplete type would report a zero alignment and then
we'd naively do a alignmentAtOffset on it and emit code using an
alignment equal to the largest power-of-two factor of the offset.
We should also now be emitting much more aggressive alignment
attributes in the presence of over-alignment. In particular,
field access now uses alignmentAtOffset instead of min.
Several times in this patch, I had to change the existing
code-generation pattern in order to more effectively use
the Address APIs. For the most part, this seems to be a strict
improvement, like doing pointer arithmetic with GEPs instead of
ptrtoint. That said, I've tried very hard to not change semantics,
but it is likely that I've failed in a few places, for which I
apologize.
ABIArgInfo now always carries the assumed alignment of indirect and
indirect byval arguments. In order to cut down on what was already
a dauntingly large patch, I changed the code to never set align
attributes in the IR on non-byval indirect arguments. That is,
we still generate code which assumes that indirect arguments have
the given alignment, but we don't express this information to the
backend except where it's semantically required (i.e. on byvals).
This is likely a minor regression for those targets that did provide
this information, but it'll be trivial to add it back in a later
patch.
I partially punted on applying this work to CGBuiltin. Please
do not add more uses of the CreateDefaultAligned{Load,Store}
APIs; they will be going away eventually.
llvm-svn: 246985
2015-09-08 16:05:57 +08:00
|
|
|
// CHECK-NEXT: store i16 1, i16* [[T0]], align 8
|
2015-02-28 03:18:17 +08:00
|
|
|
// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[S]], [[S]]* [[X]], i32 0, i32 1
|
2013-03-08 05:37:17 +08:00
|
|
|
// CHECK-NEXT: store i16 2, i16* [[T0]], align 2
|
2015-02-28 03:18:17 +08:00
|
|
|
// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[S]], [[S]]* [[X]], i32 0, i32 2
|
Compute and preserve alignment more faithfully in IR-generation.
Introduce an Address type to bundle a pointer value with an
alignment. Introduce APIs on CGBuilderTy to work with Address
values. Change core APIs on CGF/CGM to traffic in Address where
appropriate. Require alignments to be non-zero. Update a ton
of code to compute and propagate alignment information.
As part of this, I've promoted CGBuiltin's EmitPointerWithAlignment
helper function to CGF and made use of it in a number of places in
the expression emitter.
The end result is that we should now be significantly more correct
when performing operations on objects that are locally known to
be under-aligned. Since alignment is not reliably tracked in the
type system, there are inherent limits to this, but at least we
are no longer confused by standard operations like derived-to-base
conversions and array-to-pointer decay. I've also fixed a large
number of bugs where we were applying the complete-object alignment
to a pointer instead of the non-virtual alignment, although most of
these were hidden by the very conservative approach we took with
member alignment.
Also, because IRGen now reliably asserts on zero alignments, we
should no longer be subject to an absurd but frustrating recurring
bug where an incomplete type would report a zero alignment and then
we'd naively do a alignmentAtOffset on it and emit code using an
alignment equal to the largest power-of-two factor of the offset.
We should also now be emitting much more aggressive alignment
attributes in the presence of over-alignment. In particular,
field access now uses alignmentAtOffset instead of min.
Several times in this patch, I had to change the existing
code-generation pattern in order to more effectively use
the Address APIs. For the most part, this seems to be a strict
improvement, like doing pointer arithmetic with GEPs instead of
ptrtoint. That said, I've tried very hard to not change semantics,
but it is likely that I've failed in a few places, for which I
apologize.
ABIArgInfo now always carries the assumed alignment of indirect and
indirect byval arguments. In order to cut down on what was already
a dauntingly large patch, I changed the code to never set align
attributes in the IR on non-byval indirect arguments. That is,
we still generate code which assumes that indirect arguments have
the given alignment, but we don't express this information to the
backend except where it's semantically required (i.e. on byvals).
This is likely a minor regression for those targets that did provide
this information, but it'll be trivial to add it back in a later
patch.
I partially punted on applying this work to CGBuiltin. Please
do not add more uses of the CreateDefaultAligned{Load,Store}
APIs; they will be going away eventually.
llvm-svn: 246985
2015-09-08 16:05:57 +08:00
|
|
|
// CHECK-NEXT: store i16 3, i16* [[T0]], align 4
|
2015-02-28 03:18:17 +08:00
|
|
|
// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[S]], [[S]]* [[X]], i32 0, i32 3
|
2013-03-08 05:37:17 +08:00
|
|
|
// CHECK-NEXT: store i16 4, i16* [[T0]], align 2
|
|
|
|
|
_Atomic(S) x = (S){1,2,3,4};
|
|
|
|
|
|
2015-02-28 05:19:58 +08:00
|
|
|
// CHECK-NEXT: [[T0:%.*]] = load [[S]]*, [[S]]** [[FP]]
|
2013-03-08 05:37:17 +08:00
|
|
|
// CHECK-NEXT: [[T1:%.*]] = bitcast [[S]]* [[T0]] to i64*
|
2015-02-28 05:19:58 +08:00
|
|
|
// CHECK-NEXT: [[T2:%.*]] = load atomic i64, i64* [[T1]] seq_cst, align 8
|
2013-03-08 05:37:17 +08:00
|
|
|
// CHECK-NEXT: [[T3:%.*]] = bitcast [[S]]* [[F]] to i64*
|
|
|
|
|
// CHECK-NEXT: store i64 [[T2]], i64* [[T3]], align 2
|
|
|
|
|
S f = *fp;
|
|
|
|
|
|
2015-02-28 05:19:58 +08:00
|
|
|
// CHECK-NEXT: [[T0:%.*]] = load [[S]]*, [[S]]** [[FP]]
|
2013-03-08 05:37:17 +08:00
|
|
|
// CHECK-NEXT: [[T1:%.*]] = bitcast [[S]]* [[TMP0]] to i8*
|
|
|
|
|
// CHECK-NEXT: [[T2:%.*]] = bitcast [[S]]* [[F]] to i8*
|
2015-11-19 13:55:59 +08:00
|
|
|
// CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* [[T1]], i8* [[T2]], i32 8, i32 2, i1 false)
|
2013-03-08 05:37:17 +08:00
|
|
|
// CHECK-NEXT: [[T3:%.*]] = bitcast [[S]]* [[TMP0]] to i64*
|
2015-02-28 05:19:58 +08:00
|
|
|
// CHECK-NEXT: [[T4:%.*]] = load i64, i64* [[T3]], align 8
|
2013-03-08 05:37:17 +08:00
|
|
|
// CHECK-NEXT: [[T5:%.*]] = bitcast [[S]]* [[T0]] to i64*
|
|
|
|
|
// CHECK-NEXT: store atomic i64 [[T4]], i64* [[T5]] seq_cst, align 8
|
|
|
|
|
*fp = f;
|
|
|
|
|
|
|
|
|
|
// CHECK-NEXT: ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
typedef struct { short x, y, z; } PS;
|
2014-12-05 09:06:59 +08:00
|
|
|
// CHECK: define void @testPromotedStruct([[APS:.*]]*
|
2013-03-08 05:37:17 +08:00
|
|
|
void testPromotedStruct(_Atomic(PS) *fp) {
|
|
|
|
|
// CHECK: [[FP:%.*]] = alloca [[APS]]*, align 4
|
|
|
|
|
// CHECK-NEXT: [[X:%.*]] = alloca [[APS]], align 8
|
|
|
|
|
// CHECK-NEXT: [[F:%.*]] = alloca [[PS:%.*]], align 2
|
|
|
|
|
// CHECK-NEXT: [[TMP0:%.*]] = alloca [[APS]], align 8
|
|
|
|
|
// CHECK-NEXT: [[TMP1:%.*]] = alloca [[APS]], align 8
|
|
|
|
|
// CHECK-NEXT: store [[APS]]*
|
|
|
|
|
|
2015-02-28 05:19:58 +08:00
|
|
|
// CHECK-NEXT: [[P:%.*]] = load [[APS]]*, [[APS]]** [[FP]]
|
2013-03-08 05:37:17 +08:00
|
|
|
// CHECK-NEXT: [[T0:%.*]] = bitcast [[APS]]* [[P]] to i8*
|
2015-11-19 13:55:59 +08:00
|
|
|
// CHECK-NEXT: call void @llvm.memset.p0i8.i64(i8* [[T0]], i8 0, i64 8, i32 8, i1 false)
|
2015-02-28 03:18:17 +08:00
|
|
|
// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[APS]], [[APS]]* [[P]], i32 0, i32 0
|
|
|
|
|
// CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [[PS]], [[PS]]* [[T0]], i32 0, i32 0
|
Compute and preserve alignment more faithfully in IR-generation.
Introduce an Address type to bundle a pointer value with an
alignment. Introduce APIs on CGBuilderTy to work with Address
values. Change core APIs on CGF/CGM to traffic in Address where
appropriate. Require alignments to be non-zero. Update a ton
of code to compute and propagate alignment information.
As part of this, I've promoted CGBuiltin's EmitPointerWithAlignment
helper function to CGF and made use of it in a number of places in
the expression emitter.
The end result is that we should now be significantly more correct
when performing operations on objects that are locally known to
be under-aligned. Since alignment is not reliably tracked in the
type system, there are inherent limits to this, but at least we
are no longer confused by standard operations like derived-to-base
conversions and array-to-pointer decay. I've also fixed a large
number of bugs where we were applying the complete-object alignment
to a pointer instead of the non-virtual alignment, although most of
these were hidden by the very conservative approach we took with
member alignment.
Also, because IRGen now reliably asserts on zero alignments, we
should no longer be subject to an absurd but frustrating recurring
bug where an incomplete type would report a zero alignment and then
we'd naively do a alignmentAtOffset on it and emit code using an
alignment equal to the largest power-of-two factor of the offset.
We should also now be emitting much more aggressive alignment
attributes in the presence of over-alignment. In particular,
field access now uses alignmentAtOffset instead of min.
Several times in this patch, I had to change the existing
code-generation pattern in order to more effectively use
the Address APIs. For the most part, this seems to be a strict
improvement, like doing pointer arithmetic with GEPs instead of
ptrtoint. That said, I've tried very hard to not change semantics,
but it is likely that I've failed in a few places, for which I
apologize.
ABIArgInfo now always carries the assumed alignment of indirect and
indirect byval arguments. In order to cut down on what was already
a dauntingly large patch, I changed the code to never set align
attributes in the IR on non-byval indirect arguments. That is,
we still generate code which assumes that indirect arguments have
the given alignment, but we don't express this information to the
backend except where it's semantically required (i.e. on byvals).
This is likely a minor regression for those targets that did provide
this information, but it'll be trivial to add it back in a later
patch.
I partially punted on applying this work to CGBuiltin. Please
do not add more uses of the CreateDefaultAligned{Load,Store}
APIs; they will be going away eventually.
llvm-svn: 246985
2015-09-08 16:05:57 +08:00
|
|
|
// CHECK-NEXT: store i16 1, i16* [[T1]], align 8
|
2015-02-28 03:18:17 +08:00
|
|
|
// CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [[PS]], [[PS]]* [[T0]], i32 0, i32 1
|
2013-03-08 05:37:17 +08:00
|
|
|
// CHECK-NEXT: store i16 2, i16* [[T1]], align 2
|
2015-02-28 03:18:17 +08:00
|
|
|
// CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [[PS]], [[PS]]* [[T0]], i32 0, i32 2
|
Compute and preserve alignment more faithfully in IR-generation.
Introduce an Address type to bundle a pointer value with an
alignment. Introduce APIs on CGBuilderTy to work with Address
values. Change core APIs on CGF/CGM to traffic in Address where
appropriate. Require alignments to be non-zero. Update a ton
of code to compute and propagate alignment information.
As part of this, I've promoted CGBuiltin's EmitPointerWithAlignment
helper function to CGF and made use of it in a number of places in
the expression emitter.
The end result is that we should now be significantly more correct
when performing operations on objects that are locally known to
be under-aligned. Since alignment is not reliably tracked in the
type system, there are inherent limits to this, but at least we
are no longer confused by standard operations like derived-to-base
conversions and array-to-pointer decay. I've also fixed a large
number of bugs where we were applying the complete-object alignment
to a pointer instead of the non-virtual alignment, although most of
these were hidden by the very conservative approach we took with
member alignment.
Also, because IRGen now reliably asserts on zero alignments, we
should no longer be subject to an absurd but frustrating recurring
bug where an incomplete type would report a zero alignment and then
we'd naively do a alignmentAtOffset on it and emit code using an
alignment equal to the largest power-of-two factor of the offset.
We should also now be emitting much more aggressive alignment
attributes in the presence of over-alignment. In particular,
field access now uses alignmentAtOffset instead of min.
Several times in this patch, I had to change the existing
code-generation pattern in order to more effectively use
the Address APIs. For the most part, this seems to be a strict
improvement, like doing pointer arithmetic with GEPs instead of
ptrtoint. That said, I've tried very hard to not change semantics,
but it is likely that I've failed in a few places, for which I
apologize.
ABIArgInfo now always carries the assumed alignment of indirect and
indirect byval arguments. In order to cut down on what was already
a dauntingly large patch, I changed the code to never set align
attributes in the IR on non-byval indirect arguments. That is,
we still generate code which assumes that indirect arguments have
the given alignment, but we don't express this information to the
backend except where it's semantically required (i.e. on byvals).
This is likely a minor regression for those targets that did provide
this information, but it'll be trivial to add it back in a later
patch.
I partially punted on applying this work to CGBuiltin. Please
do not add more uses of the CreateDefaultAligned{Load,Store}
APIs; they will be going away eventually.
llvm-svn: 246985
2015-09-08 16:05:57 +08:00
|
|
|
// CHECK-NEXT: store i16 3, i16* [[T1]], align 4
|
2013-03-08 05:37:17 +08:00
|
|
|
__c11_atomic_init(fp, (PS){1,2,3});
|
|
|
|
|
|
|
|
|
|
// CHECK-NEXT: [[T0:%.*]] = bitcast [[APS]]* [[X]] to i8*
|
2015-11-19 13:55:59 +08:00
|
|
|
// CHECK-NEXT: call void @llvm.memset.p0i8.i32(i8* [[T0]], i8 0, i32 8, i32 8, i1 false)
|
2015-02-28 03:18:17 +08:00
|
|
|
// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[APS]], [[APS]]* [[X]], i32 0, i32 0
|
|
|
|
|
// CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [[PS]], [[PS]]* [[T0]], i32 0, i32 0
|
Compute and preserve alignment more faithfully in IR-generation.
Introduce an Address type to bundle a pointer value with an
alignment. Introduce APIs on CGBuilderTy to work with Address
values. Change core APIs on CGF/CGM to traffic in Address where
appropriate. Require alignments to be non-zero. Update a ton
of code to compute and propagate alignment information.
As part of this, I've promoted CGBuiltin's EmitPointerWithAlignment
helper function to CGF and made use of it in a number of places in
the expression emitter.
The end result is that we should now be significantly more correct
when performing operations on objects that are locally known to
be under-aligned. Since alignment is not reliably tracked in the
type system, there are inherent limits to this, but at least we
are no longer confused by standard operations like derived-to-base
conversions and array-to-pointer decay. I've also fixed a large
number of bugs where we were applying the complete-object alignment
to a pointer instead of the non-virtual alignment, although most of
these were hidden by the very conservative approach we took with
member alignment.
Also, because IRGen now reliably asserts on zero alignments, we
should no longer be subject to an absurd but frustrating recurring
bug where an incomplete type would report a zero alignment and then
we'd naively do a alignmentAtOffset on it and emit code using an
alignment equal to the largest power-of-two factor of the offset.
We should also now be emitting much more aggressive alignment
attributes in the presence of over-alignment. In particular,
field access now uses alignmentAtOffset instead of min.
Several times in this patch, I had to change the existing
code-generation pattern in order to more effectively use
the Address APIs. For the most part, this seems to be a strict
improvement, like doing pointer arithmetic with GEPs instead of
ptrtoint. That said, I've tried very hard to not change semantics,
but it is likely that I've failed in a few places, for which I
apologize.
ABIArgInfo now always carries the assumed alignment of indirect and
indirect byval arguments. In order to cut down on what was already
a dauntingly large patch, I changed the code to never set align
attributes in the IR on non-byval indirect arguments. That is,
we still generate code which assumes that indirect arguments have
the given alignment, but we don't express this information to the
backend except where it's semantically required (i.e. on byvals).
This is likely a minor regression for those targets that did provide
this information, but it'll be trivial to add it back in a later
patch.
I partially punted on applying this work to CGBuiltin. Please
do not add more uses of the CreateDefaultAligned{Load,Store}
APIs; they will be going away eventually.
llvm-svn: 246985
2015-09-08 16:05:57 +08:00
|
|
|
// CHECK-NEXT: store i16 1, i16* [[T1]], align 8
|
2015-02-28 03:18:17 +08:00
|
|
|
// CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [[PS]], [[PS]]* [[T0]], i32 0, i32 1
|
2013-03-08 05:37:17 +08:00
|
|
|
// CHECK-NEXT: store i16 2, i16* [[T1]], align 2
|
2015-02-28 03:18:17 +08:00
|
|
|
// CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [[PS]], [[PS]]* [[T0]], i32 0, i32 2
|
Compute and preserve alignment more faithfully in IR-generation.
Introduce an Address type to bundle a pointer value with an
alignment. Introduce APIs on CGBuilderTy to work with Address
values. Change core APIs on CGF/CGM to traffic in Address where
appropriate. Require alignments to be non-zero. Update a ton
of code to compute and propagate alignment information.
As part of this, I've promoted CGBuiltin's EmitPointerWithAlignment
helper function to CGF and made use of it in a number of places in
the expression emitter.
The end result is that we should now be significantly more correct
when performing operations on objects that are locally known to
be under-aligned. Since alignment is not reliably tracked in the
type system, there are inherent limits to this, but at least we
are no longer confused by standard operations like derived-to-base
conversions and array-to-pointer decay. I've also fixed a large
number of bugs where we were applying the complete-object alignment
to a pointer instead of the non-virtual alignment, although most of
these were hidden by the very conservative approach we took with
member alignment.
Also, because IRGen now reliably asserts on zero alignments, we
should no longer be subject to an absurd but frustrating recurring
bug where an incomplete type would report a zero alignment and then
we'd naively do a alignmentAtOffset on it and emit code using an
alignment equal to the largest power-of-two factor of the offset.
We should also now be emitting much more aggressive alignment
attributes in the presence of over-alignment. In particular,
field access now uses alignmentAtOffset instead of min.
Several times in this patch, I had to change the existing
code-generation pattern in order to more effectively use
the Address APIs. For the most part, this seems to be a strict
improvement, like doing pointer arithmetic with GEPs instead of
ptrtoint. That said, I've tried very hard to not change semantics,
but it is likely that I've failed in a few places, for which I
apologize.
ABIArgInfo now always carries the assumed alignment of indirect and
indirect byval arguments. In order to cut down on what was already
a dauntingly large patch, I changed the code to never set align
attributes in the IR on non-byval indirect arguments. That is,
we still generate code which assumes that indirect arguments have
the given alignment, but we don't express this information to the
backend except where it's semantically required (i.e. on byvals).
This is likely a minor regression for those targets that did provide
this information, but it'll be trivial to add it back in a later
patch.
I partially punted on applying this work to CGBuiltin. Please
do not add more uses of the CreateDefaultAligned{Load,Store}
APIs; they will be going away eventually.
llvm-svn: 246985
2015-09-08 16:05:57 +08:00
|
|
|
// CHECK-NEXT: store i16 3, i16* [[T1]], align 4
|
2013-03-08 05:37:17 +08:00
|
|
|
_Atomic(PS) x = (PS){1,2,3};
|
|
|
|
|
|
2015-02-28 05:19:58 +08:00
|
|
|
// CHECK-NEXT: [[T0:%.*]] = load [[APS]]*, [[APS]]** [[FP]]
|
2013-03-08 05:37:17 +08:00
|
|
|
// CHECK-NEXT: [[T1:%.*]] = bitcast [[APS]]* [[T0]] to i64*
|
2015-02-28 05:19:58 +08:00
|
|
|
// CHECK-NEXT: [[T2:%.*]] = load atomic i64, i64* [[T1]] seq_cst, align 8
|
2013-03-08 05:37:17 +08:00
|
|
|
// CHECK-NEXT: [[T3:%.*]] = bitcast [[APS]]* [[TMP0]] to i64*
|
Compute and preserve alignment more faithfully in IR-generation.
Introduce an Address type to bundle a pointer value with an
alignment. Introduce APIs on CGBuilderTy to work with Address
values. Change core APIs on CGF/CGM to traffic in Address where
appropriate. Require alignments to be non-zero. Update a ton
of code to compute and propagate alignment information.
As part of this, I've promoted CGBuiltin's EmitPointerWithAlignment
helper function to CGF and made use of it in a number of places in
the expression emitter.
The end result is that we should now be significantly more correct
when performing operations on objects that are locally known to
be under-aligned. Since alignment is not reliably tracked in the
type system, there are inherent limits to this, but at least we
are no longer confused by standard operations like derived-to-base
conversions and array-to-pointer decay. I've also fixed a large
number of bugs where we were applying the complete-object alignment
to a pointer instead of the non-virtual alignment, although most of
these were hidden by the very conservative approach we took with
member alignment.
Also, because IRGen now reliably asserts on zero alignments, we
should no longer be subject to an absurd but frustrating recurring
bug where an incomplete type would report a zero alignment and then
we'd naively do a alignmentAtOffset on it and emit code using an
alignment equal to the largest power-of-two factor of the offset.
We should also now be emitting much more aggressive alignment
attributes in the presence of over-alignment. In particular,
field access now uses alignmentAtOffset instead of min.
Several times in this patch, I had to change the existing
code-generation pattern in order to more effectively use
the Address APIs. For the most part, this seems to be a strict
improvement, like doing pointer arithmetic with GEPs instead of
ptrtoint. That said, I've tried very hard to not change semantics,
but it is likely that I've failed in a few places, for which I
apologize.
ABIArgInfo now always carries the assumed alignment of indirect and
indirect byval arguments. In order to cut down on what was already
a dauntingly large patch, I changed the code to never set align
attributes in the IR on non-byval indirect arguments. That is,
we still generate code which assumes that indirect arguments have
the given alignment, but we don't express this information to the
backend except where it's semantically required (i.e. on byvals).
This is likely a minor regression for those targets that did provide
this information, but it'll be trivial to add it back in a later
patch.
I partially punted on applying this work to CGBuiltin. Please
do not add more uses of the CreateDefaultAligned{Load,Store}
APIs; they will be going away eventually.
llvm-svn: 246985
2015-09-08 16:05:57 +08:00
|
|
|
// CHECK-NEXT: store i64 [[T2]], i64* [[T3]], align 8
|
2015-02-28 03:18:17 +08:00
|
|
|
// CHECK-NEXT: [[T0:%.*]] = getelementptr inbounds [[APS]], [[APS]]* [[TMP0]], i32 0, i32 0
|
2013-03-08 05:37:17 +08:00
|
|
|
// CHECK-NEXT: [[T1:%.*]] = bitcast [[PS]]* [[F]] to i8*
|
|
|
|
|
// CHECK-NEXT: [[T2:%.*]] = bitcast [[PS]]* [[T0]] to i8*
|
2015-11-19 13:55:59 +08:00
|
|
|
// CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* [[T1]], i8* [[T2]], i32 6, i32 2, i1 false)
|
2013-03-08 05:37:17 +08:00
|
|
|
PS f = *fp;
|
|
|
|
|
|
2015-02-28 05:19:58 +08:00
|
|
|
// CHECK-NEXT: [[T0:%.*]] = load [[APS]]*, [[APS]]** [[FP]]
|
2013-07-11 09:32:21 +08:00
|
|
|
// CHECK-NEXT: [[T1:%.*]] = bitcast { %struct.PS, [2 x i8] }* [[TMP1]] to i8*
|
2015-11-19 13:55:59 +08:00
|
|
|
// CHECK-NEXT: call void @llvm.memset.p0i8.i32(i8* [[T1]], i8 0, i32 8, i32 8, i1 false)
|
2015-02-28 03:18:17 +08:00
|
|
|
// CHECK-NEXT: [[T1:%.*]] = getelementptr inbounds [[APS]], [[APS]]* [[TMP1]], i32 0, i32 0
|
2013-03-08 05:37:17 +08:00
|
|
|
// CHECK-NEXT: [[T2:%.*]] = bitcast [[PS]]* [[T1]] to i8*
|
|
|
|
|
// CHECK-NEXT: [[T3:%.*]] = bitcast [[PS]]* [[F]] to i8*
|
2015-11-19 13:55:59 +08:00
|
|
|
// CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* [[T2]], i8* [[T3]], i32 6, i32 2, i1 false)
|
2013-03-08 05:37:17 +08:00
|
|
|
// CHECK-NEXT: [[T4:%.*]] = bitcast [[APS]]* [[TMP1]] to i64*
|
2015-02-28 05:19:58 +08:00
|
|
|
// CHECK-NEXT: [[T5:%.*]] = load i64, i64* [[T4]], align 8
|
2013-03-08 05:37:17 +08:00
|
|
|
// CHECK-NEXT: [[T6:%.*]] = bitcast [[APS]]* [[T0]] to i64*
|
|
|
|
|
// CHECK-NEXT: store atomic i64 [[T5]], i64* [[T6]] seq_cst, align 8
|
|
|
|
|
*fp = f;
|
|
|
|
|
|
|
|
|
|
// CHECK-NEXT: ret void
|
|
|
|
|
}
|
|
|
|
|
|
2015-11-10 03:56:35 +08:00
|
|
|
PS test_promoted_load(_Atomic(PS) *addr) {
|
|
|
|
|
// CHECK-LABEL: @test_promoted_load(%struct.PS* noalias sret %agg.result, { %struct.PS, [2 x i8] }* %addr)
|
|
|
|
|
// CHECK: [[ADDR_ARG:%.*]] = alloca { %struct.PS, [2 x i8] }*, align 4
|
|
|
|
|
// CHECK: [[ATOMIC_RES:%.*]] = alloca { %struct.PS, [2 x i8] }, align 8
|
|
|
|
|
// CHECK: store { %struct.PS, [2 x i8] }* %addr, { %struct.PS, [2 x i8] }** [[ADDR_ARG]], align 4
|
|
|
|
|
// CHECK: [[ADDR:%.*]] = load { %struct.PS, [2 x i8] }*, { %struct.PS, [2 x i8] }** [[ADDR_ARG]], align 4
|
|
|
|
|
// CHECK: [[ADDR64:%.*]] = bitcast { %struct.PS, [2 x i8] }* [[ADDR]] to i64*
|
|
|
|
|
// CHECK: [[ATOMIC_RES64:%.*]] = bitcast { %struct.PS, [2 x i8] }* [[ATOMIC_RES]] to i64*
|
|
|
|
|
// CHECK: [[VAL:%.*]] = load atomic i64, i64* [[ADDR64]] seq_cst, align 8
|
|
|
|
|
// CHECK: store i64 [[VAL]], i64* [[ATOMIC_RES64]], align 8
|
|
|
|
|
// CHECK: [[ATOMIC_RES_STRUCT:%.*]] = bitcast i64* [[ATOMIC_RES64]] to %struct.PS*
|
|
|
|
|
// CHECK: [[AGG_RESULT8:%.*]] = bitcast %struct.PS* %agg.result to i8*
|
|
|
|
|
// CHECK: [[ATOMIC_RES8:%.*]] = bitcast %struct.PS* [[ATOMIC_RES_STRUCT]] to i8*
|
2015-11-19 13:55:59 +08:00
|
|
|
// CHECK: call void @llvm.memcpy.p0i8.p0i8.i32(i8* [[AGG_RESULT8]], i8* [[ATOMIC_RES8]], i32 6, i32 2, i1 false)
|
2013-03-08 05:37:17 +08:00
|
|
|
|
2015-11-10 03:56:35 +08:00
|
|
|
return __c11_atomic_load(addr, 5);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void test_promoted_store(_Atomic(PS) *addr, PS *val) {
|
|
|
|
|
// CHECK-LABEL: @test_promoted_store({ %struct.PS, [2 x i8] }* %addr, %struct.PS* %val)
|
|
|
|
|
// CHECK: [[ADDR_ARG:%.*]] = alloca { %struct.PS, [2 x i8] }*, align 4
|
|
|
|
|
// CHECK: [[VAL_ARG:%.*]] = alloca %struct.PS*, align 4
|
|
|
|
|
// CHECK: [[NONATOMIC_TMP:%.*]] = alloca %struct.PS, align 2
|
|
|
|
|
// CHECK: [[ATOMIC_VAL:%.*]] = alloca { %struct.PS, [2 x i8] }, align 8
|
|
|
|
|
// CHECK: store { %struct.PS, [2 x i8] }* %addr, { %struct.PS, [2 x i8] }** [[ADDR_ARG]], align 4
|
|
|
|
|
// CHECK: store %struct.PS* %val, %struct.PS** [[VAL_ARG]], align 4
|
|
|
|
|
// CHECK: [[ADDR:%.*]] = load { %struct.PS, [2 x i8] }*, { %struct.PS, [2 x i8] }** [[ADDR_ARG]], align 4
|
|
|
|
|
// CHECK: [[VAL:%.*]] = load %struct.PS*, %struct.PS** [[VAL_ARG]], align 4
|
|
|
|
|
// CHECK: [[NONATOMIC_TMP8:%.*]] = bitcast %struct.PS* [[NONATOMIC_TMP]] to i8*
|
|
|
|
|
// CHECK: [[VAL8:%.*]] = bitcast %struct.PS* [[VAL]] to i8*
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2015-11-19 13:55:59 +08:00
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// CHECK: call void @llvm.memcpy.p0i8.p0i8.i32(i8* [[NONATOMIC_TMP8]], i8* [[VAL8]], i32 6, i32 2, i1 false)
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2015-11-10 03:56:35 +08:00
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// CHECK: [[ADDR64:%.*]] = bitcast { %struct.PS, [2 x i8] }* [[ADDR]] to i64*
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// CHECK: [[ATOMIC_VAL8:%.*]] = bitcast { %struct.PS, [2 x i8] }* [[ATOMIC_VAL]] to i8*
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// CHECK: [[NONATOMIC_TMP8:%.*]] = bitcast %struct.PS* [[NONATOMIC_TMP]] to i8*
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2015-11-19 13:55:59 +08:00
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// CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[ATOMIC_VAL8]], i8* [[NONATOMIC_TMP8]], i64 6, i32 2, i1 false)
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2015-11-10 03:56:35 +08:00
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// CHECK: [[ATOMIC_VAL64:%.*]] = bitcast { %struct.PS, [2 x i8] }* [[ATOMIC_VAL]] to i64*
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// CHECK: [[VAL64:%.*]] = load i64, i64* [[ATOMIC_VAL64]], align 8
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// CHECK: store atomic i64 [[VAL64]], i64* [[ADDR64]] seq_cst, align 8
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__c11_atomic_store(addr, *val, 5);
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}
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PS test_promoted_exchange(_Atomic(PS) *addr, PS *val) {
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// CHECK-LABEL: @test_promoted_exchange(%struct.PS* noalias sret %agg.result, { %struct.PS, [2 x i8] }* %addr, %struct.PS* %val)
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// CHECK: [[ADDR_ARG:%.*]] = alloca { %struct.PS, [2 x i8] }*, align 4
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// CHECK: [[VAL_ARG:%.*]] = alloca %struct.PS*, align 4
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// CHECK: [[NONATOMIC_TMP:%.*]] = alloca %struct.PS, align 2
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// CHECK: [[ATOMIC_VAL:%.*]] = alloca { %struct.PS, [2 x i8] }, align 8
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// CHECK: [[ATOMIC_RES:%.*]] = alloca { %struct.PS, [2 x i8] }, align 8
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// CHECK: store { %struct.PS, [2 x i8] }* %addr, { %struct.PS, [2 x i8] }** [[ADDR_ARG]], align 4
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// CHECK: store %struct.PS* %val, %struct.PS** [[VAL_ARG]], align 4
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// CHECK: [[ADDR:%.*]] = load { %struct.PS, [2 x i8] }*, { %struct.PS, [2 x i8] }** [[ADDR_ARG]], align 4
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// CHECK: [[VAL:%.*]] = load %struct.PS*, %struct.PS** [[VAL_ARG]], align 4
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// CHECK: [[NONATOMIC_TMP8:%.*]] = bitcast %struct.PS* [[NONATOMIC_TMP]] to i8*
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// CHECK: [[VAL8:%.*]] = bitcast %struct.PS* [[VAL]] to i8*
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2015-11-19 13:55:59 +08:00
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// CHECK: call void @llvm.memcpy.p0i8.p0i8.i32(i8* [[NONATOMIC_TMP8]], i8* [[VAL8]], i32 6, i32 2, i1 false)
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2015-11-10 03:56:35 +08:00
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// CHECK: [[ADDR64:%.*]] = bitcast { %struct.PS, [2 x i8] }* [[ADDR]] to i64*
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// CHECK: [[ATOMIC_VAL8:%.*]] = bitcast { %struct.PS, [2 x i8] }* [[ATOMIC_VAL]] to i8*
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// CHECK: [[NONATOMIC_TMP8:%.*]] = bitcast %struct.PS* [[NONATOMIC_TMP]] to i8*
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2015-11-19 13:55:59 +08:00
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// CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[ATOMIC_VAL8]], i8* [[NONATOMIC_TMP8]], i64 6, i32 2, i1 false)
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2015-11-10 03:56:35 +08:00
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// CHECK: [[ATOMIC_VAL64:%.*]] = bitcast { %struct.PS, [2 x i8] }* [[ATOMIC_VAL]] to i64*
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// CHECK: [[ATOMIC_RES64:%.*]] = bitcast { %struct.PS, [2 x i8] }* [[ATOMIC_RES]] to i64*
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// CHECK: [[VAL64:%.*]] = load i64, i64* [[ATOMIC_VAL64]], align 8
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// CHECK: [[RES:%.*]] = atomicrmw xchg i64* [[ADDR64]], i64 [[VAL64]] seq_cst
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// CHECK: store i64 [[RES]], i64* [[ATOMIC_RES64]], align 8
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// CHECK: [[ATOMIC_RES_STRUCT:%.*]] = bitcast i64* [[ATOMIC_RES64]] to %struct.PS*
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// CHECK: [[AGG_RESULT8:%.*]] = bitcast %struct.PS* %agg.result to i8*
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// CHECK: [[ATOMIC_RES8:%.*]] = bitcast %struct.PS* [[ATOMIC_RES_STRUCT]] to i8*
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2015-11-19 13:55:59 +08:00
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// CHECK: call void @llvm.memcpy.p0i8.p0i8.i32(i8* [[AGG_RESULT8]], i8* [[ATOMIC_RES8]], i32 6, i32 2, i1 false)
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2015-11-10 03:56:35 +08:00
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return __c11_atomic_exchange(addr, *val, 5);
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}
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_Bool test_promoted_cmpxchg(_Atomic(PS) *addr, PS *desired, PS *new) {
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// CHECK: define zeroext i1 @test_promoted_cmpxchg({ %struct.PS, [2 x i8] }* %addr, %struct.PS* %desired, %struct.PS* %new) #0 {
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// CHECK: [[ADDR_ARG:%.*]] = alloca { %struct.PS, [2 x i8] }*, align 4
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// CHECK: [[DESIRED_ARG:%.*]] = alloca %struct.PS*, align 4
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// CHECK: [[NEW_ARG:%.*]] = alloca %struct.PS*, align 4
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// CHECK: [[NONATOMIC_TMP:%.*]] = alloca %struct.PS, align 2
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// CHECK: [[ATOMIC_DESIRED:%.*]] = alloca { %struct.PS, [2 x i8] }, align 8
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// CHECK: [[ATOMIC_NEW:%.*]] = alloca { %struct.PS, [2 x i8] }, align 8
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|
// CHECK: [[RES_ADDR:%.*]] = alloca i8, align 1
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// CHECK: store { %struct.PS, [2 x i8] }* %addr, { %struct.PS, [2 x i8] }** [[ADDR_ARG]], align 4
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// CHECK: store %struct.PS* %desired, %struct.PS** [[DESIRED_ARG]], align 4
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|
// CHECK: store %struct.PS* %new, %struct.PS** [[NEW_ARG]], align 4
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|
// CHECK: [[ADDR:%.*]] = load { %struct.PS, [2 x i8] }*, { %struct.PS, [2 x i8] }** [[ADDR_ARG]], align 4
|
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|
// CHECK: [[DESIRED:%.*]] = load %struct.PS*, %struct.PS** [[DESIRED_ARG]], align 4
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|
// CHECK: [[NEW:%.*]] = load %struct.PS*, %struct.PS** [[NEW_ARG]], align 4
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|
// CHECK: [[NONATOMIC_TMP8:%.*]] = bitcast %struct.PS* [[NONATOMIC_TMP]] to i8*
|
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|
// CHECK: [[NEW8:%.*]] = bitcast %struct.PS* [[NEW]] to i8*
|
2015-11-19 13:55:59 +08:00
|
|
|
// CHECK: call void @llvm.memcpy.p0i8.p0i8.i32(i8* [[NONATOMIC_TMP8]], i8* [[NEW8]], i32 6, i32 2, i1 false)
|
2015-11-10 03:56:35 +08:00
|
|
|
// CHECK: [[ADDR64:%.*]] = bitcast { %struct.PS, [2 x i8] }* [[ADDR]] to i64*
|
|
|
|
|
// CHECK: [[ATOMIC_DESIRED8:%.*]] = bitcast { %struct.PS, [2 x i8] }* [[ATOMIC_DESIRED:%.*]] to i8*
|
|
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|
|
// CHECK: [[DESIRED8:%.*]] = bitcast %struct.PS* [[DESIRED]] to i8*
|
2015-11-19 13:55:59 +08:00
|
|
|
// CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[ATOMIC_DESIRED8]], i8* [[DESIRED8]], i64 6, i32 2, i1 false)
|
2015-11-10 03:56:35 +08:00
|
|
|
// CHECK: [[ATOMIC_DESIRED64:%.*]] = bitcast { %struct.PS, [2 x i8] }* [[ATOMIC_DESIRED:%.*]] to i64*
|
|
|
|
|
// CHECK: [[ATOMIC_NEW8:%.*]] = bitcast { %struct.PS, [2 x i8] }* [[ATOMIC_NEW]] to i8*
|
|
|
|
|
// CHECK: [[NONATOMIC_TMP8:%.*]] = bitcast %struct.PS* [[NONATOMIC_TMP]] to i8*
|
2015-11-19 13:55:59 +08:00
|
|
|
// CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* [[ATOMIC_NEW8]], i8* [[NONATOMIC_TMP8]], i64 6, i32 2, i1 false)
|
2015-11-10 03:56:35 +08:00
|
|
|
// CHECK: [[ATOMIC_NEW64:%.*]] = bitcast { %struct.PS, [2 x i8] }* [[ATOMIC_NEW]] to i64*
|
|
|
|
|
// CHECK: [[ATOMIC_DESIRED_VAL64:%.*]] = load i64, i64* [[ATOMIC_DESIRED64]], align 8
|
|
|
|
|
// CHECK: [[ATOMIC_NEW_VAL64:%.*]] = load i64, i64* [[ATOMIC_NEW64]], align 8
|
|
|
|
|
// CHECK: [[RES:%.*]] = cmpxchg i64* [[ADDR64]], i64 [[ATOMIC_DESIRED_VAL64]], i64 [[ATOMIC_NEW_VAL64]] seq_cst seq_cst
|
|
|
|
|
// CHECK: [[RES_VAL64:%.*]] = extractvalue { i64, i1 } [[RES]], 0
|
|
|
|
|
// CHECK: [[RES_BOOL:%.*]] = extractvalue { i64, i1 } [[RES]], 1
|
|
|
|
|
// CHECK: br i1 [[RES_BOOL]], label {{%.*}}, label {{%.*}}
|
|
|
|
|
|
|
|
|
|
// CHECK: store i64 [[RES_VAL64]], i64* [[ATOMIC_DESIRED64]], align 8
|
|
|
|
|
// CHECK: br label {{%.*}}
|
|
|
|
|
|
|
|
|
|
// CHECK: [[RES_BOOL8:%.*]] = zext i1 [[RES_BOOL]] to i8
|
|
|
|
|
// CHECK: store i8 [[RES_BOOL8]], i8* [[RES_ADDR]], align 1
|
|
|
|
|
// CHECK: [[RES_BOOL8:%.*]] = load i8, i8* [[RES_ADDR]], align 1
|
|
|
|
|
// CHECK: [[RETVAL:%.*]] = trunc i8 [[RES_BOOL8]] to i1
|
|
|
|
|
// CHECK: ret i1 [[RETVAL]]
|
|
|
|
|
|
|
|
|
|
return __c11_atomic_compare_exchange_strong(addr, desired, *new, 5, 5);
|
2013-03-08 05:37:17 +08:00
|
|
|
}
|