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llvm-project/llvm/test/Transforms/InstCombine/sign-test-and-or.ll

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InstCombine: Add a few missing combines for ANDs and ORs of sign bit tests. On x86 we now compile "if (a < 0 && b < 0)" into testl %edi, %esi js IF.THEN llvm-svn: 128496
2011-03-30 06:06:41 +08:00
; RUN: opt -S -instcombine < %s | FileCheck %s
declare void @foo()
define void @test1(i32 %a, i32 %b) nounwind {
%1 = icmp slt i32 %a, 0
%2 = icmp slt i32 %b, 0
%or.cond = or i1 %1, %2
br i1 %or.cond, label %if.then, label %if.end
; CHECK: @test1
; CHECK-NEXT: %1 = or i32 %a, %b
; CHECK-NEXT: %2 = icmp slt i32 %1, 0
; CHECK-NEXT: br
if.then:
tail call void @foo() nounwind
ret void
if.end:
ret void
}
define void @test2(i32 %a, i32 %b) nounwind {
%1 = icmp sgt i32 %a, -1
%2 = icmp sgt i32 %b, -1
%or.cond = or i1 %1, %2
br i1 %or.cond, label %if.then, label %if.end
; CHECK: @test2
; CHECK-NEXT: %1 = and i32 %a, %b
; CHECK-NEXT: %2 = icmp sgt i32 %1, -1
; CHECK-NEXT: br
if.then:
tail call void @foo() nounwind
ret void
if.end:
ret void
}
define void @test3(i32 %a, i32 %b) nounwind {
%1 = icmp slt i32 %a, 0
%2 = icmp slt i32 %b, 0
%or.cond = and i1 %1, %2
br i1 %or.cond, label %if.then, label %if.end
; CHECK: @test3
; CHECK-NEXT: %1 = and i32 %a, %b
; CHECK-NEXT: %2 = icmp slt i32 %1, 0
; CHECK-NEXT: br
if.then:
tail call void @foo() nounwind
ret void
if.end:
ret void
}
define void @test4(i32 %a, i32 %b) nounwind {
%1 = icmp sgt i32 %a, -1
%2 = icmp sgt i32 %b, -1
%or.cond = and i1 %1, %2
br i1 %or.cond, label %if.then, label %if.end
; CHECK: @test4
; CHECK-NEXT: %1 = or i32 %a, %b
; CHECK-NEXT: %2 = icmp sgt i32 %1, -1
; CHECK-NEXT: br
if.then:
tail call void @foo() nounwind
ret void
if.end:
ret void
}
InstCombine: If we have a bit test and a sign test anded/ored together, merge the sign bit into the bit test. This is common in bit field code, e.g. checking if the first or the last bit of a bit field is set. llvm-svn: 147749
2012-01-09 02:32:24 +08:00
define void @test5(i32 %a) nounwind {
%and = and i32 %a, 134217728
%1 = icmp eq i32 %and, 0
%2 = icmp sgt i32 %a, -1
%or.cond = and i1 %1, %2
br i1 %or.cond, label %if.then, label %if.end
; CHECK: @test5
Tweak my last commit to be less conservative about uses. We still save an instruction when just the "and" part is replaced. Also change the code to match comments more closely. llvm-svn: 147753
2012-01-09 05:12:51 +08:00
; CHECK-NEXT: %1 = and i32 %a, -2013265920
; CHECK-NEXT: %2 = icmp eq i32 %1, 0
; CHECK-NEXT: br i1 %2, label %if.then, label %if.end
InstCombine: If we have a bit test and a sign test anded/ored together, merge the sign bit into the bit test. This is common in bit field code, e.g. checking if the first or the last bit of a bit field is set. llvm-svn: 147749
2012-01-09 02:32:24 +08:00
if.then:
tail call void @foo() nounwind
ret void
if.end:
ret void
}
define void @test6(i32 %a) nounwind {
%1 = icmp sgt i32 %a, -1
%and = and i32 %a, 134217728
%2 = icmp eq i32 %and, 0
%or.cond = and i1 %1, %2
br i1 %or.cond, label %if.then, label %if.end
; CHECK: @test6
Tweak my last commit to be less conservative about uses. We still save an instruction when just the "and" part is replaced. Also change the code to match comments more closely. llvm-svn: 147753
2012-01-09 05:12:51 +08:00
; CHECK-NEXT: %1 = and i32 %a, -2013265920
; CHECK-NEXT: %2 = icmp eq i32 %1, 0
; CHECK-NEXT: br i1 %2, label %if.then, label %if.end
InstCombine: If we have a bit test and a sign test anded/ored together, merge the sign bit into the bit test. This is common in bit field code, e.g. checking if the first or the last bit of a bit field is set. llvm-svn: 147749
2012-01-09 02:32:24 +08:00
if.then:
tail call void @foo() nounwind
ret void
if.end:
ret void
}
define void @test7(i32 %a) nounwind {
%and = and i32 %a, 134217728
%1 = icmp ne i32 %and, 0
%2 = icmp slt i32 %a, 0
%or.cond = or i1 %1, %2
br i1 %or.cond, label %if.then, label %if.end
; CHECK: @test7
Tweak my last commit to be less conservative about uses. We still save an instruction when just the "and" part is replaced. Also change the code to match comments more closely. llvm-svn: 147753
2012-01-09 05:12:51 +08:00
; CHECK-NEXT: %1 = and i32 %a, -2013265920
; CHECK-NEXT: %2 = icmp eq i32 %1, 0
; CHECK-NEXT: br i1 %2, label %if.end, label %if.the
InstCombine: If we have a bit test and a sign test anded/ored together, merge the sign bit into the bit test. This is common in bit field code, e.g. checking if the first or the last bit of a bit field is set. llvm-svn: 147749
2012-01-09 02:32:24 +08:00
if.then:
tail call void @foo() nounwind
ret void
if.end:
ret void
}
define void @test8(i32 %a) nounwind {
%1 = icmp slt i32 %a, 0
%and = and i32 %a, 134217728
%2 = icmp ne i32 %and, 0
%or.cond = or i1 %1, %2
br i1 %or.cond, label %if.then, label %if.end
; CHECK: @test8
Tweak my last commit to be less conservative about uses. We still save an instruction when just the "and" part is replaced. Also change the code to match comments more closely. llvm-svn: 147753
2012-01-09 05:12:51 +08:00
; CHECK-NEXT: %1 = and i32 %a, -2013265920
; CHECK-NEXT: %2 = icmp eq i32 %1, 0
; CHECK-NEXT: br i1 %2, label %if.end, label %if.the
InstCombine: If we have a bit test and a sign test anded/ored together, merge the sign bit into the bit test. This is common in bit field code, e.g. checking if the first or the last bit of a bit field is set. llvm-svn: 147749
2012-01-09 02:32:24 +08:00
if.then:
tail call void @foo() nounwind
ret void
if.end:
ret void
}
InstCombine: Teach foldLogOpOfMaskedICmpsHelper that sign bit tests are bit tests. This subsumes several other transforms while enabling us to catch more cases. llvm-svn: 147777
2012-01-10 01:23:27 +08:00
define void @test9(i32 %a) nounwind {
%1 = and i32 %a, 1073741824
%2 = icmp ne i32 %1, 0
%3 = icmp sgt i32 %a, -1
%or.cond = and i1 %2, %3
br i1 %or.cond, label %if.then, label %if.end
; CHECK: @test9
; CHECK-NEXT: %1 = and i32 %a, -1073741824
; CHECK-NEXT: %2 = icmp eq i32 %1, 1073741824
; CHECK-NEXT: br i1 %2, label %if.then, label %if.end
if.then:
tail call void @foo() nounwind
ret void
if.end:
ret void
}