2016-11-02 07:40:28 +08:00
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set(LLVM_TARGET_DEFINITIONS RISCV.td)
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2017-08-08 22:32:35 +08:00
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tablegen(LLVM RISCVGenAsmMatcher.inc -gen-asm-matcher)
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2017-08-15 21:08:29 +08:00
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tablegen(LLVM RISCVGenAsmWriter.inc -gen-asm-writer)
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[RISCV] Tablegen-driven Instruction Compression.
Summary:
This patch implements a tablegen-driven Instruction Compression
mechanism for generating RISCV compressed instructions
(C Extension) from the expanded instruction form.
This tablegen backend processes CompressPat declarations in a
td file and generates all the compile-time and runtime checks
required to validate the declarations, validate the input
operands and generate correct instructions.
The checks include validating register operands, immediate
operands, fixed register operands and fixed immediate operands.
Example:
class CompressPat<dag input, dag output> {
dag Input = input;
dag Output = output;
list<Predicate> Predicates = [];
}
let Predicates = [HasStdExtC] in {
def : CompressPat<(ADD GPRNoX0:$rs1, GPRNoX0:$rs1, GPRNoX0:$rs2),
(C_ADD GPRNoX0:$rs1, GPRNoX0:$rs2)>;
}
The result is an auto-generated header file
'RISCVGenCompressEmitter.inc' which exports two functions for
compressing/uncompressing MCInst instructions, plus
some helper functions:
bool compressInst(MCInst& OutInst, const MCInst &MI,
const MCSubtargetInfo &STI,
MCContext &Context);
bool uncompressInst(MCInst& OutInst, const MCInst &MI,
const MCRegisterInfo &MRI,
const MCSubtargetInfo &STI);
The clients that include this auto-generated header file and
invoke these functions can compress an instruction before emitting
it, in the target-specific ASM or ELF streamer, or can uncompress
an instruction before printing it, when the expanded instruction
format aliases is favored.
The following clients were added to implement compression\uncompression
for RISCV:
1) RISCVAsmParser::MatchAndEmitInstruction:
Inserted a call to compressInst() to compresses instructions
parsed by llvm-mc coming from an ASM input.
2) RISCVAsmPrinter::EmitInstruction:
Inserted a call to compressInst() to compress instructions that
were lowered from Machine Instructions (MachineInstr).
3) RVInstPrinter::printInst:
Inserted a call to uncompressInst() to print the expanded
version of the instruction instead of the compressed one (e.g,
add s0, s0, a5 instead of c.add s0, a5) when -riscv-no-aliases
is not passed.
This patch squashes D45119, D42780 and D41932. It was reviewed in smaller patches by
asb, efriedma, apazos and mgrang.
Reviewers: asb, efriedma, apazos, llvm-commits, sabuasal
Reviewed By: sabuasal
Subscribers: mgorny, eraman, asb, rbar, johnrusso, simoncook, jordy.potman.lists, apazos, niosHD, kito-cheng, shiva0217, zzheng
Differential Revision: https://reviews.llvm.org/D45385
llvm-svn: 329455
2018-04-07 05:07:05 +08:00
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tablegen(LLVM RISCVGenCompressInstEmitter.inc -gen-compress-inst-emitter)
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2017-10-20 05:37:38 +08:00
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tablegen(LLVM RISCVGenDAGISel.inc -gen-dag-isel)
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2017-09-17 22:36:28 +08:00
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tablegen(LLVM RISCVGenDisassemblerTables.inc -gen-disassembler)
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2018-04-04 20:37:44 +08:00
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tablegen(LLVM RISCVGenInstrInfo.inc -gen-instr-info)
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tablegen(LLVM RISCVGenMCCodeEmitter.inc -gen-emitter)
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tablegen(LLVM RISCVGenMCPseudoLowering.inc -gen-pseudo-lowering)
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tablegen(LLVM RISCVGenRegisterInfo.inc -gen-register-info)
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tablegen(LLVM RISCVGenSubtargetInfo.inc -gen-subtarget)
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2016-11-02 07:40:28 +08:00
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add_public_tablegen_target(RISCVCommonTableGen)
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2016-11-02 01:27:54 +08:00
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add_llvm_target(RISCVCodeGen
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2017-10-20 05:37:38 +08:00
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RISCVAsmPrinter.cpp
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RISCVFrameLowering.cpp
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RISCVInstrInfo.cpp
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RISCVISelDAGToDAG.cpp
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RISCVISelLowering.cpp
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RISCVMCInstLower.cpp
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[RISCV] Add machine function pass to merge base + offset
Summary:
In r333455 we added a peephole to fix the corner cases that result
from separating base + offset lowering of global address.The
peephole didn't handle some of the cases because it only has a basic
block view instead of a function level view.
This patch replaces that logic with a machine function pass. In
addition to handling the original cases it handles uses of the global
address across blocks in function and folding an offset from LW\SW
instruction. This pass won't run for OptNone compilation, so there
will be a negative impact overall vs the old approach at O0.
Reviewers: asb, apazos, mgrang
Reviewed By: asb
Subscribers: MartinMosbeck, brucehoult, the_o, rogfer01, mgorny, rbar, johnrusso, simoncook, niosHD, kito-cheng, shiva0217, zzheng, llvm-commits, edward-jones
Differential Revision: https://reviews.llvm.org/D47857
llvm-svn: 335786
2018-06-28 04:51:42 +08:00
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RISCVMergeBaseOffset.cpp
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2017-10-20 05:37:38 +08:00
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RISCVRegisterInfo.cpp
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RISCVSubtarget.cpp
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2016-11-02 01:27:54 +08:00
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RISCVTargetMachine.cpp
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[RISCV] Use init_array instead of ctors for RISCV target, by default
Summary:
LLVM defaults to the newer .init_array/.fini_array scheme for static
constructors rather than the less desirable .ctors/.dtors (the UseCtors
flag defaults to false). This wasn't being respected in the RISC-V
backend because it fails to call TargetLoweringObjectFileELF::InitializeELF with the the appropriate
flag for UseInitArray.
This patch fixes this by implementing RISCVELFTargetObjectFile and overriding its Initialize method to call
InitializeELF(TM.Options.UseInitArray).
Reviewers: asb, apazos
Reviewed By: asb
Subscribers: mgorny, rbar, johnrusso, simoncook, jordy.potman.lists, sabuasal, niosHD, kito-cheng, shiva0217, llvm-commits
Differential Revision: https://reviews.llvm.org/D44750
llvm-svn: 328433
2018-03-25 02:37:19 +08:00
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RISCVTargetObjectFile.cpp
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2016-11-02 01:27:54 +08:00
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)
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2017-08-08 22:32:35 +08:00
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add_subdirectory(AsmParser)
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2017-09-17 22:36:28 +08:00
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add_subdirectory(Disassembler)
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2017-08-15 21:08:29 +08:00
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add_subdirectory(InstPrinter)
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2016-11-02 07:47:30 +08:00
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add_subdirectory(MCTargetDesc)
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2017-08-15 21:08:29 +08:00
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add_subdirectory(TargetInfo)
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