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llvm-project/llvm/test/CodeGen/X86/atomic128.ll

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Regen expected tests result. NFC llvm-svn: 294866
2017-02-12 03:27:15 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
X86: expand atomics in IR instead of as MachineInstrs. The logic for expanding atomics that aren't natively supported in terms of cmpxchg loops is much simpler to express at the IR level. It also allows the normal optimisations and CodeGen improvements to help out with atomics, instead of using a limited set of possible instructions.. rdar://problem/13496295 llvm-svn: 212119
2014-07-02 02:53:31 +08:00
; RUN: llc < %s -mtriple=x86_64-apple-macosx10.9 -verify-machineinstrs -mattr=cx16 | FileCheck %s
[X86] Check for 64-bit mode in X86Subtarget::hasCmpxchg16b() The feature flag alone can't be trusted since it can be passed via -mattr. Need to ensure 64-bit mode as well. We had a 64 bit mode check on the instruction to make the assembler work correctly. But we weren't guarding any of our lowering code or the hooks for the AtomicExpandPass. I've added 32-bit command lines to atomic128.ll with and without cx16. The tests there would all previously fail if -mattr=cx16 was passed to them. I had to move one test case for f128 to a new file as it seems to have a different 32-bit mode or possibly sse issue. Differential Revision: https://reviews.llvm.org/D59308 llvm-svn: 356078
2019-03-14 02:48:50 +08:00
; RUN: llc < %s -mtriple=i386-linux-gnu -verify-machineinstrs -mattr=cx16 | FileCheck %s -check-prefixes=CHECK32
; RUN: llc < %s -mtriple=i386-linux-gnu -verify-machineinstrs -mattr=-cx16 | FileCheck %s -check-prefixes=CHECK32
X86: expand atomics in IR instead of as MachineInstrs. The logic for expanding atomics that aren't natively supported in terms of cmpxchg loops is much simpler to express at the IR level. It also allows the normal optimisations and CodeGen improvements to help out with atomics, instead of using a limited set of possible instructions.. rdar://problem/13496295 llvm-svn: 212119
2014-07-02 02:53:31 +08:00
@var = global i128 0
[X86] Make sure we do not clobber RBX with cmpxchg when used as a base pointer. cmpxchg[8|16]b uses RBX as one of its argument. In other words, using this instruction clobbers RBX as it is defined to hold one the input. When the backend uses dynamically allocated stack, RBX is used as a reserved register for the base pointer. Reserved registers have special semantic that only the target understands and enforces, because of that, the register allocator don’t use them, but also, don’t try to make sure they are used properly (remember it does not know how they are supposed to be used). Therefore, when RBX is used as a reserved register but defined by something that is not compatible with that use, the register allocator will not fix the surrounding code to make sure it gets saved and restored properly around the broken code. This is the responsibility of the target to do the right thing with its reserved register. To fix that, when the base pointer needs to be preserved, we use a different pseudo instruction for cmpxchg that save rbx. That pseudo takes two more arguments than the regular instruction: - One is the value to be copied into RBX to set the proper value for the comparison. - The other is the virtual register holding the save of the value of RBX as the base pointer. This saving is done as part of isel (i.e., we emit a copy from rbx). cmpxchg_save_rbx <regular cmpxchg args>, input_for_rbx_reg, save_of_rbx_as_bp This gets expanded into: rbx = copy input_for_rbx_reg cmpxchg <regular cmpxchg args> rbx = save_of_rbx_as_bp Note: The actual modeling of the pseudo is a bit more complicated to make sure the interferes that appears after the pseudo gets expanded are properly modeled before that expansion. This fixes PR26883. llvm-svn: 263325
2016-03-12 10:25:27 +08:00
; Due to the scheduling right after isel for cmpxchg and given the
; machine scheduler and copy coalescer do not mess up with physical
; register live-ranges, we end up with a useless copy.
Regen expected tests result. NFC llvm-svn: 294866
2017-02-12 03:27:15 +08:00
define i128 @val_compare_and_swap(i128* %p, i128 %oldval, i128 %newval) {
; CHECK-LABEL: val_compare_and_swap:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; CHECK: ## %bb.0:
Regen expected tests result. NFC llvm-svn: 294866
2017-02-12 03:27:15 +08:00
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbx, -16
[X86] Handle COPYs of physregs better (regalloc hints) Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
2018-09-20 02:59:08 +08:00
; CHECK-NEXT: movq %rcx, %rbx
Regen expected tests result. NFC llvm-svn: 294866
2017-02-12 03:27:15 +08:00
; CHECK-NEXT: movq %rsi, %rax
; CHECK-NEXT: movq %r8, %rcx
; CHECK-NEXT: lock cmpxchg16b (%rdi)
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: retq
[X86] Check for 64-bit mode in X86Subtarget::hasCmpxchg16b() The feature flag alone can't be trusted since it can be passed via -mattr. Need to ensure 64-bit mode as well. We had a 64 bit mode check on the instruction to make the assembler work correctly. But we weren't guarding any of our lowering code or the hooks for the AtomicExpandPass. I've added 32-bit command lines to atomic128.ll with and without cx16. The tests there would all previously fail if -mattr=cx16 was passed to them. I had to move one test case for f128 to a new file as it seems to have a different 32-bit mode or possibly sse issue. Differential Revision: https://reviews.llvm.org/D59308 llvm-svn: 356078
2019-03-14 02:48:50 +08:00
;
; CHECK32-LABEL: val_compare_and_swap:
; CHECK32: # %bb.0:
; CHECK32-NEXT: pushl %edi
; CHECK32-NEXT: .cfi_def_cfa_offset 8
; CHECK32-NEXT: pushl %esi
; CHECK32-NEXT: .cfi_def_cfa_offset 12
; CHECK32-NEXT: subl $20, %esp
; CHECK32-NEXT: .cfi_def_cfa_offset 32
; CHECK32-NEXT: .cfi_offset %esi, -12
; CHECK32-NEXT: .cfi_offset %edi, -8
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %esi
; CHECK32-NEXT: subl $8, %esp
; CHECK32-NEXT: .cfi_adjust_cfa_offset 8
; CHECK32-NEXT: leal {{[0-9]+}}(%esp), %eax
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl %eax
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: calll __sync_val_compare_and_swap_16
; CHECK32-NEXT: .cfi_adjust_cfa_offset -4
; CHECK32-NEXT: addl $44, %esp
; CHECK32-NEXT: .cfi_adjust_cfa_offset -44
; CHECK32-NEXT: movl (%esp), %eax
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %edx
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %edi
; CHECK32-NEXT: movl %edi, 8(%esi)
; CHECK32-NEXT: movl %edx, 12(%esi)
; CHECK32-NEXT: movl %eax, (%esi)
; CHECK32-NEXT: movl %ecx, 4(%esi)
; CHECK32-NEXT: movl %esi, %eax
; CHECK32-NEXT: addl $20, %esp
; CHECK32-NEXT: .cfi_def_cfa_offset 12
; CHECK32-NEXT: popl %esi
; CHECK32-NEXT: .cfi_def_cfa_offset 8
; CHECK32-NEXT: popl %edi
; CHECK32-NEXT: .cfi_def_cfa_offset 4
; CHECK32-NEXT: retl $4
X86: expand atomics in IR instead of as MachineInstrs. The logic for expanding atomics that aren't natively supported in terms of cmpxchg loops is much simpler to express at the IR level. It also allows the normal optimisations and CodeGen improvements to help out with atomics, instead of using a limited set of possible instructions.. rdar://problem/13496295 llvm-svn: 212119
2014-07-02 02:53:31 +08:00
%pair = cmpxchg i128* %p, i128 %oldval, i128 %newval acquire acquire
%val = extractvalue { i128, i1 } %pair, 0
ret i128 %val
}
[X86][test] Add a regression test for lock cmpxchg16b on a global variable with offset Add a test for a bug (uncovered by D88808) fixed by f34bb06935aa3bab353d70d515b767fdd2f5625c. Also delete cmpxchg16b.ll which is covered by atomic128.ll Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D89163
2020-10-10 05:51:45 +08:00
@cmpxchg16b_global = external dso_local global { i128, i128 }, align 16
;; Make sure we retain the offset of the global variable.
define void @cmpxchg16b_global_with_offset() nounwind {
; CHECK-LABEL: cmpxchg16b_global_with_offset:
; CHECK: ## %bb.0: ## %entry
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: xorl %ebx, %ebx
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated The motivation is that the update script has at least two deviations (`<...>@GOT`/`<...>@PLT`/ and not hiding pointer arithmetics) from what pretty much all the checklines were generated with, and most of the tests are still not updated, so each time one of the non-up-to-date tests is updated to see the effect of the code change, there is a lot of noise. Instead of having to deal with that each time, let's just deal with everything at once. This has been done via: ``` cd llvm-project/llvm/test/CodeGen/X86 grep -rl "; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py" | xargs -L1 <...>/llvm-project/llvm/utils/update_llc_test_checks.py --llc-binary <...>/llvm-project/build/bin/llc ``` Not all tests were regenerated, however.
2021-06-12 04:26:17 +08:00
; CHECK-NEXT: lock cmpxchg16b _cmpxchg16b_global+16(%rip)
[X86][test] Add a regression test for lock cmpxchg16b on a global variable with offset Add a test for a bug (uncovered by D88808) fixed by f34bb06935aa3bab353d70d515b767fdd2f5625c. Also delete cmpxchg16b.ll which is covered by atomic128.ll Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D89163
2020-10-10 05:51:45 +08:00
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: retq
;
; CHECK32-LABEL: cmpxchg16b_global_with_offset:
; CHECK32: # %bb.0: # %entry
; CHECK32-NEXT: subl $36, %esp
; CHECK32-NEXT: leal {{[0-9]+}}(%esp), %eax
; CHECK32-NEXT: pushl $0
; CHECK32-NEXT: pushl $0
; CHECK32-NEXT: pushl $0
; CHECK32-NEXT: pushl $0
; CHECK32-NEXT: pushl $0
; CHECK32-NEXT: pushl $0
; CHECK32-NEXT: pushl $0
; CHECK32-NEXT: pushl $0
; CHECK32-NEXT: pushl $cmpxchg16b_global+16
; CHECK32-NEXT: pushl %eax
; CHECK32-NEXT: calll __sync_val_compare_and_swap_16
; CHECK32-NEXT: addl $72, %esp
; CHECK32-NEXT: retl
entry:
%0 = load atomic i128, i128* getelementptr inbounds ({i128, i128}, {i128, i128}* @cmpxchg16b_global, i64 0, i32 1) acquire, align 16
ret void
}
X86: expand atomics in IR instead of as MachineInstrs. The logic for expanding atomics that aren't natively supported in terms of cmpxchg loops is much simpler to express at the IR level. It also allows the normal optimisations and CodeGen improvements to help out with atomics, instead of using a limited set of possible instructions.. rdar://problem/13496295 llvm-svn: 212119
2014-07-02 02:53:31 +08:00
define void @fetch_and_nand(i128* %p, i128 %bits) {
; CHECK-LABEL: fetch_and_nand:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; CHECK: ## %bb.0:
Regen expected tests result. NFC llvm-svn: 294866
2017-02-12 03:27:15 +08:00
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdx, %r8
; CHECK-NEXT: movq (%rdi), %rax
; CHECK-NEXT: movq 8(%rdi), %rdx
; CHECK-NEXT: .p2align 4, 0x90
[X86][test] Add a regression test for lock cmpxchg16b on a global variable with offset Add a test for a bug (uncovered by D88808) fixed by f34bb06935aa3bab353d70d515b767fdd2f5625c. Also delete cmpxchg16b.ll which is covered by atomic128.ll Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D89163
2020-10-10 05:51:45 +08:00
; CHECK-NEXT: LBB2_1: ## %atomicrmw.start
Regen expected tests result. NFC llvm-svn: 294866
2017-02-12 03:27:15 +08:00
; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
; CHECK-NEXT: movq %rdx, %rcx
; CHECK-NEXT: andq %r8, %rcx
; CHECK-NEXT: movq %rax, %rbx
; CHECK-NEXT: andq %rsi, %rbx
; CHECK-NEXT: notq %rbx
; CHECK-NEXT: notq %rcx
; CHECK-NEXT: lock cmpxchg16b (%rdi)
[X86][test] Add a regression test for lock cmpxchg16b on a global variable with offset Add a test for a bug (uncovered by D88808) fixed by f34bb06935aa3bab353d70d515b767fdd2f5625c. Also delete cmpxchg16b.ll which is covered by atomic128.ll Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D89163
2020-10-10 05:51:45 +08:00
; CHECK-NEXT: jne LBB2_1
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; CHECK-NEXT: ## %bb.2: ## %atomicrmw.end
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated The motivation is that the update script has at least two deviations (`<...>@GOT`/`<...>@PLT`/ and not hiding pointer arithmetics) from what pretty much all the checklines were generated with, and most of the tests are still not updated, so each time one of the non-up-to-date tests is updated to see the effect of the code change, there is a lot of noise. Instead of having to deal with that each time, let's just deal with everything at once. This has been done via: ``` cd llvm-project/llvm/test/CodeGen/X86 grep -rl "; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py" | xargs -L1 <...>/llvm-project/llvm/utils/update_llc_test_checks.py --llc-binary <...>/llvm-project/build/bin/llc ``` Not all tests were regenerated, however.
2021-06-12 04:26:17 +08:00
; CHECK-NEXT: movq %rax, _var(%rip)
; CHECK-NEXT: movq %rdx, _var+8(%rip)
Regen expected tests result. NFC llvm-svn: 294866
2017-02-12 03:27:15 +08:00
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: retq
[X86] Check for 64-bit mode in X86Subtarget::hasCmpxchg16b() The feature flag alone can't be trusted since it can be passed via -mattr. Need to ensure 64-bit mode as well. We had a 64 bit mode check on the instruction to make the assembler work correctly. But we weren't guarding any of our lowering code or the hooks for the AtomicExpandPass. I've added 32-bit command lines to atomic128.ll with and without cx16. The tests there would all previously fail if -mattr=cx16 was passed to them. I had to move one test case for f128 to a new file as it seems to have a different 32-bit mode or possibly sse issue. Differential Revision: https://reviews.llvm.org/D59308 llvm-svn: 356078
2019-03-14 02:48:50 +08:00
;
; CHECK32-LABEL: fetch_and_nand:
; CHECK32: # %bb.0:
; CHECK32-NEXT: pushl %esi
; CHECK32-NEXT: .cfi_def_cfa_offset 8
; CHECK32-NEXT: subl $24, %esp
; CHECK32-NEXT: .cfi_def_cfa_offset 32
; CHECK32-NEXT: .cfi_offset %esi, -8
; CHECK32-NEXT: subl $8, %esp
; CHECK32-NEXT: .cfi_adjust_cfa_offset 8
; CHECK32-NEXT: leal {{[0-9]+}}(%esp), %eax
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl %eax
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: calll __sync_fetch_and_nand_16
; CHECK32-NEXT: .cfi_adjust_cfa_offset -4
; CHECK32-NEXT: addl $28, %esp
; CHECK32-NEXT: .cfi_adjust_cfa_offset -28
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %edx
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %esi
; CHECK32-NEXT: movl %esi, var+8
; CHECK32-NEXT: movl %edx, var+12
; CHECK32-NEXT: movl %eax, var
; CHECK32-NEXT: movl %ecx, var+4
; CHECK32-NEXT: addl $24, %esp
; CHECK32-NEXT: .cfi_def_cfa_offset 8
; CHECK32-NEXT: popl %esi
; CHECK32-NEXT: .cfi_def_cfa_offset 4
; CHECK32-NEXT: retl
X86: expand atomics in IR instead of as MachineInstrs. The logic for expanding atomics that aren't natively supported in terms of cmpxchg loops is much simpler to express at the IR level. It also allows the normal optimisations and CodeGen improvements to help out with atomics, instead of using a limited set of possible instructions.. rdar://problem/13496295 llvm-svn: 212119
2014-07-02 02:53:31 +08:00
%val = atomicrmw nand i128* %p, i128 %bits release
store i128 %val, i128* @var, align 16
ret void
}
define void @fetch_and_or(i128* %p, i128 %bits) {
; CHECK-LABEL: fetch_and_or:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; CHECK: ## %bb.0:
Regen expected tests result. NFC llvm-svn: 294866
2017-02-12 03:27:15 +08:00
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdx, %r8
; CHECK-NEXT: movq (%rdi), %rax
; CHECK-NEXT: movq 8(%rdi), %rdx
; CHECK-NEXT: .p2align 4, 0x90
[X86][test] Add a regression test for lock cmpxchg16b on a global variable with offset Add a test for a bug (uncovered by D88808) fixed by f34bb06935aa3bab353d70d515b767fdd2f5625c. Also delete cmpxchg16b.ll which is covered by atomic128.ll Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D89163
2020-10-10 05:51:45 +08:00
; CHECK-NEXT: LBB3_1: ## %atomicrmw.start
Regen expected tests result. NFC llvm-svn: 294866
2017-02-12 03:27:15 +08:00
; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
; CHECK-NEXT: movq %rax, %rbx
; CHECK-NEXT: orq %rsi, %rbx
; CHECK-NEXT: movq %rdx, %rcx
; CHECK-NEXT: orq %r8, %rcx
; CHECK-NEXT: lock cmpxchg16b (%rdi)
[X86][test] Add a regression test for lock cmpxchg16b on a global variable with offset Add a test for a bug (uncovered by D88808) fixed by f34bb06935aa3bab353d70d515b767fdd2f5625c. Also delete cmpxchg16b.ll which is covered by atomic128.ll Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D89163
2020-10-10 05:51:45 +08:00
; CHECK-NEXT: jne LBB3_1
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; CHECK-NEXT: ## %bb.2: ## %atomicrmw.end
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated The motivation is that the update script has at least two deviations (`<...>@GOT`/`<...>@PLT`/ and not hiding pointer arithmetics) from what pretty much all the checklines were generated with, and most of the tests are still not updated, so each time one of the non-up-to-date tests is updated to see the effect of the code change, there is a lot of noise. Instead of having to deal with that each time, let's just deal with everything at once. This has been done via: ``` cd llvm-project/llvm/test/CodeGen/X86 grep -rl "; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py" | xargs -L1 <...>/llvm-project/llvm/utils/update_llc_test_checks.py --llc-binary <...>/llvm-project/build/bin/llc ``` Not all tests were regenerated, however.
2021-06-12 04:26:17 +08:00
; CHECK-NEXT: movq %rax, _var(%rip)
; CHECK-NEXT: movq %rdx, _var+8(%rip)
Regen expected tests result. NFC llvm-svn: 294866
2017-02-12 03:27:15 +08:00
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: retq
[X86] Check for 64-bit mode in X86Subtarget::hasCmpxchg16b() The feature flag alone can't be trusted since it can be passed via -mattr. Need to ensure 64-bit mode as well. We had a 64 bit mode check on the instruction to make the assembler work correctly. But we weren't guarding any of our lowering code or the hooks for the AtomicExpandPass. I've added 32-bit command lines to atomic128.ll with and without cx16. The tests there would all previously fail if -mattr=cx16 was passed to them. I had to move one test case for f128 to a new file as it seems to have a different 32-bit mode or possibly sse issue. Differential Revision: https://reviews.llvm.org/D59308 llvm-svn: 356078
2019-03-14 02:48:50 +08:00
;
; CHECK32-LABEL: fetch_and_or:
; CHECK32: # %bb.0:
; CHECK32-NEXT: pushl %esi
; CHECK32-NEXT: .cfi_def_cfa_offset 8
; CHECK32-NEXT: subl $24, %esp
; CHECK32-NEXT: .cfi_def_cfa_offset 32
; CHECK32-NEXT: .cfi_offset %esi, -8
; CHECK32-NEXT: subl $8, %esp
; CHECK32-NEXT: .cfi_adjust_cfa_offset 8
; CHECK32-NEXT: leal {{[0-9]+}}(%esp), %eax
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl %eax
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: calll __sync_fetch_and_or_16
; CHECK32-NEXT: .cfi_adjust_cfa_offset -4
; CHECK32-NEXT: addl $28, %esp
; CHECK32-NEXT: .cfi_adjust_cfa_offset -28
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %edx
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %esi
; CHECK32-NEXT: movl %esi, var+8
; CHECK32-NEXT: movl %edx, var+12
; CHECK32-NEXT: movl %eax, var
; CHECK32-NEXT: movl %ecx, var+4
; CHECK32-NEXT: addl $24, %esp
; CHECK32-NEXT: .cfi_def_cfa_offset 8
; CHECK32-NEXT: popl %esi
; CHECK32-NEXT: .cfi_def_cfa_offset 4
; CHECK32-NEXT: retl
X86: expand atomics in IR instead of as MachineInstrs. The logic for expanding atomics that aren't natively supported in terms of cmpxchg loops is much simpler to express at the IR level. It also allows the normal optimisations and CodeGen improvements to help out with atomics, instead of using a limited set of possible instructions.. rdar://problem/13496295 llvm-svn: 212119
2014-07-02 02:53:31 +08:00
%val = atomicrmw or i128* %p, i128 %bits seq_cst
store i128 %val, i128* @var, align 16
ret void
}
define void @fetch_and_add(i128* %p, i128 %bits) {
; CHECK-LABEL: fetch_and_add:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; CHECK: ## %bb.0:
Regen expected tests result. NFC llvm-svn: 294866
2017-02-12 03:27:15 +08:00
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdx, %r8
; CHECK-NEXT: movq (%rdi), %rax
; CHECK-NEXT: movq 8(%rdi), %rdx
; CHECK-NEXT: .p2align 4, 0x90
[X86][test] Add a regression test for lock cmpxchg16b on a global variable with offset Add a test for a bug (uncovered by D88808) fixed by f34bb06935aa3bab353d70d515b767fdd2f5625c. Also delete cmpxchg16b.ll which is covered by atomic128.ll Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D89163
2020-10-10 05:51:45 +08:00
; CHECK-NEXT: LBB4_1: ## %atomicrmw.start
Regen expected tests result. NFC llvm-svn: 294866
2017-02-12 03:27:15 +08:00
; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
; CHECK-NEXT: movq %rax, %rbx
; CHECK-NEXT: addq %rsi, %rbx
; CHECK-NEXT: movq %rdx, %rcx
; CHECK-NEXT: adcq %r8, %rcx
; CHECK-NEXT: lock cmpxchg16b (%rdi)
[X86][test] Add a regression test for lock cmpxchg16b on a global variable with offset Add a test for a bug (uncovered by D88808) fixed by f34bb06935aa3bab353d70d515b767fdd2f5625c. Also delete cmpxchg16b.ll which is covered by atomic128.ll Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D89163
2020-10-10 05:51:45 +08:00
; CHECK-NEXT: jne LBB4_1
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; CHECK-NEXT: ## %bb.2: ## %atomicrmw.end
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated The motivation is that the update script has at least two deviations (`<...>@GOT`/`<...>@PLT`/ and not hiding pointer arithmetics) from what pretty much all the checklines were generated with, and most of the tests are still not updated, so each time one of the non-up-to-date tests is updated to see the effect of the code change, there is a lot of noise. Instead of having to deal with that each time, let's just deal with everything at once. This has been done via: ``` cd llvm-project/llvm/test/CodeGen/X86 grep -rl "; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py" | xargs -L1 <...>/llvm-project/llvm/utils/update_llc_test_checks.py --llc-binary <...>/llvm-project/build/bin/llc ``` Not all tests were regenerated, however.
2021-06-12 04:26:17 +08:00
; CHECK-NEXT: movq %rax, _var(%rip)
; CHECK-NEXT: movq %rdx, _var+8(%rip)
Regen expected tests result. NFC llvm-svn: 294866
2017-02-12 03:27:15 +08:00
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: retq
[X86] Check for 64-bit mode in X86Subtarget::hasCmpxchg16b() The feature flag alone can't be trusted since it can be passed via -mattr. Need to ensure 64-bit mode as well. We had a 64 bit mode check on the instruction to make the assembler work correctly. But we weren't guarding any of our lowering code or the hooks for the AtomicExpandPass. I've added 32-bit command lines to atomic128.ll with and without cx16. The tests there would all previously fail if -mattr=cx16 was passed to them. I had to move one test case for f128 to a new file as it seems to have a different 32-bit mode or possibly sse issue. Differential Revision: https://reviews.llvm.org/D59308 llvm-svn: 356078
2019-03-14 02:48:50 +08:00
;
; CHECK32-LABEL: fetch_and_add:
; CHECK32: # %bb.0:
; CHECK32-NEXT: pushl %esi
; CHECK32-NEXT: .cfi_def_cfa_offset 8
; CHECK32-NEXT: subl $24, %esp
; CHECK32-NEXT: .cfi_def_cfa_offset 32
; CHECK32-NEXT: .cfi_offset %esi, -8
; CHECK32-NEXT: subl $8, %esp
; CHECK32-NEXT: .cfi_adjust_cfa_offset 8
; CHECK32-NEXT: leal {{[0-9]+}}(%esp), %eax
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl %eax
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: calll __sync_fetch_and_add_16
; CHECK32-NEXT: .cfi_adjust_cfa_offset -4
; CHECK32-NEXT: addl $28, %esp
; CHECK32-NEXT: .cfi_adjust_cfa_offset -28
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %edx
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %esi
; CHECK32-NEXT: movl %esi, var+8
; CHECK32-NEXT: movl %edx, var+12
; CHECK32-NEXT: movl %eax, var
; CHECK32-NEXT: movl %ecx, var+4
; CHECK32-NEXT: addl $24, %esp
; CHECK32-NEXT: .cfi_def_cfa_offset 8
; CHECK32-NEXT: popl %esi
; CHECK32-NEXT: .cfi_def_cfa_offset 4
; CHECK32-NEXT: retl
X86: expand atomics in IR instead of as MachineInstrs. The logic for expanding atomics that aren't natively supported in terms of cmpxchg loops is much simpler to express at the IR level. It also allows the normal optimisations and CodeGen improvements to help out with atomics, instead of using a limited set of possible instructions.. rdar://problem/13496295 llvm-svn: 212119
2014-07-02 02:53:31 +08:00
%val = atomicrmw add i128* %p, i128 %bits seq_cst
store i128 %val, i128* @var, align 16
ret void
}
define void @fetch_and_sub(i128* %p, i128 %bits) {
; CHECK-LABEL: fetch_and_sub:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; CHECK: ## %bb.0:
Regen expected tests result. NFC llvm-svn: 294866
2017-02-12 03:27:15 +08:00
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdx, %r8
; CHECK-NEXT: movq (%rdi), %rax
; CHECK-NEXT: movq 8(%rdi), %rdx
; CHECK-NEXT: .p2align 4, 0x90
[X86][test] Add a regression test for lock cmpxchg16b on a global variable with offset Add a test for a bug (uncovered by D88808) fixed by f34bb06935aa3bab353d70d515b767fdd2f5625c. Also delete cmpxchg16b.ll which is covered by atomic128.ll Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D89163
2020-10-10 05:51:45 +08:00
; CHECK-NEXT: LBB5_1: ## %atomicrmw.start
Regen expected tests result. NFC llvm-svn: 294866
2017-02-12 03:27:15 +08:00
; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
; CHECK-NEXT: movq %rax, %rbx
; CHECK-NEXT: subq %rsi, %rbx
; CHECK-NEXT: movq %rdx, %rcx
; CHECK-NEXT: sbbq %r8, %rcx
; CHECK-NEXT: lock cmpxchg16b (%rdi)
[X86][test] Add a regression test for lock cmpxchg16b on a global variable with offset Add a test for a bug (uncovered by D88808) fixed by f34bb06935aa3bab353d70d515b767fdd2f5625c. Also delete cmpxchg16b.ll which is covered by atomic128.ll Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D89163
2020-10-10 05:51:45 +08:00
; CHECK-NEXT: jne LBB5_1
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; CHECK-NEXT: ## %bb.2: ## %atomicrmw.end
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated The motivation is that the update script has at least two deviations (`<...>@GOT`/`<...>@PLT`/ and not hiding pointer arithmetics) from what pretty much all the checklines were generated with, and most of the tests are still not updated, so each time one of the non-up-to-date tests is updated to see the effect of the code change, there is a lot of noise. Instead of having to deal with that each time, let's just deal with everything at once. This has been done via: ``` cd llvm-project/llvm/test/CodeGen/X86 grep -rl "; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py" | xargs -L1 <...>/llvm-project/llvm/utils/update_llc_test_checks.py --llc-binary <...>/llvm-project/build/bin/llc ``` Not all tests were regenerated, however.
2021-06-12 04:26:17 +08:00
; CHECK-NEXT: movq %rax, _var(%rip)
; CHECK-NEXT: movq %rdx, _var+8(%rip)
Regen expected tests result. NFC llvm-svn: 294866
2017-02-12 03:27:15 +08:00
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: retq
[X86] Check for 64-bit mode in X86Subtarget::hasCmpxchg16b() The feature flag alone can't be trusted since it can be passed via -mattr. Need to ensure 64-bit mode as well. We had a 64 bit mode check on the instruction to make the assembler work correctly. But we weren't guarding any of our lowering code or the hooks for the AtomicExpandPass. I've added 32-bit command lines to atomic128.ll with and without cx16. The tests there would all previously fail if -mattr=cx16 was passed to them. I had to move one test case for f128 to a new file as it seems to have a different 32-bit mode or possibly sse issue. Differential Revision: https://reviews.llvm.org/D59308 llvm-svn: 356078
2019-03-14 02:48:50 +08:00
;
; CHECK32-LABEL: fetch_and_sub:
; CHECK32: # %bb.0:
; CHECK32-NEXT: pushl %esi
; CHECK32-NEXT: .cfi_def_cfa_offset 8
; CHECK32-NEXT: subl $24, %esp
; CHECK32-NEXT: .cfi_def_cfa_offset 32
; CHECK32-NEXT: .cfi_offset %esi, -8
; CHECK32-NEXT: subl $8, %esp
; CHECK32-NEXT: .cfi_adjust_cfa_offset 8
; CHECK32-NEXT: leal {{[0-9]+}}(%esp), %eax
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl %eax
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: calll __sync_fetch_and_sub_16
; CHECK32-NEXT: .cfi_adjust_cfa_offset -4
; CHECK32-NEXT: addl $28, %esp
; CHECK32-NEXT: .cfi_adjust_cfa_offset -28
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %edx
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %esi
; CHECK32-NEXT: movl %esi, var+8
; CHECK32-NEXT: movl %edx, var+12
; CHECK32-NEXT: movl %eax, var
; CHECK32-NEXT: movl %ecx, var+4
; CHECK32-NEXT: addl $24, %esp
; CHECK32-NEXT: .cfi_def_cfa_offset 8
; CHECK32-NEXT: popl %esi
; CHECK32-NEXT: .cfi_def_cfa_offset 4
; CHECK32-NEXT: retl
X86: expand atomics in IR instead of as MachineInstrs. The logic for expanding atomics that aren't natively supported in terms of cmpxchg loops is much simpler to express at the IR level. It also allows the normal optimisations and CodeGen improvements to help out with atomics, instead of using a limited set of possible instructions.. rdar://problem/13496295 llvm-svn: 212119
2014-07-02 02:53:31 +08:00
%val = atomicrmw sub i128* %p, i128 %bits seq_cst
store i128 %val, i128* @var, align 16
ret void
}
define void @fetch_and_min(i128* %p, i128 %bits) {
; CHECK-LABEL: fetch_and_min:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; CHECK: ## %bb.0:
Regen expected tests result. NFC llvm-svn: 294866
2017-02-12 03:27:15 +08:00
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdx, %r8
; CHECK-NEXT: movq (%rdi), %rax
; CHECK-NEXT: movq 8(%rdi), %rdx
; CHECK-NEXT: .p2align 4, 0x90
[X86][test] Add a regression test for lock cmpxchg16b on a global variable with offset Add a test for a bug (uncovered by D88808) fixed by f34bb06935aa3bab353d70d515b767fdd2f5625c. Also delete cmpxchg16b.ll which is covered by atomic128.ll Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D89163
2020-10-10 05:51:45 +08:00
; CHECK-NEXT: LBB6_1: ## %atomicrmw.start
Regen expected tests result. NFC llvm-svn: 294866
2017-02-12 03:27:15 +08:00
; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
; CHECK-NEXT: cmpq %rax, %rsi
; CHECK-NEXT: movq %r8, %rcx
; CHECK-NEXT: sbbq %rdx, %rcx
; CHECK-NEXT: movq %r8, %rcx
[x86] Fix an amazing goof in the handling of sub, or, and xor lowering. The comment for this code indicated that it should work similar to our handling of add lowering above: if we see uses of an instruction other than flag usage and store usage, it tries to avoid the specialized X86ISD::* nodes that are designed for flag+op modeling and emits an explicit test. Problem is, only the add case actually did this. In all the other cases, the logic was incomplete and inverted. Any time the value was used by a store, we bailed on the specialized X86ISD node. All of this appears to have been historical where we had different logic here. =/ Turns out, we have quite a few patterns designed around these nodes. We should actually form them. I fixed the code to match what we do for add, and it has quite a positive effect just within some of our test cases. The only thing close to a regression I see is using: notl %r testl %r, %r instead of: xorl -1, %r But we can add a pattern or something to fold that back out. The improvements seem more than worth this. I've also worked with Craig to update the comments to no longer be actively contradicted by the code. =[ Some of this still remains a mystery to both Craig and myself, but this seems like a large step in the direction of consistency and slightly more accurate comments. Many thanks to Craig for help figuring out this nasty stuff. Differential Revision: https://reviews.llvm.org/D37096 llvm-svn: 311737
2017-08-25 08:34:07 +08:00
; CHECK-NEXT: cmovgeq %rdx, %rcx
; CHECK-NEXT: movq %rsi, %rbx
; CHECK-NEXT: cmovgeq %rax, %rbx
Regen expected tests result. NFC llvm-svn: 294866
2017-02-12 03:27:15 +08:00
; CHECK-NEXT: lock cmpxchg16b (%rdi)
[X86][test] Add a regression test for lock cmpxchg16b on a global variable with offset Add a test for a bug (uncovered by D88808) fixed by f34bb06935aa3bab353d70d515b767fdd2f5625c. Also delete cmpxchg16b.ll which is covered by atomic128.ll Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D89163
2020-10-10 05:51:45 +08:00
; CHECK-NEXT: jne LBB6_1
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; CHECK-NEXT: ## %bb.2: ## %atomicrmw.end
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated The motivation is that the update script has at least two deviations (`<...>@GOT`/`<...>@PLT`/ and not hiding pointer arithmetics) from what pretty much all the checklines were generated with, and most of the tests are still not updated, so each time one of the non-up-to-date tests is updated to see the effect of the code change, there is a lot of noise. Instead of having to deal with that each time, let's just deal with everything at once. This has been done via: ``` cd llvm-project/llvm/test/CodeGen/X86 grep -rl "; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py" | xargs -L1 <...>/llvm-project/llvm/utils/update_llc_test_checks.py --llc-binary <...>/llvm-project/build/bin/llc ``` Not all tests were regenerated, however.
2021-06-12 04:26:17 +08:00
; CHECK-NEXT: movq %rax, _var(%rip)
; CHECK-NEXT: movq %rdx, _var+8(%rip)
Regen expected tests result. NFC llvm-svn: 294866
2017-02-12 03:27:15 +08:00
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: retq
[X86] Check for 64-bit mode in X86Subtarget::hasCmpxchg16b() The feature flag alone can't be trusted since it can be passed via -mattr. Need to ensure 64-bit mode as well. We had a 64 bit mode check on the instruction to make the assembler work correctly. But we weren't guarding any of our lowering code or the hooks for the AtomicExpandPass. I've added 32-bit command lines to atomic128.ll with and without cx16. The tests there would all previously fail if -mattr=cx16 was passed to them. I had to move one test case for f128 to a new file as it seems to have a different 32-bit mode or possibly sse issue. Differential Revision: https://reviews.llvm.org/D59308 llvm-svn: 356078
2019-03-14 02:48:50 +08:00
;
; CHECK32-LABEL: fetch_and_min:
; CHECK32: # %bb.0:
; CHECK32-NEXT: pushl %esi
; CHECK32-NEXT: .cfi_def_cfa_offset 8
; CHECK32-NEXT: subl $24, %esp
; CHECK32-NEXT: .cfi_def_cfa_offset 32
; CHECK32-NEXT: .cfi_offset %esi, -8
; CHECK32-NEXT: subl $8, %esp
; CHECK32-NEXT: .cfi_adjust_cfa_offset 8
; CHECK32-NEXT: leal {{[0-9]+}}(%esp), %eax
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl %eax
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: calll __sync_fetch_and_min_16
; CHECK32-NEXT: .cfi_adjust_cfa_offset -4
; CHECK32-NEXT: addl $28, %esp
; CHECK32-NEXT: .cfi_adjust_cfa_offset -28
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %edx
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %esi
; CHECK32-NEXT: movl %esi, var+8
; CHECK32-NEXT: movl %edx, var+12
; CHECK32-NEXT: movl %eax, var
; CHECK32-NEXT: movl %ecx, var+4
; CHECK32-NEXT: addl $24, %esp
; CHECK32-NEXT: .cfi_def_cfa_offset 8
; CHECK32-NEXT: popl %esi
; CHECK32-NEXT: .cfi_def_cfa_offset 4
; CHECK32-NEXT: retl
X86: expand atomics in IR instead of as MachineInstrs. The logic for expanding atomics that aren't natively supported in terms of cmpxchg loops is much simpler to express at the IR level. It also allows the normal optimisations and CodeGen improvements to help out with atomics, instead of using a limited set of possible instructions.. rdar://problem/13496295 llvm-svn: 212119
2014-07-02 02:53:31 +08:00
%val = atomicrmw min i128* %p, i128 %bits seq_cst
store i128 %val, i128* @var, align 16
ret void
}
define void @fetch_and_max(i128* %p, i128 %bits) {
; CHECK-LABEL: fetch_and_max:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; CHECK: ## %bb.0:
Regen expected tests result. NFC llvm-svn: 294866
2017-02-12 03:27:15 +08:00
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdx, %r8
; CHECK-NEXT: movq (%rdi), %rax
; CHECK-NEXT: movq 8(%rdi), %rdx
; CHECK-NEXT: .p2align 4, 0x90
[X86][test] Add a regression test for lock cmpxchg16b on a global variable with offset Add a test for a bug (uncovered by D88808) fixed by f34bb06935aa3bab353d70d515b767fdd2f5625c. Also delete cmpxchg16b.ll which is covered by atomic128.ll Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D89163
2020-10-10 05:51:45 +08:00
; CHECK-NEXT: LBB7_1: ## %atomicrmw.start
Regen expected tests result. NFC llvm-svn: 294866
2017-02-12 03:27:15 +08:00
; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
[X86] Limit the scope of the min/max canonicalization in combineSelect Previously the transform was doing these two canonicalizations (x > y) ? x : y -> (x >= y) ? x : y (x < y) ? x : y -> (x <= y) ? x : y But those don't seem to be useful generally. And they actively pessimize the cases in PR47049. This patch limits it to (x > 0) ? x : 0 -> (x >= 0) ? x : 0 (x < -1) ? x : -1 -> (x <= -1) ? x : -1 These are the cases mentioned in the comments as the motivation for the canonicalization. These allow the CMOV to use the S flag from the compare thus improving opportunities to use a TEST or the flags from an arithmetic instruction.
2020-08-08 13:51:49 +08:00
; CHECK-NEXT: cmpq %rax, %rsi
Regen expected tests result. NFC llvm-svn: 294866
2017-02-12 03:27:15 +08:00
; CHECK-NEXT: movq %r8, %rcx
[X86] Limit the scope of the min/max canonicalization in combineSelect Previously the transform was doing these two canonicalizations (x > y) ? x : y -> (x >= y) ? x : y (x < y) ? x : y -> (x <= y) ? x : y But those don't seem to be useful generally. And they actively pessimize the cases in PR47049. This patch limits it to (x > 0) ? x : 0 -> (x >= 0) ? x : 0 (x < -1) ? x : -1 -> (x <= -1) ? x : -1 These are the cases mentioned in the comments as the motivation for the canonicalization. These allow the CMOV to use the S flag from the compare thus improving opportunities to use a TEST or the flags from an arithmetic instruction.
2020-08-08 13:51:49 +08:00
; CHECK-NEXT: sbbq %rdx, %rcx
; CHECK-NEXT: movq %r8, %rcx
; CHECK-NEXT: cmovlq %rdx, %rcx
[x86] Fix an amazing goof in the handling of sub, or, and xor lowering. The comment for this code indicated that it should work similar to our handling of add lowering above: if we see uses of an instruction other than flag usage and store usage, it tries to avoid the specialized X86ISD::* nodes that are designed for flag+op modeling and emits an explicit test. Problem is, only the add case actually did this. In all the other cases, the logic was incomplete and inverted. Any time the value was used by a store, we bailed on the specialized X86ISD node. All of this appears to have been historical where we had different logic here. =/ Turns out, we have quite a few patterns designed around these nodes. We should actually form them. I fixed the code to match what we do for add, and it has quite a positive effect just within some of our test cases. The only thing close to a regression I see is using: notl %r testl %r, %r instead of: xorl -1, %r But we can add a pattern or something to fold that back out. The improvements seem more than worth this. I've also worked with Craig to update the comments to no longer be actively contradicted by the code. =[ Some of this still remains a mystery to both Craig and myself, but this seems like a large step in the direction of consistency and slightly more accurate comments. Many thanks to Craig for help figuring out this nasty stuff. Differential Revision: https://reviews.llvm.org/D37096 llvm-svn: 311737
2017-08-25 08:34:07 +08:00
; CHECK-NEXT: movq %rsi, %rbx
[X86] Limit the scope of the min/max canonicalization in combineSelect Previously the transform was doing these two canonicalizations (x > y) ? x : y -> (x >= y) ? x : y (x < y) ? x : y -> (x <= y) ? x : y But those don't seem to be useful generally. And they actively pessimize the cases in PR47049. This patch limits it to (x > 0) ? x : 0 -> (x >= 0) ? x : 0 (x < -1) ? x : -1 -> (x <= -1) ? x : -1 These are the cases mentioned in the comments as the motivation for the canonicalization. These allow the CMOV to use the S flag from the compare thus improving opportunities to use a TEST or the flags from an arithmetic instruction.
2020-08-08 13:51:49 +08:00
; CHECK-NEXT: cmovlq %rax, %rbx
Regen expected tests result. NFC llvm-svn: 294866
2017-02-12 03:27:15 +08:00
; CHECK-NEXT: lock cmpxchg16b (%rdi)
[X86][test] Add a regression test for lock cmpxchg16b on a global variable with offset Add a test for a bug (uncovered by D88808) fixed by f34bb06935aa3bab353d70d515b767fdd2f5625c. Also delete cmpxchg16b.ll which is covered by atomic128.ll Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D89163
2020-10-10 05:51:45 +08:00
; CHECK-NEXT: jne LBB7_1
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; CHECK-NEXT: ## %bb.2: ## %atomicrmw.end
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated The motivation is that the update script has at least two deviations (`<...>@GOT`/`<...>@PLT`/ and not hiding pointer arithmetics) from what pretty much all the checklines were generated with, and most of the tests are still not updated, so each time one of the non-up-to-date tests is updated to see the effect of the code change, there is a lot of noise. Instead of having to deal with that each time, let's just deal with everything at once. This has been done via: ``` cd llvm-project/llvm/test/CodeGen/X86 grep -rl "; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py" | xargs -L1 <...>/llvm-project/llvm/utils/update_llc_test_checks.py --llc-binary <...>/llvm-project/build/bin/llc ``` Not all tests were regenerated, however.
2021-06-12 04:26:17 +08:00
; CHECK-NEXT: movq %rax, _var(%rip)
; CHECK-NEXT: movq %rdx, _var+8(%rip)
Regen expected tests result. NFC llvm-svn: 294866
2017-02-12 03:27:15 +08:00
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: retq
[X86] Check for 64-bit mode in X86Subtarget::hasCmpxchg16b() The feature flag alone can't be trusted since it can be passed via -mattr. Need to ensure 64-bit mode as well. We had a 64 bit mode check on the instruction to make the assembler work correctly. But we weren't guarding any of our lowering code or the hooks for the AtomicExpandPass. I've added 32-bit command lines to atomic128.ll with and without cx16. The tests there would all previously fail if -mattr=cx16 was passed to them. I had to move one test case for f128 to a new file as it seems to have a different 32-bit mode or possibly sse issue. Differential Revision: https://reviews.llvm.org/D59308 llvm-svn: 356078
2019-03-14 02:48:50 +08:00
;
; CHECK32-LABEL: fetch_and_max:
; CHECK32: # %bb.0:
; CHECK32-NEXT: pushl %esi
; CHECK32-NEXT: .cfi_def_cfa_offset 8
; CHECK32-NEXT: subl $24, %esp
; CHECK32-NEXT: .cfi_def_cfa_offset 32
; CHECK32-NEXT: .cfi_offset %esi, -8
; CHECK32-NEXT: subl $8, %esp
; CHECK32-NEXT: .cfi_adjust_cfa_offset 8
; CHECK32-NEXT: leal {{[0-9]+}}(%esp), %eax
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl %eax
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: calll __sync_fetch_and_max_16
; CHECK32-NEXT: .cfi_adjust_cfa_offset -4
; CHECK32-NEXT: addl $28, %esp
; CHECK32-NEXT: .cfi_adjust_cfa_offset -28
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %edx
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %esi
; CHECK32-NEXT: movl %esi, var+8
; CHECK32-NEXT: movl %edx, var+12
; CHECK32-NEXT: movl %eax, var
; CHECK32-NEXT: movl %ecx, var+4
; CHECK32-NEXT: addl $24, %esp
; CHECK32-NEXT: .cfi_def_cfa_offset 8
; CHECK32-NEXT: popl %esi
; CHECK32-NEXT: .cfi_def_cfa_offset 4
; CHECK32-NEXT: retl
X86: expand atomics in IR instead of as MachineInstrs. The logic for expanding atomics that aren't natively supported in terms of cmpxchg loops is much simpler to express at the IR level. It also allows the normal optimisations and CodeGen improvements to help out with atomics, instead of using a limited set of possible instructions.. rdar://problem/13496295 llvm-svn: 212119
2014-07-02 02:53:31 +08:00
%val = atomicrmw max i128* %p, i128 %bits seq_cst
store i128 %val, i128* @var, align 16
ret void
}
define void @fetch_and_umin(i128* %p, i128 %bits) {
; CHECK-LABEL: fetch_and_umin:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; CHECK: ## %bb.0:
Regen expected tests result. NFC llvm-svn: 294866
2017-02-12 03:27:15 +08:00
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdx, %r8
; CHECK-NEXT: movq (%rdi), %rax
; CHECK-NEXT: movq 8(%rdi), %rdx
; CHECK-NEXT: .p2align 4, 0x90
[X86][test] Add a regression test for lock cmpxchg16b on a global variable with offset Add a test for a bug (uncovered by D88808) fixed by f34bb06935aa3bab353d70d515b767fdd2f5625c. Also delete cmpxchg16b.ll which is covered by atomic128.ll Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D89163
2020-10-10 05:51:45 +08:00
; CHECK-NEXT: LBB8_1: ## %atomicrmw.start
Regen expected tests result. NFC llvm-svn: 294866
2017-02-12 03:27:15 +08:00
; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
; CHECK-NEXT: cmpq %rax, %rsi
; CHECK-NEXT: movq %r8, %rcx
; CHECK-NEXT: sbbq %rdx, %rcx
; CHECK-NEXT: movq %r8, %rcx
[x86] Fix an amazing goof in the handling of sub, or, and xor lowering. The comment for this code indicated that it should work similar to our handling of add lowering above: if we see uses of an instruction other than flag usage and store usage, it tries to avoid the specialized X86ISD::* nodes that are designed for flag+op modeling and emits an explicit test. Problem is, only the add case actually did this. In all the other cases, the logic was incomplete and inverted. Any time the value was used by a store, we bailed on the specialized X86ISD node. All of this appears to have been historical where we had different logic here. =/ Turns out, we have quite a few patterns designed around these nodes. We should actually form them. I fixed the code to match what we do for add, and it has quite a positive effect just within some of our test cases. The only thing close to a regression I see is using: notl %r testl %r, %r instead of: xorl -1, %r But we can add a pattern or something to fold that back out. The improvements seem more than worth this. I've also worked with Craig to update the comments to no longer be actively contradicted by the code. =[ Some of this still remains a mystery to both Craig and myself, but this seems like a large step in the direction of consistency and slightly more accurate comments. Many thanks to Craig for help figuring out this nasty stuff. Differential Revision: https://reviews.llvm.org/D37096 llvm-svn: 311737
2017-08-25 08:34:07 +08:00
; CHECK-NEXT: cmovaeq %rdx, %rcx
; CHECK-NEXT: movq %rsi, %rbx
; CHECK-NEXT: cmovaeq %rax, %rbx
Regen expected tests result. NFC llvm-svn: 294866
2017-02-12 03:27:15 +08:00
; CHECK-NEXT: lock cmpxchg16b (%rdi)
[X86][test] Add a regression test for lock cmpxchg16b on a global variable with offset Add a test for a bug (uncovered by D88808) fixed by f34bb06935aa3bab353d70d515b767fdd2f5625c. Also delete cmpxchg16b.ll which is covered by atomic128.ll Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D89163
2020-10-10 05:51:45 +08:00
; CHECK-NEXT: jne LBB8_1
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; CHECK-NEXT: ## %bb.2: ## %atomicrmw.end
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated The motivation is that the update script has at least two deviations (`<...>@GOT`/`<...>@PLT`/ and not hiding pointer arithmetics) from what pretty much all the checklines were generated with, and most of the tests are still not updated, so each time one of the non-up-to-date tests is updated to see the effect of the code change, there is a lot of noise. Instead of having to deal with that each time, let's just deal with everything at once. This has been done via: ``` cd llvm-project/llvm/test/CodeGen/X86 grep -rl "; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py" | xargs -L1 <...>/llvm-project/llvm/utils/update_llc_test_checks.py --llc-binary <...>/llvm-project/build/bin/llc ``` Not all tests were regenerated, however.
2021-06-12 04:26:17 +08:00
; CHECK-NEXT: movq %rax, _var(%rip)
; CHECK-NEXT: movq %rdx, _var+8(%rip)
Regen expected tests result. NFC llvm-svn: 294866
2017-02-12 03:27:15 +08:00
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: retq
[X86] Check for 64-bit mode in X86Subtarget::hasCmpxchg16b() The feature flag alone can't be trusted since it can be passed via -mattr. Need to ensure 64-bit mode as well. We had a 64 bit mode check on the instruction to make the assembler work correctly. But we weren't guarding any of our lowering code or the hooks for the AtomicExpandPass. I've added 32-bit command lines to atomic128.ll with and without cx16. The tests there would all previously fail if -mattr=cx16 was passed to them. I had to move one test case for f128 to a new file as it seems to have a different 32-bit mode or possibly sse issue. Differential Revision: https://reviews.llvm.org/D59308 llvm-svn: 356078
2019-03-14 02:48:50 +08:00
;
; CHECK32-LABEL: fetch_and_umin:
; CHECK32: # %bb.0:
; CHECK32-NEXT: pushl %esi
; CHECK32-NEXT: .cfi_def_cfa_offset 8
; CHECK32-NEXT: subl $24, %esp
; CHECK32-NEXT: .cfi_def_cfa_offset 32
; CHECK32-NEXT: .cfi_offset %esi, -8
; CHECK32-NEXT: subl $8, %esp
; CHECK32-NEXT: .cfi_adjust_cfa_offset 8
; CHECK32-NEXT: leal {{[0-9]+}}(%esp), %eax
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl %eax
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: calll __sync_fetch_and_umin_16
; CHECK32-NEXT: .cfi_adjust_cfa_offset -4
; CHECK32-NEXT: addl $28, %esp
; CHECK32-NEXT: .cfi_adjust_cfa_offset -28
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %edx
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %esi
; CHECK32-NEXT: movl %esi, var+8
; CHECK32-NEXT: movl %edx, var+12
; CHECK32-NEXT: movl %eax, var
; CHECK32-NEXT: movl %ecx, var+4
; CHECK32-NEXT: addl $24, %esp
; CHECK32-NEXT: .cfi_def_cfa_offset 8
; CHECK32-NEXT: popl %esi
; CHECK32-NEXT: .cfi_def_cfa_offset 4
; CHECK32-NEXT: retl
X86: expand atomics in IR instead of as MachineInstrs. The logic for expanding atomics that aren't natively supported in terms of cmpxchg loops is much simpler to express at the IR level. It also allows the normal optimisations and CodeGen improvements to help out with atomics, instead of using a limited set of possible instructions.. rdar://problem/13496295 llvm-svn: 212119
2014-07-02 02:53:31 +08:00
%val = atomicrmw umin i128* %p, i128 %bits seq_cst
store i128 %val, i128* @var, align 16
ret void
}
define void @fetch_and_umax(i128* %p, i128 %bits) {
; CHECK-LABEL: fetch_and_umax:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; CHECK: ## %bb.0:
Regen expected tests result. NFC llvm-svn: 294866
2017-02-12 03:27:15 +08:00
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdx, %r8
; CHECK-NEXT: movq (%rdi), %rax
; CHECK-NEXT: movq 8(%rdi), %rdx
; CHECK-NEXT: .p2align 4, 0x90
[X86][test] Add a regression test for lock cmpxchg16b on a global variable with offset Add a test for a bug (uncovered by D88808) fixed by f34bb06935aa3bab353d70d515b767fdd2f5625c. Also delete cmpxchg16b.ll which is covered by atomic128.ll Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D89163
2020-10-10 05:51:45 +08:00
; CHECK-NEXT: LBB9_1: ## %atomicrmw.start
Regen expected tests result. NFC llvm-svn: 294866
2017-02-12 03:27:15 +08:00
; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
; CHECK-NEXT: cmpq %rax, %rsi
; CHECK-NEXT: movq %r8, %rcx
; CHECK-NEXT: sbbq %rdx, %rcx
; CHECK-NEXT: movq %r8, %rcx
[x86] Fix an amazing goof in the handling of sub, or, and xor lowering. The comment for this code indicated that it should work similar to our handling of add lowering above: if we see uses of an instruction other than flag usage and store usage, it tries to avoid the specialized X86ISD::* nodes that are designed for flag+op modeling and emits an explicit test. Problem is, only the add case actually did this. In all the other cases, the logic was incomplete and inverted. Any time the value was used by a store, we bailed on the specialized X86ISD node. All of this appears to have been historical where we had different logic here. =/ Turns out, we have quite a few patterns designed around these nodes. We should actually form them. I fixed the code to match what we do for add, and it has quite a positive effect just within some of our test cases. The only thing close to a regression I see is using: notl %r testl %r, %r instead of: xorl -1, %r But we can add a pattern or something to fold that back out. The improvements seem more than worth this. I've also worked with Craig to update the comments to no longer be actively contradicted by the code. =[ Some of this still remains a mystery to both Craig and myself, but this seems like a large step in the direction of consistency and slightly more accurate comments. Many thanks to Craig for help figuring out this nasty stuff. Differential Revision: https://reviews.llvm.org/D37096 llvm-svn: 311737
2017-08-25 08:34:07 +08:00
; CHECK-NEXT: cmovbq %rdx, %rcx
; CHECK-NEXT: movq %rsi, %rbx
; CHECK-NEXT: cmovbq %rax, %rbx
Regen expected tests result. NFC llvm-svn: 294866
2017-02-12 03:27:15 +08:00
; CHECK-NEXT: lock cmpxchg16b (%rdi)
[X86][test] Add a regression test for lock cmpxchg16b on a global variable with offset Add a test for a bug (uncovered by D88808) fixed by f34bb06935aa3bab353d70d515b767fdd2f5625c. Also delete cmpxchg16b.ll which is covered by atomic128.ll Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D89163
2020-10-10 05:51:45 +08:00
; CHECK-NEXT: jne LBB9_1
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; CHECK-NEXT: ## %bb.2: ## %atomicrmw.end
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated The motivation is that the update script has at least two deviations (`<...>@GOT`/`<...>@PLT`/ and not hiding pointer arithmetics) from what pretty much all the checklines were generated with, and most of the tests are still not updated, so each time one of the non-up-to-date tests is updated to see the effect of the code change, there is a lot of noise. Instead of having to deal with that each time, let's just deal with everything at once. This has been done via: ``` cd llvm-project/llvm/test/CodeGen/X86 grep -rl "; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py" | xargs -L1 <...>/llvm-project/llvm/utils/update_llc_test_checks.py --llc-binary <...>/llvm-project/build/bin/llc ``` Not all tests were regenerated, however.
2021-06-12 04:26:17 +08:00
; CHECK-NEXT: movq %rax, _var(%rip)
; CHECK-NEXT: movq %rdx, _var+8(%rip)
Regen expected tests result. NFC llvm-svn: 294866
2017-02-12 03:27:15 +08:00
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: retq
[X86] Check for 64-bit mode in X86Subtarget::hasCmpxchg16b() The feature flag alone can't be trusted since it can be passed via -mattr. Need to ensure 64-bit mode as well. We had a 64 bit mode check on the instruction to make the assembler work correctly. But we weren't guarding any of our lowering code or the hooks for the AtomicExpandPass. I've added 32-bit command lines to atomic128.ll with and without cx16. The tests there would all previously fail if -mattr=cx16 was passed to them. I had to move one test case for f128 to a new file as it seems to have a different 32-bit mode or possibly sse issue. Differential Revision: https://reviews.llvm.org/D59308 llvm-svn: 356078
2019-03-14 02:48:50 +08:00
;
; CHECK32-LABEL: fetch_and_umax:
; CHECK32: # %bb.0:
; CHECK32-NEXT: pushl %esi
; CHECK32-NEXT: .cfi_def_cfa_offset 8
; CHECK32-NEXT: subl $24, %esp
; CHECK32-NEXT: .cfi_def_cfa_offset 32
; CHECK32-NEXT: .cfi_offset %esi, -8
; CHECK32-NEXT: subl $8, %esp
; CHECK32-NEXT: .cfi_adjust_cfa_offset 8
; CHECK32-NEXT: leal {{[0-9]+}}(%esp), %eax
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl %eax
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: calll __sync_fetch_and_umax_16
; CHECK32-NEXT: .cfi_adjust_cfa_offset -4
; CHECK32-NEXT: addl $28, %esp
; CHECK32-NEXT: .cfi_adjust_cfa_offset -28
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %edx
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %esi
; CHECK32-NEXT: movl %esi, var+8
; CHECK32-NEXT: movl %edx, var+12
; CHECK32-NEXT: movl %eax, var
; CHECK32-NEXT: movl %ecx, var+4
; CHECK32-NEXT: addl $24, %esp
; CHECK32-NEXT: .cfi_def_cfa_offset 8
; CHECK32-NEXT: popl %esi
; CHECK32-NEXT: .cfi_def_cfa_offset 4
; CHECK32-NEXT: retl
X86: expand atomics in IR instead of as MachineInstrs. The logic for expanding atomics that aren't natively supported in terms of cmpxchg loops is much simpler to express at the IR level. It also allows the normal optimisations and CodeGen improvements to help out with atomics, instead of using a limited set of possible instructions.. rdar://problem/13496295 llvm-svn: 212119
2014-07-02 02:53:31 +08:00
%val = atomicrmw umax i128* %p, i128 %bits seq_cst
store i128 %val, i128* @var, align 16
ret void
}
define i128 @atomic_load_seq_cst(i128* %p) {
; CHECK-LABEL: atomic_load_seq_cst:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; CHECK: ## %bb.0:
Regen expected tests result. NFC llvm-svn: 294866
2017-02-12 03:27:15 +08:00
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: xorl %ebx, %ebx
; CHECK-NEXT: lock cmpxchg16b (%rdi)
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: retq
[X86] Check for 64-bit mode in X86Subtarget::hasCmpxchg16b() The feature flag alone can't be trusted since it can be passed via -mattr. Need to ensure 64-bit mode as well. We had a 64 bit mode check on the instruction to make the assembler work correctly. But we weren't guarding any of our lowering code or the hooks for the AtomicExpandPass. I've added 32-bit command lines to atomic128.ll with and without cx16. The tests there would all previously fail if -mattr=cx16 was passed to them. I had to move one test case for f128 to a new file as it seems to have a different 32-bit mode or possibly sse issue. Differential Revision: https://reviews.llvm.org/D59308 llvm-svn: 356078
2019-03-14 02:48:50 +08:00
;
; CHECK32-LABEL: atomic_load_seq_cst:
; CHECK32: # %bb.0:
; CHECK32-NEXT: pushl %edi
; CHECK32-NEXT: .cfi_def_cfa_offset 8
; CHECK32-NEXT: pushl %esi
; CHECK32-NEXT: .cfi_def_cfa_offset 12
; CHECK32-NEXT: subl $20, %esp
; CHECK32-NEXT: .cfi_def_cfa_offset 32
; CHECK32-NEXT: .cfi_offset %esi, -12
; CHECK32-NEXT: .cfi_offset %edi, -8
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %esi
; CHECK32-NEXT: subl $8, %esp
; CHECK32-NEXT: .cfi_adjust_cfa_offset 8
; CHECK32-NEXT: leal {{[0-9]+}}(%esp), %eax
; CHECK32-NEXT: pushl $0
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl $0
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl $0
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl $0
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl $0
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl $0
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl $0
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl $0
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl %eax
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: calll __sync_val_compare_and_swap_16
; CHECK32-NEXT: .cfi_adjust_cfa_offset -4
; CHECK32-NEXT: addl $44, %esp
; CHECK32-NEXT: .cfi_adjust_cfa_offset -44
; CHECK32-NEXT: movl (%esp), %eax
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %edx
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %edi
; CHECK32-NEXT: movl %edi, 8(%esi)
; CHECK32-NEXT: movl %edx, 12(%esi)
; CHECK32-NEXT: movl %eax, (%esi)
; CHECK32-NEXT: movl %ecx, 4(%esi)
; CHECK32-NEXT: movl %esi, %eax
; CHECK32-NEXT: addl $20, %esp
; CHECK32-NEXT: .cfi_def_cfa_offset 12
; CHECK32-NEXT: popl %esi
; CHECK32-NEXT: .cfi_def_cfa_offset 8
; CHECK32-NEXT: popl %edi
; CHECK32-NEXT: .cfi_def_cfa_offset 4
; CHECK32-NEXT: retl $4
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%r = load atomic i128, i128* %p seq_cst, align 16
X86: expand atomics in IR instead of as MachineInstrs. The logic for expanding atomics that aren't natively supported in terms of cmpxchg loops is much simpler to express at the IR level. It also allows the normal optimisations and CodeGen improvements to help out with atomics, instead of using a limited set of possible instructions.. rdar://problem/13496295 llvm-svn: 212119
2014-07-02 02:53:31 +08:00
ret i128 %r
}
define i128 @atomic_load_relaxed(i128* %p) {
Regen expected tests result. NFC llvm-svn: 294866
2017-02-12 03:27:15 +08:00
; CHECK-LABEL: atomic_load_relaxed:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; CHECK: ## %bb.0:
Regen expected tests result. NFC llvm-svn: 294866
2017-02-12 03:27:15 +08:00
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: xorl %eax, %eax
; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: xorl %ebx, %ebx
; CHECK-NEXT: lock cmpxchg16b (%rdi)
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: retq
[X86] Check for 64-bit mode in X86Subtarget::hasCmpxchg16b() The feature flag alone can't be trusted since it can be passed via -mattr. Need to ensure 64-bit mode as well. We had a 64 bit mode check on the instruction to make the assembler work correctly. But we weren't guarding any of our lowering code or the hooks for the AtomicExpandPass. I've added 32-bit command lines to atomic128.ll with and without cx16. The tests there would all previously fail if -mattr=cx16 was passed to them. I had to move one test case for f128 to a new file as it seems to have a different 32-bit mode or possibly sse issue. Differential Revision: https://reviews.llvm.org/D59308 llvm-svn: 356078
2019-03-14 02:48:50 +08:00
;
; CHECK32-LABEL: atomic_load_relaxed:
; CHECK32: # %bb.0:
; CHECK32-NEXT: pushl %edi
; CHECK32-NEXT: .cfi_def_cfa_offset 8
; CHECK32-NEXT: pushl %esi
; CHECK32-NEXT: .cfi_def_cfa_offset 12
; CHECK32-NEXT: subl $20, %esp
; CHECK32-NEXT: .cfi_def_cfa_offset 32
; CHECK32-NEXT: .cfi_offset %esi, -12
; CHECK32-NEXT: .cfi_offset %edi, -8
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %esi
; CHECK32-NEXT: subl $8, %esp
; CHECK32-NEXT: .cfi_adjust_cfa_offset 8
; CHECK32-NEXT: leal {{[0-9]+}}(%esp), %eax
; CHECK32-NEXT: pushl $0
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl $0
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl $0
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl $0
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl $0
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl $0
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl $0
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl $0
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl %eax
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: calll __sync_val_compare_and_swap_16
; CHECK32-NEXT: .cfi_adjust_cfa_offset -4
; CHECK32-NEXT: addl $44, %esp
; CHECK32-NEXT: .cfi_adjust_cfa_offset -44
; CHECK32-NEXT: movl (%esp), %eax
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %edx
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %edi
; CHECK32-NEXT: movl %edi, 8(%esi)
; CHECK32-NEXT: movl %edx, 12(%esi)
; CHECK32-NEXT: movl %eax, (%esi)
; CHECK32-NEXT: movl %ecx, 4(%esi)
; CHECK32-NEXT: movl %esi, %eax
; CHECK32-NEXT: addl $20, %esp
; CHECK32-NEXT: .cfi_def_cfa_offset 12
; CHECK32-NEXT: popl %esi
; CHECK32-NEXT: .cfi_def_cfa_offset 8
; CHECK32-NEXT: popl %edi
; CHECK32-NEXT: .cfi_def_cfa_offset 4
; CHECK32-NEXT: retl $4
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%r = load atomic i128, i128* %p monotonic, align 16
X86: expand atomics in IR instead of as MachineInstrs. The logic for expanding atomics that aren't natively supported in terms of cmpxchg loops is much simpler to express at the IR level. It also allows the normal optimisations and CodeGen improvements to help out with atomics, instead of using a limited set of possible instructions.. rdar://problem/13496295 llvm-svn: 212119
2014-07-02 02:53:31 +08:00
ret i128 %r
}
define void @atomic_store_seq_cst(i128* %p, i128 %in) {
; CHECK-LABEL: atomic_store_seq_cst:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; CHECK: ## %bb.0:
Regen expected tests result. NFC llvm-svn: 294866
2017-02-12 03:27:15 +08:00
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdx, %rcx
; CHECK-NEXT: movq %rsi, %rbx
; CHECK-NEXT: movq (%rdi), %rax
; CHECK-NEXT: movq 8(%rdi), %rdx
; CHECK-NEXT: .p2align 4, 0x90
[X86][test] Add a regression test for lock cmpxchg16b on a global variable with offset Add a test for a bug (uncovered by D88808) fixed by f34bb06935aa3bab353d70d515b767fdd2f5625c. Also delete cmpxchg16b.ll which is covered by atomic128.ll Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D89163
2020-10-10 05:51:45 +08:00
; CHECK-NEXT: LBB12_1: ## %atomicrmw.start
Regen expected tests result. NFC llvm-svn: 294866
2017-02-12 03:27:15 +08:00
; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
; CHECK-NEXT: lock cmpxchg16b (%rdi)
[X86][test] Add a regression test for lock cmpxchg16b on a global variable with offset Add a test for a bug (uncovered by D88808) fixed by f34bb06935aa3bab353d70d515b767fdd2f5625c. Also delete cmpxchg16b.ll which is covered by atomic128.ll Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D89163
2020-10-10 05:51:45 +08:00
; CHECK-NEXT: jne LBB12_1
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; CHECK-NEXT: ## %bb.2: ## %atomicrmw.end
Regen expected tests result. NFC llvm-svn: 294866
2017-02-12 03:27:15 +08:00
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: retq
[X86] Check for 64-bit mode in X86Subtarget::hasCmpxchg16b() The feature flag alone can't be trusted since it can be passed via -mattr. Need to ensure 64-bit mode as well. We had a 64 bit mode check on the instruction to make the assembler work correctly. But we weren't guarding any of our lowering code or the hooks for the AtomicExpandPass. I've added 32-bit command lines to atomic128.ll with and without cx16. The tests there would all previously fail if -mattr=cx16 was passed to them. I had to move one test case for f128 to a new file as it seems to have a different 32-bit mode or possibly sse issue. Differential Revision: https://reviews.llvm.org/D59308 llvm-svn: 356078
2019-03-14 02:48:50 +08:00
;
; CHECK32-LABEL: atomic_store_seq_cst:
; CHECK32: # %bb.0:
; CHECK32-NEXT: subl $36, %esp
; CHECK32-NEXT: .cfi_adjust_cfa_offset 36
; CHECK32-NEXT: leal {{[0-9]+}}(%esp), %eax
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl %eax
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: calll __sync_lock_test_and_set_16
; CHECK32-NEXT: .cfi_adjust_cfa_offset -4
; CHECK32-NEXT: addl $56, %esp
; CHECK32-NEXT: .cfi_adjust_cfa_offset -56
; CHECK32-NEXT: retl
X86: expand atomics in IR instead of as MachineInstrs. The logic for expanding atomics that aren't natively supported in terms of cmpxchg loops is much simpler to express at the IR level. It also allows the normal optimisations and CodeGen improvements to help out with atomics, instead of using a limited set of possible instructions.. rdar://problem/13496295 llvm-svn: 212119
2014-07-02 02:53:31 +08:00
store atomic i128 %in, i128* %p seq_cst, align 16
ret void
}
define void @atomic_store_release(i128* %p, i128 %in) {
; CHECK-LABEL: atomic_store_release:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; CHECK: ## %bb.0:
Regen expected tests result. NFC llvm-svn: 294866
2017-02-12 03:27:15 +08:00
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdx, %rcx
; CHECK-NEXT: movq %rsi, %rbx
; CHECK-NEXT: movq (%rdi), %rax
; CHECK-NEXT: movq 8(%rdi), %rdx
; CHECK-NEXT: .p2align 4, 0x90
[X86][test] Add a regression test for lock cmpxchg16b on a global variable with offset Add a test for a bug (uncovered by D88808) fixed by f34bb06935aa3bab353d70d515b767fdd2f5625c. Also delete cmpxchg16b.ll which is covered by atomic128.ll Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D89163
2020-10-10 05:51:45 +08:00
; CHECK-NEXT: LBB13_1: ## %atomicrmw.start
Regen expected tests result. NFC llvm-svn: 294866
2017-02-12 03:27:15 +08:00
; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
; CHECK-NEXT: lock cmpxchg16b (%rdi)
[X86][test] Add a regression test for lock cmpxchg16b on a global variable with offset Add a test for a bug (uncovered by D88808) fixed by f34bb06935aa3bab353d70d515b767fdd2f5625c. Also delete cmpxchg16b.ll which is covered by atomic128.ll Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D89163
2020-10-10 05:51:45 +08:00
; CHECK-NEXT: jne LBB13_1
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; CHECK-NEXT: ## %bb.2: ## %atomicrmw.end
Regen expected tests result. NFC llvm-svn: 294866
2017-02-12 03:27:15 +08:00
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: retq
[X86] Check for 64-bit mode in X86Subtarget::hasCmpxchg16b() The feature flag alone can't be trusted since it can be passed via -mattr. Need to ensure 64-bit mode as well. We had a 64 bit mode check on the instruction to make the assembler work correctly. But we weren't guarding any of our lowering code or the hooks for the AtomicExpandPass. I've added 32-bit command lines to atomic128.ll with and without cx16. The tests there would all previously fail if -mattr=cx16 was passed to them. I had to move one test case for f128 to a new file as it seems to have a different 32-bit mode or possibly sse issue. Differential Revision: https://reviews.llvm.org/D59308 llvm-svn: 356078
2019-03-14 02:48:50 +08:00
;
; CHECK32-LABEL: atomic_store_release:
; CHECK32: # %bb.0:
; CHECK32-NEXT: subl $36, %esp
; CHECK32-NEXT: .cfi_adjust_cfa_offset 36
; CHECK32-NEXT: leal {{[0-9]+}}(%esp), %eax
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl %eax
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: calll __sync_lock_test_and_set_16
; CHECK32-NEXT: .cfi_adjust_cfa_offset -4
; CHECK32-NEXT: addl $56, %esp
; CHECK32-NEXT: .cfi_adjust_cfa_offset -56
; CHECK32-NEXT: retl
X86: expand atomics in IR instead of as MachineInstrs. The logic for expanding atomics that aren't natively supported in terms of cmpxchg loops is much simpler to express at the IR level. It also allows the normal optimisations and CodeGen improvements to help out with atomics, instead of using a limited set of possible instructions.. rdar://problem/13496295 llvm-svn: 212119
2014-07-02 02:53:31 +08:00
store atomic i128 %in, i128* %p release, align 16
ret void
}
define void @atomic_store_relaxed(i128* %p, i128 %in) {
; CHECK-LABEL: atomic_store_relaxed:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; CHECK: ## %bb.0:
Regen expected tests result. NFC llvm-svn: 294866
2017-02-12 03:27:15 +08:00
; CHECK-NEXT: pushq %rbx
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset %rbx, -16
; CHECK-NEXT: movq %rdx, %rcx
; CHECK-NEXT: movq %rsi, %rbx
; CHECK-NEXT: movq (%rdi), %rax
; CHECK-NEXT: movq 8(%rdi), %rdx
; CHECK-NEXT: .p2align 4, 0x90
[X86][test] Add a regression test for lock cmpxchg16b on a global variable with offset Add a test for a bug (uncovered by D88808) fixed by f34bb06935aa3bab353d70d515b767fdd2f5625c. Also delete cmpxchg16b.ll which is covered by atomic128.ll Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D89163
2020-10-10 05:51:45 +08:00
; CHECK-NEXT: LBB14_1: ## %atomicrmw.start
Regen expected tests result. NFC llvm-svn: 294866
2017-02-12 03:27:15 +08:00
; CHECK-NEXT: ## =>This Inner Loop Header: Depth=1
; CHECK-NEXT: lock cmpxchg16b (%rdi)
[X86][test] Add a regression test for lock cmpxchg16b on a global variable with offset Add a test for a bug (uncovered by D88808) fixed by f34bb06935aa3bab353d70d515b767fdd2f5625c. Also delete cmpxchg16b.ll which is covered by atomic128.ll Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D89163
2020-10-10 05:51:45 +08:00
; CHECK-NEXT: jne LBB14_1
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; CHECK-NEXT: ## %bb.2: ## %atomicrmw.end
Regen expected tests result. NFC llvm-svn: 294866
2017-02-12 03:27:15 +08:00
; CHECK-NEXT: popq %rbx
; CHECK-NEXT: retq
[X86] Check for 64-bit mode in X86Subtarget::hasCmpxchg16b() The feature flag alone can't be trusted since it can be passed via -mattr. Need to ensure 64-bit mode as well. We had a 64 bit mode check on the instruction to make the assembler work correctly. But we weren't guarding any of our lowering code or the hooks for the AtomicExpandPass. I've added 32-bit command lines to atomic128.ll with and without cx16. The tests there would all previously fail if -mattr=cx16 was passed to them. I had to move one test case for f128 to a new file as it seems to have a different 32-bit mode or possibly sse issue. Differential Revision: https://reviews.llvm.org/D59308 llvm-svn: 356078
2019-03-14 02:48:50 +08:00
;
; CHECK32-LABEL: atomic_store_relaxed:
; CHECK32: # %bb.0:
; CHECK32-NEXT: subl $36, %esp
; CHECK32-NEXT: .cfi_adjust_cfa_offset 36
; CHECK32-NEXT: leal {{[0-9]+}}(%esp), %eax
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: pushl %eax
; CHECK32-NEXT: .cfi_adjust_cfa_offset 4
; CHECK32-NEXT: calll __sync_lock_test_and_set_16
; CHECK32-NEXT: .cfi_adjust_cfa_offset -4
; CHECK32-NEXT: addl $56, %esp
; CHECK32-NEXT: .cfi_adjust_cfa_offset -56
; CHECK32-NEXT: retl
X86: expand atomics in IR instead of as MachineInstrs. The logic for expanding atomics that aren't natively supported in terms of cmpxchg loops is much simpler to express at the IR level. It also allows the normal optimisations and CodeGen improvements to help out with atomics, instead of using a limited set of possible instructions.. rdar://problem/13496295 llvm-svn: 212119
2014-07-02 02:53:31 +08:00
store atomic i128 %in, i128* %p unordered, align 16
ret void
}
Allow FP types for atomicrmw xchg llvm-svn: 351427
2019-01-17 18:49:01 +08:00