forked from OSchip/llvm-project
41 lines
1.0 KiB
TableGen
41 lines
1.0 KiB
TableGen
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// RUN: not llvm-tblgen -gen-instr-info -I %p/../../include %s 2>&1 | FileCheck %s
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// This test verifies that TableGen is displaying an error when mapped instruction
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// does not contain a field listed under RowFields.
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include "llvm/Target/Target.td"
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class SimpleReg<string n> : Register<n> {
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let Namespace = "Simple";
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}
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def R0 : SimpleReg<"r0">;
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def SimpleRegClass : RegisterClass<"Simple",[i32],0,(add R0)>;
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def SimpleInstrInfo : InstrInfo;
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def SimpleTarget : Target {
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let InstructionSet = SimpleInstrInfo;
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}
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class SimpleRel;
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def REL_DEF : InstrMapping {
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let FilterClass = "SimpleRel";
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let RowFields = ["BaseName"];
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let ColFields = ["Col"];
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let KeyCol = ["KeyCol"];
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let ValueCols = [["ValCol"]];
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}
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class INSTR_DEF : Instruction {
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let Namespace = "Simple";
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let OutOperandList = (outs);
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let InOperandList = (ins);
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string Basename = "";
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string Col = "";
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}
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def SimpleInstr : SimpleRel, INSTR_DEF;
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// CHECK: error: No value "BaseName" found in "SimpleInstr" instruction description.
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// CHECK: def SimpleInstr : SimpleRel, INSTR_DEF;
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