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llvm-project/llvm/test/MC/Mips/mips-alu-instructions.s

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Mips specific llvm assembler support for ALU instructions. This includes register support. Test case included. Contributer: Vladimir Medic llvm-svn: 163268
2012-09-06 07:34:03 +08:00
# RUN: llvm-mc %s -triple=mipsel-unknown-linux -show-encoding -mcpu=mips32r2 | FileCheck %s
# Check that the assembler can handle the documented syntax
# for arithmetic and logical instructions.
#------------------------------------------------------------------------------
# Logical instructions
#------------------------------------------------------------------------------
# CHECK: and $9, $6, $7 # encoding: [0x24,0x48,0xc7,0x00]
# CHECK: andi $9, $6, 17767 # encoding: [0x67,0x45,0xc9,0x30]
The Mips standalone assembler aliased instruction support. The assembler can alias one instruction into another based on the operands. For example the jump instruction "J" takes and immediate operand, but if the operand is a register the assembler will change it into a jump register "JR" instruction. These changes are in the instruction td file. Test cases included Contributer: Vladimir Medic llvm-svn: 163368
2012-09-07 09:42:38 +08:00
# CHECK: andi $9, $6, 17767 # encoding: [0x67,0x45,0xc9,0x30]
Mips assembler: Add TwoOperandConstraint definitions This patch removes alias definition for addiu $rs,$imm and instead uses the TwoOperandAliasConstraint field in the ArithLogicI instruction class. This way all instructions that inherit ArithLogicI class have the same macro defined. The usage examples are added to test files. Patch by Vladimir Medic llvm-svn: 182048
2013-05-17 04:24:27 +08:00
# CHECK: andi $9, $9, 17767 # encoding: [0x67,0x45,0x29,0x31]
Mips specific llvm assembler support for ALU instructions. This includes register support. Test case included. Contributer: Vladimir Medic llvm-svn: 163268
2012-09-06 07:34:03 +08:00
# CHECK: clo $6, $7 # encoding: [0x21,0x30,0xe6,0x70]
# CHECK: clz $6, $7 # encoding: [0x20,0x30,0xe6,0x70]
# CHECK: ins $19, $9, 6, 7 # encoding: [0x84,0x61,0x33,0x7d]
# CHECK: nor $9, $6, $7 # encoding: [0x27,0x48,0xc7,0x00]
# CHECK: or $3, $3, $5 # encoding: [0x25,0x18,0x65,0x00]
[Mips Assembler] Add support for OR macro with imediate opperand Mips assembler supports macros that allows the OR instruction to have an immediate parameter. This patch adds an instruction alias that converts this macro into a Mips ORI instruction. Contributer: Vladimir Medic llvm-svn: 178316
2013-03-29 07:45:13 +08:00
# CHECK: ori $4, $5, 17767 # encoding: [0x67,0x45,0xa4,0x34]
Mips specific llvm assembler support for ALU instructions. This includes register support. Test case included. Contributer: Vladimir Medic llvm-svn: 163268
2012-09-06 07:34:03 +08:00
# CHECK: ori $9, $6, 17767 # encoding: [0x67,0x45,0xc9,0x34]
Mips assembler: Add TwoOperandConstraint definitions This patch removes alias definition for addiu $rs,$imm and instead uses the TwoOperandAliasConstraint field in the ArithLogicI instruction class. This way all instructions that inherit ArithLogicI class have the same macro defined. The usage examples are added to test files. Patch by Vladimir Medic llvm-svn: 182048
2013-05-17 04:24:27 +08:00
# CHECK: ori $11, $11, 128 # encoding: [0x80,0x00,0x6b,0x35]
Mips specific llvm assembler support for ALU instructions. This includes register support. Test case included. Contributer: Vladimir Medic llvm-svn: 163268
2012-09-06 07:34:03 +08:00
# CHECK: rotr $9, $6, 7 # encoding: [0xc2,0x49,0x26,0x00]
# CHECK: rotrv $9, $6, $7 # encoding: [0x46,0x48,0xe6,0x00]
# CHECK: sll $4, $3, 7 # encoding: [0xc0,0x21,0x03,0x00]
# CHECK: sllv $2, $3, $5 # encoding: [0x04,0x10,0xa3,0x00]
# CHECK: slt $3, $3, $5 # encoding: [0x2a,0x18,0x65,0x00]
# CHECK: slti $3, $3, 103 # encoding: [0x67,0x00,0x63,0x28]
The Mips standalone assembler aliased instruction support. The assembler can alias one instruction into another based on the operands. For example the jump instruction "J" takes and immediate operand, but if the operand is a register the assembler will change it into a jump register "JR" instruction. These changes are in the instruction td file. Test cases included Contributer: Vladimir Medic llvm-svn: 163368
2012-09-07 09:42:38 +08:00
# CHECK: slti $3, $3, 103 # encoding: [0x67,0x00,0x63,0x28]
Mips specific llvm assembler support for ALU instructions. This includes register support. Test case included. Contributer: Vladimir Medic llvm-svn: 163268
2012-09-06 07:34:03 +08:00
# CHECK: sltiu $3, $3, 103 # encoding: [0x67,0x00,0x63,0x2c]
# CHECK: sltu $3, $3, $5 # encoding: [0x2b,0x18,0x65,0x00]
# CHECK: sra $4, $3, 7 # encoding: [0xc3,0x21,0x03,0x00]
# CHECK: srav $2, $3, $5 # encoding: [0x07,0x10,0xa3,0x00]
# CHECK: srl $4, $3, 7 # encoding: [0xc2,0x21,0x03,0x00]
# CHECK: srlv $2, $3, $5 # encoding: [0x06,0x10,0xa3,0x00]
# CHECK: xor $3, $3, $5 # encoding: [0x26,0x18,0x65,0x00]
# CHECK: xori $9, $6, 17767 # encoding: [0x67,0x45,0xc9,0x38]
Mips assembler: Add TwoOperandConstraint definitions This patch removes alias definition for addiu $rs,$imm and instead uses the TwoOperandAliasConstraint field in the ArithLogicI instruction class. This way all instructions that inherit ArithLogicI class have the same macro defined. The usage examples are added to test files. Patch by Vladimir Medic llvm-svn: 182048
2013-05-17 04:24:27 +08:00
# CHECK: xori $9, $6, 17767 # encoding: [0x67,0x45,0xc9,0x38]
# CHECK: xori $11, $11, 12 # encoding: [0x0c,0x00,0x6b,0x39]
Mips specific llvm assembler support for ALU instructions. This includes register support. Test case included. Contributer: Vladimir Medic llvm-svn: 163268
2012-09-06 07:34:03 +08:00
# CHECK: wsbh $6, $7 # encoding: [0xa0,0x30,0x07,0x7c]
This patch that sets the EmitAlias flag in td files and enables the instruction printer to print aliased instructions. Due to usage of RegisterOperands a change in common code (utils/TableGen/AsmWriterEmitter.cpp) is required to get the correct register value if it is a RegisterOperand. Contributer: Vladimir Medic llvm-svn: 174358
2013-02-05 16:32:10 +08:00
# CHECK: not $7, $8 # encoding: [0x27,0x38,0x00,0x01]
Mips specific llvm assembler support for ALU instructions. This includes register support. Test case included. Contributer: Vladimir Medic llvm-svn: 163268
2012-09-06 07:34:03 +08:00
and $9, $6, $7
The Mips standalone assembler aliased instruction support. The assembler can alias one instruction into another based on the operands. For example the jump instruction "J" takes and immediate operand, but if the operand is a register the assembler will change it into a jump register "JR" instruction. These changes are in the instruction td file. Test cases included Contributer: Vladimir Medic llvm-svn: 163368
2012-09-07 09:42:38 +08:00
and $9, $6, 17767
Mips specific llvm assembler support for ALU instructions. This includes register support. Test case included. Contributer: Vladimir Medic llvm-svn: 163268
2012-09-06 07:34:03 +08:00
andi $9, $6, 17767
Mips assembler: Add TwoOperandConstraint definitions This patch removes alias definition for addiu $rs,$imm and instead uses the TwoOperandAliasConstraint field in the ArithLogicI instruction class. This way all instructions that inherit ArithLogicI class have the same macro defined. The usage examples are added to test files. Patch by Vladimir Medic llvm-svn: 182048
2013-05-17 04:24:27 +08:00
andi $9, 17767
Mips specific llvm assembler support for ALU instructions. This includes register support. Test case included. Contributer: Vladimir Medic llvm-svn: 163268
2012-09-06 07:34:03 +08:00
clo $6, $7
clz $6, $7
ins $19, $9, 6,7
nor $9, $6, $7
or $3, $3, $5
[Mips Assembler] Add support for OR macro with imediate opperand Mips assembler supports macros that allows the OR instruction to have an immediate parameter. This patch adds an instruction alias that converts this macro into a Mips ORI instruction. Contributer: Vladimir Medic llvm-svn: 178316
2013-03-29 07:45:13 +08:00
or $4, $5, 17767
Mips specific llvm assembler support for ALU instructions. This includes register support. Test case included. Contributer: Vladimir Medic llvm-svn: 163268
2012-09-06 07:34:03 +08:00
ori $9, $6, 17767
Mips assembler: Add TwoOperandConstraint definitions This patch removes alias definition for addiu $rs,$imm and instead uses the TwoOperandAliasConstraint field in the ArithLogicI instruction class. This way all instructions that inherit ArithLogicI class have the same macro defined. The usage examples are added to test files. Patch by Vladimir Medic llvm-svn: 182048
2013-05-17 04:24:27 +08:00
ori $11, 128
Mips specific llvm assembler support for ALU instructions. This includes register support. Test case included. Contributer: Vladimir Medic llvm-svn: 163268
2012-09-06 07:34:03 +08:00
rotr $9, $6, 7
rotrv $9, $6, $7
sll $4, $3, 7
sllv $2, $3, $5
slt $3, $3, $5
The Mips standalone assembler aliased instruction support. The assembler can alias one instruction into another based on the operands. For example the jump instruction "J" takes and immediate operand, but if the operand is a register the assembler will change it into a jump register "JR" instruction. These changes are in the instruction td file. Test cases included Contributer: Vladimir Medic llvm-svn: 163368
2012-09-07 09:42:38 +08:00
slt $3, $3, 103
Mips specific llvm assembler support for ALU instructions. This includes register support. Test case included. Contributer: Vladimir Medic llvm-svn: 163268
2012-09-06 07:34:03 +08:00
slti $3, $3, 103
sltiu $3, $3, 103
sltu $3, $3, $5
sra $4, $3, 7
srav $2, $3, $5
srl $4, $3, 7
srlv $2, $3, $5
xor $3, $3, $5
The Mips standalone assembler aliased instruction support. The assembler can alias one instruction into another based on the operands. For example the jump instruction "J" takes and immediate operand, but if the operand is a register the assembler will change it into a jump register "JR" instruction. These changes are in the instruction td file. Test cases included Contributer: Vladimir Medic llvm-svn: 163368
2012-09-07 09:42:38 +08:00
xor $9, $6, 17767
Mips specific llvm assembler support for ALU instructions. This includes register support. Test case included. Contributer: Vladimir Medic llvm-svn: 163268
2012-09-06 07:34:03 +08:00
xori $9, $6, 17767
Mips assembler: Add TwoOperandConstraint definitions This patch removes alias definition for addiu $rs,$imm and instead uses the TwoOperandAliasConstraint field in the ArithLogicI instruction class. This way all instructions that inherit ArithLogicI class have the same macro defined. The usage examples are added to test files. Patch by Vladimir Medic llvm-svn: 182048
2013-05-17 04:24:27 +08:00
xori $11, 12
Mips specific llvm assembler support for ALU instructions. This includes register support. Test case included. Contributer: Vladimir Medic llvm-svn: 163268
2012-09-06 07:34:03 +08:00
wsbh $6, $7
The Mips standalone assembler aliased instruction support. The assembler can alias one instruction into another based on the operands. For example the jump instruction "J" takes and immediate operand, but if the operand is a register the assembler will change it into a jump register "JR" instruction. These changes are in the instruction td file. Test cases included Contributer: Vladimir Medic llvm-svn: 163368
2012-09-07 09:42:38 +08:00
not $7 ,$8
Mips specific llvm assembler support for ALU instructions. This includes register support. Test case included. Contributer: Vladimir Medic llvm-svn: 163268
2012-09-06 07:34:03 +08:00
#------------------------------------------------------------------------------
# Arithmetic instructions
#------------------------------------------------------------------------------
# CHECK: add $9, $6, $7 # encoding: [0x20,0x48,0xc7,0x00]
# CHECK: addi $9, $6, 17767 # encoding: [0x67,0x45,0xc9,0x20]
# CHECK: addiu $9, $6, -15001 # encoding: [0x67,0xc5,0xc9,0x24]
The Mips standalone assembler aliased instruction support. The assembler can alias one instruction into another based on the operands. For example the jump instruction "J" takes and immediate operand, but if the operand is a register the assembler will change it into a jump register "JR" instruction. These changes are in the instruction td file. Test cases included Contributer: Vladimir Medic llvm-svn: 163368
2012-09-07 09:42:38 +08:00
# CHECK: addi $9, $6, 17767 # encoding: [0x67,0x45,0xc9,0x20]
Mips assembler: Add TwoOperandConstraint definitions This patch removes alias definition for addiu $rs,$imm and instead uses the TwoOperandAliasConstraint field in the ArithLogicI instruction class. This way all instructions that inherit ArithLogicI class have the same macro defined. The usage examples are added to test files. Patch by Vladimir Medic llvm-svn: 182048
2013-05-17 04:24:27 +08:00
# CHECK: addi $9, $9, 17767 # encoding: [0x67,0x45,0x29,0x21]
The Mips standalone assembler aliased instruction support. The assembler can alias one instruction into another based on the operands. For example the jump instruction "J" takes and immediate operand, but if the operand is a register the assembler will change it into a jump register "JR" instruction. These changes are in the instruction td file. Test cases included Contributer: Vladimir Medic llvm-svn: 163368
2012-09-07 09:42:38 +08:00
# CHECK: addiu $9, $6, -15001 # encoding: [0x67,0xc5,0xc9,0x24]
Mips assembler: Assembler macro ADDIU $rs,imm This patch adds alias for addiu instruction which enables following syntax: addiu $rs,imm The macro is translated as: addiu $rs,$rs,imm Contributer: Vladimir Medic llvm-svn: 181729
2013-05-14 04:26:46 +08:00
# CHECK: addiu $11, $11, 40 # encoding: [0x28,0x00,0x6b,0x25]
Mips specific llvm assembler support for ALU instructions. This includes register support. Test case included. Contributer: Vladimir Medic llvm-svn: 163268
2012-09-06 07:34:03 +08:00
# CHECK: addu $9, $6, $7 # encoding: [0x21,0x48,0xc7,0x00]
# CHECK: madd $6, $7 # encoding: [0x00,0x00,0xc7,0x70]
# CHECK: maddu $6, $7 # encoding: [0x01,0x00,0xc7,0x70]
# CHECK: msub $6, $7 # encoding: [0x04,0x00,0xc7,0x70]
# CHECK: msubu $6, $7 # encoding: [0x05,0x00,0xc7,0x70]
# CHECK: mult $3, $5 # encoding: [0x18,0x00,0x65,0x00]
# CHECK: multu $3, $5 # encoding: [0x19,0x00,0x65,0x00]
# CHECK: sub $9, $6, $7 # encoding: [0x22,0x48,0xc7,0x00]
This patch adds aliases for Mips sub instruction with immediate operands. Corresponding test cases are added. llvm-svn: 191734
2013-10-01 17:48:56 +08:00
# CHECK: addi $sp, $sp, -56 # encoding: [0xc8,0xff,0xbd,0x23]
Mips specific llvm assembler support for ALU instructions. This includes register support. Test case included. Contributer: Vladimir Medic llvm-svn: 163268
2012-09-06 07:34:03 +08:00
# CHECK: subu $4, $3, $5 # encoding: [0x23,0x20,0x65,0x00]
This patch adds aliases for Mips sub instruction with immediate operands. Corresponding test cases are added. llvm-svn: 191734
2013-10-01 17:48:56 +08:00
# CHECK: addiu $sp, $sp, -40 # encoding: [0xd8,0xff,0xbd,0x27]
This patch that sets the EmitAlias flag in td files and enables the instruction printer to print aliased instructions. Due to usage of RegisterOperands a change in common code (utils/TableGen/AsmWriterEmitter.cpp) is required to get the correct register value if it is a RegisterOperand. Contributer: Vladimir Medic llvm-svn: 174358
2013-02-05 16:32:10 +08:00
# CHECK: neg $6, $7 # encoding: [0x22,0x30,0x07,0x00]
# CHECK: negu $6, $7 # encoding: [0x23,0x30,0x07,0x00]
# CHECK: move $7, $8 # encoding: [0x21,0x38,0x00,0x01]
This is a resubmittal. For some reason it broke the bots yesterday but I cannot reproduce the problem and have scrubed my sources and even tested with llvm-lit -v --vg. The Mips RDHWR (Read Hardware Register) instruction was not tested for assembler or dissassembler consumption. This patch adds that functionality. Contributer: Vladimir Medic llvm-svn: 172685
2013-01-17 08:28:20 +08:00
# CHECK: .set push
# CHECK: .set mips32r2
Revert "[mips] Add names and tests for the hardware registers" This reverts commit r221299. The tests LLVM :: MC/Disassembler/Mips/mips32.txt LLVM :: MC/Disassembler/Mips/mips32_le.txt were failing. llvm-svn: 221307
2014-11-05 06:15:05 +08:00
# CHECK: rdhwr $5, $29
This is a resubmittal. For some reason it broke the bots yesterday but I cannot reproduce the problem and have scrubed my sources and even tested with llvm-lit -v --vg. The Mips RDHWR (Read Hardware Register) instruction was not tested for assembler or dissassembler consumption. This patch adds that functionality. Contributer: Vladimir Medic llvm-svn: 172685
2013-01-17 08:28:20 +08:00
# CHECK: .set pop # encoding: [0x3b,0xe8,0x05,0x7c]
Mips specific llvm assembler support for ALU instructions. This includes register support. Test case included. Contributer: Vladimir Medic llvm-svn: 163268
2012-09-06 07:34:03 +08:00
add $9,$6,$7
The Mips standalone assembler aliased instruction support. The assembler can alias one instruction into another based on the operands. For example the jump instruction "J" takes and immediate operand, but if the operand is a register the assembler will change it into a jump register "JR" instruction. These changes are in the instruction td file. Test cases included Contributer: Vladimir Medic llvm-svn: 163368
2012-09-07 09:42:38 +08:00
add $9,$6,17767
addu $9,$6,-15001
Mips specific llvm assembler support for ALU instructions. This includes register support. Test case included. Contributer: Vladimir Medic llvm-svn: 163268
2012-09-06 07:34:03 +08:00
addi $9,$6,17767
Mips assembler: Add TwoOperandConstraint definitions This patch removes alias definition for addiu $rs,$imm and instead uses the TwoOperandAliasConstraint field in the ArithLogicI instruction class. This way all instructions that inherit ArithLogicI class have the same macro defined. The usage examples are added to test files. Patch by Vladimir Medic llvm-svn: 182048
2013-05-17 04:24:27 +08:00
addi $9,17767
Mips specific llvm assembler support for ALU instructions. This includes register support. Test case included. Contributer: Vladimir Medic llvm-svn: 163268
2012-09-06 07:34:03 +08:00
addiu $9,$6,-15001
Mips assembler: Assembler macro ADDIU $rs,imm This patch adds alias for addiu instruction which enables following syntax: addiu $rs,imm The macro is translated as: addiu $rs,$rs,imm Contributer: Vladimir Medic llvm-svn: 181729
2013-05-14 04:26:46 +08:00
addiu $11,40
Mips specific llvm assembler support for ALU instructions. This includes register support. Test case included. Contributer: Vladimir Medic llvm-svn: 163268
2012-09-06 07:34:03 +08:00
addu $9,$6,$7
madd $6,$7
maddu $6,$7
msub $6,$7
msubu $6,$7
mult $3,$5
multu $3,$5
sub $9,$6,$7
This patch adds aliases for Mips sub instruction with immediate operands. Corresponding test cases are added. llvm-svn: 191734
2013-10-01 17:48:56 +08:00
sub $sp,$sp,56
Mips specific llvm assembler support for ALU instructions. This includes register support. Test case included. Contributer: Vladimir Medic llvm-svn: 163268
2012-09-06 07:34:03 +08:00
subu $4,$3,$5
This patch adds aliases for Mips sub instruction with immediate operands. Corresponding test cases are added. llvm-svn: 191734
2013-10-01 17:48:56 +08:00
subu $sp,$sp,40
The Mips standalone assembler aliased instruction support. The assembler can alias one instruction into another based on the operands. For example the jump instruction "J" takes and immediate operand, but if the operand is a register the assembler will change it into a jump register "JR" instruction. These changes are in the instruction td file. Test cases included Contributer: Vladimir Medic llvm-svn: 163368
2012-09-07 09:42:38 +08:00
neg $6,$7
negu $6,$7
move $7,$8
This is a resubmittal. For some reason it broke the bots yesterday but I cannot reproduce the problem and have scrubed my sources and even tested with llvm-lit -v --vg. The Mips RDHWR (Read Hardware Register) instruction was not tested for assembler or dissassembler consumption. This patch adds that functionality. Contributer: Vladimir Medic llvm-svn: 172685
2013-01-17 08:28:20 +08:00
rdhwr $5, $29
[mips] Implement shorthand add / sub forms for MIPS. Summary: - If only two registers are passed to a three-register operation, then the first argument is both source and destination register. - If a non-register is passed as the last argument, generate the immediate version of the instruction. Also mark DADD commutative and add scheduling information (to the generic scheduler), and implement DSUB. Patch by David Chisnall His work was sponsored by: DARPA, AFRL CC: theraven Differential Revision: http://llvm-reviews.chandlerc.com/D3148 llvm-svn: 204605
2014-03-24 22:05:39 +08:00
#------------------------------------------------------------------------------
# Shortcuts for arithmetic instructions
#------------------------------------------------------------------------------
# CHECK: add $9, $9, $3 # encoding: [0x20,0x48,0x23,0x01]
# CHECK: addu $9, $9, $3 # encoding: [0x21,0x48,0x23,0x01]
# CHECK: addi $9, $9, 10 # encoding: [0x0a,0x00,0x29,0x21]
# CHECK: addiu $9, $9, 10 # encoding: [0x0a,0x00,0x29,0x25]
[mips] Use TwoOperandAliasConstraint for ArithLogicR instructions. This enables TableGen to generate an additional two operand matcher for our ArithLogicR class of instructions (constituted by 3 register operands). E.g.: and $1, $2 <=> and $1, $1, $2 llvm-svn: 204826
2014-03-27 00:09:43 +08:00
# CHECK: and $5, $5, $6 # encoding: [0x24,0x28,0xa6,0x00]
# CHECK: mul $9, $9, $3 # encoding: [0x02,0x48,0x23,0x71]
# CHECK: or $2, $2, $4 # encoding: [0x25,0x10,0x44,0x00]
[mips] Implement shorthand add / sub forms for MIPS. Summary: - If only two registers are passed to a three-register operation, then the first argument is both source and destination register. - If a non-register is passed as the last argument, generate the immediate version of the instruction. Also mark DADD commutative and add scheduling information (to the generic scheduler), and implement DSUB. Patch by David Chisnall His work was sponsored by: DARPA, AFRL CC: theraven Differential Revision: http://llvm-reviews.chandlerc.com/D3148 llvm-svn: 204605
2014-03-24 22:05:39 +08:00
# CHECK: sub $9, $9, $3 # encoding: [0x22,0x48,0x23,0x01]
# CHECK: subu $9, $9, $3 # encoding: [0x23,0x48,0x23,0x01]
# CHECK: addi $9, $9, -10 # encoding: [0xf6,0xff,0x29,0x21]
# CHECK: addiu $9, $9, -10 # encoding: [0xf6,0xff,0x29,0x25]
[mips] Use TwoOperandAliasConstraint for ArithLogicR instructions. This enables TableGen to generate an additional two operand matcher for our ArithLogicR class of instructions (constituted by 3 register operands). E.g.: and $1, $2 <=> and $1, $1, $2 llvm-svn: 204826
2014-03-27 00:09:43 +08:00
# CHECK: xor $9, $9, $10 # encoding: [0x26,0x48,0x2a,0x01]
[mips] Implement shorthand add / sub forms for MIPS. Summary: - If only two registers are passed to a three-register operation, then the first argument is both source and destination register. - If a non-register is passed as the last argument, generate the immediate version of the instruction. Also mark DADD commutative and add scheduling information (to the generic scheduler), and implement DSUB. Patch by David Chisnall His work was sponsored by: DARPA, AFRL CC: theraven Differential Revision: http://llvm-reviews.chandlerc.com/D3148 llvm-svn: 204605
2014-03-24 22:05:39 +08:00
add $9, $3
addu $9, $3
add $9, 10
addu $9, 10
[mips] Use TwoOperandAliasConstraint for ArithLogicR instructions. This enables TableGen to generate an additional two operand matcher for our ArithLogicR class of instructions (constituted by 3 register operands). E.g.: and $1, $2 <=> and $1, $1, $2 llvm-svn: 204826
2014-03-27 00:09:43 +08:00
and $5, $6
mul $9, $3
or $2, $4
[mips] Implement shorthand add / sub forms for MIPS. Summary: - If only two registers are passed to a three-register operation, then the first argument is both source and destination register. - If a non-register is passed as the last argument, generate the immediate version of the instruction. Also mark DADD commutative and add scheduling information (to the generic scheduler), and implement DSUB. Patch by David Chisnall His work was sponsored by: DARPA, AFRL CC: theraven Differential Revision: http://llvm-reviews.chandlerc.com/D3148 llvm-svn: 204605
2014-03-24 22:05:39 +08:00
sub $9, $3
subu $9, $3
sub $9, 10
subu $9, 10
[mips] Use TwoOperandAliasConstraint for ArithLogicR instructions. This enables TableGen to generate an additional two operand matcher for our ArithLogicR class of instructions (constituted by 3 register operands). E.g.: and $1, $2 <=> and $1, $1, $2 llvm-svn: 204826
2014-03-27 00:09:43 +08:00
xor $9, $10