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llvm-project/llvm/test/CodeGen/X86/avx512-select.ll

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AVX512 : Change v8i1 bitconvert GR8 pattern, remove unnecessary movzbl instruction. code example , previous implementation. movzbl %dil, %eax kmovw %eax, %k0 new code kmovw %edi, %k0 Differential Revision: http://reviews.llvm.org/D16287 llvm-svn: 258045
2016-01-18 20:02:45 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
[X86] Add avx512bw command lines to avx512-select.ll Prep for fixing PR42355 and ensuring we have coverage of ISD::SELECT for v64i8/v32i16 on KNL and SKX configs. llvm-svn: 364092
2019-06-22 02:49:42 +08:00
; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=avx512f | FileCheck %s --check-prefixes=X86,X86-AVX512F
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx512f | FileCheck %s --check-prefixes=X64,X64-AVX512F
; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=avx512bw | FileCheck %s --check-prefixes=X86,X86-AVX512BW
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx512bw | FileCheck %s --check-prefixes=X64,X64-AVX512BW
AVX-512: Implemented CMOV for 512-bit vectors llvm-svn: 193747
2013-10-31 21:15:32 +08:00
define <16 x i32> @select00(i32 %a, <16 x i32> %b) nounwind {
[X86][AVX512] Regenerated and added 32-bit targets to select tests llvm-svn: 309098
2017-07-26 18:39:55 +08:00
; X86-LABEL: select00:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; X86: # %bb.0:
[X86][AVX512] Regenerated and added 32-bit targets to select tests llvm-svn: 309098
2017-07-26 18:39:55 +08:00
; X86-NEXT: cmpl $255, {{[0-9]+}}(%esp)
[X86] SET0 to use XMM registers where possible PR26018 PR32862 Differential Revision: https://reviews.llvm.org/D35965 llvm-svn: 309926
2017-08-03 16:50:18 +08:00
; X86-NEXT: vpxor %xmm1, %xmm1, %xmm1
[X86][AVX512] Regenerated and added 32-bit targets to select tests llvm-svn: 309098
2017-07-26 18:39:55 +08:00
; X86-NEXT: je .LBB0_2
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; X86-NEXT: # %bb.1:
[X86][AVX512] Regenerated and added 32-bit targets to select tests llvm-svn: 309098
2017-07-26 18:39:55 +08:00
; X86-NEXT: vmovdqa64 %zmm0, %zmm1
; X86-NEXT: .LBB0_2:
[X86] Stop promoting vector and/or/xor/andn to vXi64. These promotions add additional bitcasts to the SelectionDAG that can pessimize computeKnownBits/computeNumSignBits. It also seems to interfere with broadcast formation. This patch removes the promotion and adds isel patterns instead. The increased table size is more than I would like, but hopefully we can find some canonicalizations or other tricks to start pruning out patterns going forward. Differential Revision: https://reviews.llvm.org/D53268 llvm-svn: 345408
2018-10-27 01:21:26 +08:00
; X86-NEXT: vpxord %zmm1, %zmm0, %zmm0
[X86][AVX512] Regenerated and added 32-bit targets to select tests llvm-svn: 309098
2017-07-26 18:39:55 +08:00
; X86-NEXT: retl
;
; X64-LABEL: select00:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; X64: # %bb.0:
[X86][AVX512] Regenerated and added 32-bit targets to select tests llvm-svn: 309098
2017-07-26 18:39:55 +08:00
; X64-NEXT: cmpl $255, %edi
[X86] Remove some uarch tuning flags from KNL that look to have been inherited from SNB/IVB incorrectly KNL is based on a modified Silvermont core so I don't think these features apply. I think the LEA flag is probably also wrong, but I'm less sure as I barely understand the 3 LEA flags we have currently. Differential Revision: https://reviews.llvm.org/D53671 llvm-svn: 345285
2018-10-26 01:28:57 +08:00
; X64-NEXT: vpxor %xmm1, %xmm1, %xmm1
[X86][AVX512] Regenerated and added 32-bit targets to select tests llvm-svn: 309098
2017-07-26 18:39:55 +08:00
; X64-NEXT: je .LBB0_2
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; X64-NEXT: # %bb.1:
[X86][AVX512] Regenerated and added 32-bit targets to select tests llvm-svn: 309098
2017-07-26 18:39:55 +08:00
; X64-NEXT: vmovdqa64 %zmm0, %zmm1
; X64-NEXT: .LBB0_2:
[X86] Stop promoting vector and/or/xor/andn to vXi64. These promotions add additional bitcasts to the SelectionDAG that can pessimize computeKnownBits/computeNumSignBits. It also seems to interfere with broadcast formation. This patch removes the promotion and adds isel patterns instead. The increased table size is more than I would like, but hopefully we can find some canonicalizations or other tricks to start pruning out patterns going forward. Differential Revision: https://reviews.llvm.org/D53268 llvm-svn: 345408
2018-10-27 01:21:26 +08:00
; X64-NEXT: vpxord %zmm1, %zmm0, %zmm0
[X86][AVX512] Regenerated and added 32-bit targets to select tests llvm-svn: 309098
2017-07-26 18:39:55 +08:00
; X64-NEXT: retq
AVX-512: Implemented CMOV for 512-bit vectors llvm-svn: 193747
2013-10-31 21:15:32 +08:00
%cmpres = icmp eq i32 %a, 255
%selres = select i1 %cmpres, <16 x i32> zeroinitializer, <16 x i32> %b
%res = xor <16 x i32> %b, %selres
ret <16 x i32> %res
}
define <8 x i64> @select01(i32 %a, <8 x i64> %b) nounwind {
[X86][AVX512] Regenerated and added 32-bit targets to select tests llvm-svn: 309098
2017-07-26 18:39:55 +08:00
; X86-LABEL: select01:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; X86: # %bb.0:
[X86][AVX512] Regenerated and added 32-bit targets to select tests llvm-svn: 309098
2017-07-26 18:39:55 +08:00
; X86-NEXT: cmpl $255, {{[0-9]+}}(%esp)
[X86] SET0 to use XMM registers where possible PR26018 PR32862 Differential Revision: https://reviews.llvm.org/D35965 llvm-svn: 309926
2017-08-03 16:50:18 +08:00
; X86-NEXT: vpxor %xmm1, %xmm1, %xmm1
[X86][AVX512] Regenerated and added 32-bit targets to select tests llvm-svn: 309098
2017-07-26 18:39:55 +08:00
; X86-NEXT: je .LBB1_2
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; X86-NEXT: # %bb.1:
[X86][AVX512] Regenerated and added 32-bit targets to select tests llvm-svn: 309098
2017-07-26 18:39:55 +08:00
; X86-NEXT: vmovdqa64 %zmm0, %zmm1
; X86-NEXT: .LBB1_2:
; X86-NEXT: vpxorq %zmm1, %zmm0, %zmm0
; X86-NEXT: retl
;
; X64-LABEL: select01:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; X64: # %bb.0:
[X86][AVX512] Regenerated and added 32-bit targets to select tests llvm-svn: 309098
2017-07-26 18:39:55 +08:00
; X64-NEXT: cmpl $255, %edi
[X86] Remove some uarch tuning flags from KNL that look to have been inherited from SNB/IVB incorrectly KNL is based on a modified Silvermont core so I don't think these features apply. I think the LEA flag is probably also wrong, but I'm less sure as I barely understand the 3 LEA flags we have currently. Differential Revision: https://reviews.llvm.org/D53671 llvm-svn: 345285
2018-10-26 01:28:57 +08:00
; X64-NEXT: vpxor %xmm1, %xmm1, %xmm1
[X86][AVX512] Regenerated and added 32-bit targets to select tests llvm-svn: 309098
2017-07-26 18:39:55 +08:00
; X64-NEXT: je .LBB1_2
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; X64-NEXT: # %bb.1:
[X86][AVX512] Regenerated and added 32-bit targets to select tests llvm-svn: 309098
2017-07-26 18:39:55 +08:00
; X64-NEXT: vmovdqa64 %zmm0, %zmm1
; X64-NEXT: .LBB1_2:
; X64-NEXT: vpxorq %zmm1, %zmm0, %zmm0
; X64-NEXT: retq
AVX-512: Implemented CMOV for 512-bit vectors llvm-svn: 193747
2013-10-31 21:15:32 +08:00
%cmpres = icmp eq i32 %a, 255
%selres = select i1 %cmpres, <8 x i64> zeroinitializer, <8 x i64> %b
%res = xor <8 x i64> %b, %selres
ret <8 x i64> %res
}
AVX-512: Added legal type MVT::i1 and VK1 register for it. Added scalar compare VCMPSS, VCMPSD. Implemented LowerSELECT for scalar FP operations. I replaced FSETCCss, FSETCCsd with one node type FSETCCs. Node extract_vector_elt(v16i1/v8i1, idx) returns an element of type i1. llvm-svn: 197384
2013-12-16 21:52:35 +08:00
define float @select02(float %a, float %b, float %c, float %eps) {
[X86][AVX512] Regenerated and added 32-bit targets to select tests llvm-svn: 309098
2017-07-26 18:39:55 +08:00
; X86-LABEL: select02:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; X86: # %bb.0:
[X86][AVX512] Regenerated and added 32-bit targets to select tests llvm-svn: 309098
2017-07-26 18:39:55 +08:00
; X86-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X86-NEXT: vucomiss {{[0-9]+}}(%esp), %xmm0
; X86-NEXT: leal {{[0-9]+}}(%esp), %eax
; X86-NEXT: leal {{[0-9]+}}(%esp), %ecx
; X86-NEXT: cmovael %eax, %ecx
; X86-NEXT: flds (%ecx)
; X86-NEXT: retl
;
; X64-LABEL: select02:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; X64: # %bb.0:
[X86][AVX512] Regenerated and added 32-bit targets to select tests llvm-svn: 309098
2017-07-26 18:39:55 +08:00
; X64-NEXT: vcmpless %xmm0, %xmm3, %k1
[X86] Add VMOVSSZrrk/VMOVSDZrrk/VMOVSSZrrkz/VMOVSDZrrkz to getUndefRegClearance. We have isel patterns that can put an IMPLICIT_DEF on one of the sources for these instructions. So we should make sure we break any dependencies there. This should be done by just using one of the other sources. llvm-svn: 373025
2019-09-27 06:56:06 +08:00
; X64-NEXT: vmovss %xmm2, %xmm1, %xmm1 {%k1}
[X86][AVX512] Regenerated and added 32-bit targets to select tests llvm-svn: 309098
2017-07-26 18:39:55 +08:00
; X64-NEXT: vmovaps %xmm1, %xmm0
; X64-NEXT: retq
AVX-512: Added legal type MVT::i1 and VK1 register for it. Added scalar compare VCMPSS, VCMPSD. Implemented LowerSELECT for scalar FP operations. I replaced FSETCCss, FSETCCsd with one node type FSETCCs. Node extract_vector_elt(v16i1/v8i1, idx) returns an element of type i1. llvm-svn: 197384
2013-12-16 21:52:35 +08:00
%cmp = fcmp oge float %a, %eps
%cond = select i1 %cmp, float %c, float %b
ret float %cond
}
define double @select03(double %a, double %b, double %c, double %eps) {
[X86][AVX512] Regenerated and added 32-bit targets to select tests llvm-svn: 309098
2017-07-26 18:39:55 +08:00
; X86-LABEL: select03:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; X86: # %bb.0:
[X86][AVX512] Regenerated and added 32-bit targets to select tests llvm-svn: 309098
2017-07-26 18:39:55 +08:00
; X86-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; X86-NEXT: vucomisd {{[0-9]+}}(%esp), %xmm0
; X86-NEXT: leal {{[0-9]+}}(%esp), %eax
; X86-NEXT: leal {{[0-9]+}}(%esp), %ecx
; X86-NEXT: cmovael %eax, %ecx
; X86-NEXT: fldl (%ecx)
; X86-NEXT: retl
;
; X64-LABEL: select03:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; X64: # %bb.0:
[X86][AVX512] Regenerated and added 32-bit targets to select tests llvm-svn: 309098
2017-07-26 18:39:55 +08:00
; X64-NEXT: vcmplesd %xmm0, %xmm3, %k1
[X86] Add VMOVSSZrrk/VMOVSDZrrk/VMOVSSZrrkz/VMOVSDZrrkz to getUndefRegClearance. We have isel patterns that can put an IMPLICIT_DEF on one of the sources for these instructions. So we should make sure we break any dependencies there. This should be done by just using one of the other sources. llvm-svn: 373025
2019-09-27 06:56:06 +08:00
; X64-NEXT: vmovsd %xmm2, %xmm1, %xmm1 {%k1}
[X86][AVX512] Regenerated and added 32-bit targets to select tests llvm-svn: 309098
2017-07-26 18:39:55 +08:00
; X64-NEXT: vmovapd %xmm1, %xmm0
; X64-NEXT: retq
AVX-512: Added legal type MVT::i1 and VK1 register for it. Added scalar compare VCMPSS, VCMPSD. Implemented LowerSELECT for scalar FP operations. I replaced FSETCCss, FSETCCsd with one node type FSETCCs. Node extract_vector_elt(v16i1/v8i1, idx) returns an element of type i1. llvm-svn: 197384
2013-12-16 21:52:35 +08:00
%cmp = fcmp oge double %a, %eps
%cond = select i1 %cmp, double %c, double %b
ret double %cond
}
DAGCombiner: Make concat_vector combine safe for EVTs and concat_vectors with many arguments. PR20677 llvm-svn: 216175
2014-08-21 21:28:02 +08:00
define <16 x double> @select04(<16 x double> %a, <16 x double> %b) {
[X86][AVX512] Regenerated and added 32-bit targets to select tests llvm-svn: 309098
2017-07-26 18:39:55 +08:00
; X86-LABEL: select04:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; X86: # %bb.0:
[X86][AVX512] Regenerated and added 32-bit targets to select tests llvm-svn: 309098
2017-07-26 18:39:55 +08:00
; X86-NEXT: pushl %ebp
; X86-NEXT: .cfi_def_cfa_offset 8
; X86-NEXT: .cfi_offset %ebp, -8
; X86-NEXT: movl %esp, %ebp
; X86-NEXT: .cfi_def_cfa_register %ebp
; X86-NEXT: andl $-64, %esp
; X86-NEXT: subl $64, %esp
; X86-NEXT: vmovaps 8(%ebp), %zmm1
; X86-NEXT: movl %ebp, %esp
; X86-NEXT: popl %ebp
Correct dwarf unwind information in function epilogue This patch aims to provide correct dwarf unwind information in function epilogue for X86. It consists of two parts. The first part inserts CFI instructions that set appropriate cfa offset and cfa register in emitEpilogue() in X86FrameLowering. This part is X86 specific. The second part is platform independent and ensures that: * CFI instructions do not affect code generation (they are not counted as instructions when tail duplicating or tail merging) * Unwind information remains correct when a function is modified by different passes. This is done in a late pass by analyzing information about cfa offset and cfa register in BBs and inserting additional CFI directives where necessary. Added CFIInstrInserter pass: * analyzes each basic block to determine cfa offset and register are valid at its entry and exit * verifies that outgoing cfa offset and register of predecessor blocks match incoming values of their successors * inserts additional CFI directives at basic block beginning to correct the rule for calculating CFA Having CFI instructions in function epilogue can cause incorrect CFA calculation rule for some basic blocks. This can happen if, due to basic block reordering, or the existence of multiple epilogue blocks, some of the blocks have wrong cfa offset and register values set by the epilogue block above them. CFIInstrInserter is currently run only on X86, but can be used by any target that implements support for adding CFI instructions in epilogue. Patch by Violeta Vukobrat. Differential Revision: https://reviews.llvm.org/D42848 llvm-svn: 330706
2018-04-24 18:32:08 +08:00
; X86-NEXT: .cfi_def_cfa %esp, 4
[X86][AVX512] Regenerated and added 32-bit targets to select tests llvm-svn: 309098
2017-07-26 18:39:55 +08:00
; X86-NEXT: retl
;
; X64-LABEL: select04:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; X64: # %bb.0:
[X86][AVX512] Regenerated and added 32-bit targets to select tests llvm-svn: 309098
2017-07-26 18:39:55 +08:00
; X64-NEXT: vmovaps %zmm3, %zmm1
; X64-NEXT: retq
DAGCombiner: Make concat_vector combine safe for EVTs and concat_vectors with many arguments. PR20677 llvm-svn: 216175
2014-08-21 21:28:02 +08:00
%sel = select <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false>, <16 x double> %a, <16 x double> %b
ret <16 x double> %sel
}
Revert "Temporarily revert r220777 to sort out build bot breakage." This reverts commit r221028. Later commits depend on this and reverting just this one causes even more bots to fail. llvm-svn: 221041
2014-11-01 11:19:45 +08:00
define i8 @select05(i8 %a.0, i8 %m) {
[X86][AVX512] Regenerated and added 32-bit targets to select tests llvm-svn: 309098
2017-07-26 18:39:55 +08:00
; X86-LABEL: select05:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; X86: # %bb.0:
[X86][AVX512] Regenerated and added 32-bit targets to select tests llvm-svn: 309098
2017-07-26 18:39:55 +08:00
; X86-NEXT: movb {{[0-9]+}}(%esp), %al
; X86-NEXT: orb {{[0-9]+}}(%esp), %al
; X86-NEXT: retl
;
; X64-LABEL: select05:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; X64: # %bb.0:
[X86][AVX512] Regenerated and added 32-bit targets to select tests llvm-svn: 309098
2017-07-26 18:39:55 +08:00
; X64-NEXT: movl %edi, %eax
[X86] Handle COPYs of physregs better (regalloc hints) Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
2018-09-20 02:59:08 +08:00
; X64-NEXT: orl %esi, %eax
; X64-NEXT: # kill: def $al killed $al killed $eax
[X86][AVX512] Regenerated and added 32-bit targets to select tests llvm-svn: 309098
2017-07-26 18:39:55 +08:00
; X64-NEXT: retq
Revert "Temporarily revert r220777 to sort out build bot breakage." This reverts commit r221028. Later commits depend on this and reverting just this one causes even more bots to fail. llvm-svn: 221041
2014-11-01 11:19:45 +08:00
%mask = bitcast i8 %m to <8 x i1>
%a = bitcast i8 %a.0 to <8 x i1>
%r = select <8 x i1> %mask, <8 x i1> <i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1>, <8 x i1> %a
%res = bitcast <8 x i1> %r to i8
ret i8 %res;
}
[DAGCombiner] Fold xor/and/or (bitcast(A), bitcast(B)) -> bitcast(op (A,B)) anytime before LegalizeVectorOprs xor/and/or (bitcast(A), bitcast(B)) -> bitcast(op (A,B)) was only being combined at the AfterLegalizeTypes stage, this patch permits the combine to occur anytime before then as well. The main aim with this to improve the ability to recognise bitmasks that can be converted to shuffles. I had to modify a number of AVX512 mask tests as the basic bitcast to/from scalar pattern was being stripped out, preventing testing of the mmask bitops. By replacing the bitcasts with loads we can get almost the same result. Differential Revision: http://reviews.llvm.org/D18944 llvm-svn: 265998
2016-04-12 05:10:33 +08:00
define i8 @select05_mem(<8 x i1>* %a.0, <8 x i1>* %m) {
[X86] Add avx512bw command lines to avx512-select.ll Prep for fixing PR42355 and ensuring we have coverage of ISD::SELECT for v64i8/v32i16 on KNL and SKX configs. llvm-svn: 364092
2019-06-22 02:49:42 +08:00
; X86-AVX512F-LABEL: select05_mem:
; X86-AVX512F: # %bb.0:
; X86-AVX512F-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-AVX512F-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-AVX512F-NEXT: kmovw (%ecx), %k0
; X86-AVX512F-NEXT: kmovw (%eax), %k1
; X86-AVX512F-NEXT: korw %k1, %k0, %k0
; X86-AVX512F-NEXT: kmovw %k0, %eax
; X86-AVX512F-NEXT: # kill: def $al killed $al killed $eax
; X86-AVX512F-NEXT: retl
[X86][AVX512] Regenerated and added 32-bit targets to select tests llvm-svn: 309098
2017-07-26 18:39:55 +08:00
;
[X86] Add avx512bw command lines to avx512-select.ll Prep for fixing PR42355 and ensuring we have coverage of ISD::SELECT for v64i8/v32i16 on KNL and SKX configs. llvm-svn: 364092
2019-06-22 02:49:42 +08:00
; X64-AVX512F-LABEL: select05_mem:
; X64-AVX512F: # %bb.0:
; X64-AVX512F-NEXT: kmovw (%rsi), %k0
; X64-AVX512F-NEXT: kmovw (%rdi), %k1
; X64-AVX512F-NEXT: korw %k1, %k0, %k0
; X64-AVX512F-NEXT: kmovw %k0, %eax
; X64-AVX512F-NEXT: # kill: def $al killed $al killed $eax
; X64-AVX512F-NEXT: retq
;
; X86-AVX512BW-LABEL: select05_mem:
; X86-AVX512BW: # %bb.0:
; X86-AVX512BW-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-AVX512BW-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-AVX512BW-NEXT: kmovw (%ecx), %k0
; X86-AVX512BW-NEXT: kmovw (%eax), %k1
; X86-AVX512BW-NEXT: korw %k1, %k0, %k0
; X86-AVX512BW-NEXT: kmovd %k0, %eax
; X86-AVX512BW-NEXT: # kill: def $al killed $al killed $eax
; X86-AVX512BW-NEXT: retl
;
; X64-AVX512BW-LABEL: select05_mem:
; X64-AVX512BW: # %bb.0:
; X64-AVX512BW-NEXT: kmovw (%rsi), %k0
; X64-AVX512BW-NEXT: kmovw (%rdi), %k1
; X64-AVX512BW-NEXT: korw %k1, %k0, %k0
; X64-AVX512BW-NEXT: kmovd %k0, %eax
; X64-AVX512BW-NEXT: # kill: def $al killed $al killed $eax
; X64-AVX512BW-NEXT: retq
[DAGCombiner] Fold xor/and/or (bitcast(A), bitcast(B)) -> bitcast(op (A,B)) anytime before LegalizeVectorOprs xor/and/or (bitcast(A), bitcast(B)) -> bitcast(op (A,B)) was only being combined at the AfterLegalizeTypes stage, this patch permits the combine to occur anytime before then as well. The main aim with this to improve the ability to recognise bitmasks that can be converted to shuffles. I had to modify a number of AVX512 mask tests as the basic bitcast to/from scalar pattern was being stripped out, preventing testing of the mmask bitops. By replacing the bitcasts with loads we can get almost the same result. Differential Revision: http://reviews.llvm.org/D18944 llvm-svn: 265998
2016-04-12 05:10:33 +08:00
%mask = load <8 x i1> , <8 x i1>* %m
%a = load <8 x i1> , <8 x i1>* %a.0
%r = select <8 x i1> %mask, <8 x i1> <i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1>, <8 x i1> %a
%res = bitcast <8 x i1> %r to i8
ret i8 %res;
}
Revert "Temporarily revert r220777 to sort out build bot breakage." This reverts commit r221028. Later commits depend on this and reverting just this one causes even more bots to fail. llvm-svn: 221041
2014-11-01 11:19:45 +08:00
define i8 @select06(i8 %a.0, i8 %m) {
[X86][AVX512] Regenerated and added 32-bit targets to select tests llvm-svn: 309098
2017-07-26 18:39:55 +08:00
; X86-LABEL: select06:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; X86: # %bb.0:
[X86][AVX512] Regenerated and added 32-bit targets to select tests llvm-svn: 309098
2017-07-26 18:39:55 +08:00
; X86-NEXT: movb {{[0-9]+}}(%esp), %al
; X86-NEXT: andb {{[0-9]+}}(%esp), %al
; X86-NEXT: retl
;
; X64-LABEL: select06:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; X64: # %bb.0:
[X86][AVX512] Regenerated and added 32-bit targets to select tests llvm-svn: 309098
2017-07-26 18:39:55 +08:00
; X64-NEXT: movl %edi, %eax
[X86] Handle COPYs of physregs better (regalloc hints) Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
2018-09-20 02:59:08 +08:00
; X64-NEXT: andl %esi, %eax
; X64-NEXT: # kill: def $al killed $al killed $eax
[X86][AVX512] Regenerated and added 32-bit targets to select tests llvm-svn: 309098
2017-07-26 18:39:55 +08:00
; X64-NEXT: retq
Revert "Temporarily revert r220777 to sort out build bot breakage." This reverts commit r221028. Later commits depend on this and reverting just this one causes even more bots to fail. llvm-svn: 221041
2014-11-01 11:19:45 +08:00
%mask = bitcast i8 %m to <8 x i1>
%a = bitcast i8 %a.0 to <8 x i1>
%r = select <8 x i1> %mask, <8 x i1> %a, <8 x i1> zeroinitializer
%res = bitcast <8 x i1> %r to i8
ret i8 %res;
}
[DAGCombiner] Fold xor/and/or (bitcast(A), bitcast(B)) -> bitcast(op (A,B)) anytime before LegalizeVectorOprs xor/and/or (bitcast(A), bitcast(B)) -> bitcast(op (A,B)) was only being combined at the AfterLegalizeTypes stage, this patch permits the combine to occur anytime before then as well. The main aim with this to improve the ability to recognise bitmasks that can be converted to shuffles. I had to modify a number of AVX512 mask tests as the basic bitcast to/from scalar pattern was being stripped out, preventing testing of the mmask bitops. By replacing the bitcasts with loads we can get almost the same result. Differential Revision: http://reviews.llvm.org/D18944 llvm-svn: 265998
2016-04-12 05:10:33 +08:00
define i8 @select06_mem(<8 x i1>* %a.0, <8 x i1>* %m) {
[X86] Add avx512bw command lines to avx512-select.ll Prep for fixing PR42355 and ensuring we have coverage of ISD::SELECT for v64i8/v32i16 on KNL and SKX configs. llvm-svn: 364092
2019-06-22 02:49:42 +08:00
; X86-AVX512F-LABEL: select06_mem:
; X86-AVX512F: # %bb.0:
; X86-AVX512F-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-AVX512F-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-AVX512F-NEXT: kmovw (%ecx), %k0
; X86-AVX512F-NEXT: kmovw (%eax), %k1
; X86-AVX512F-NEXT: kandw %k1, %k0, %k0
; X86-AVX512F-NEXT: kmovw %k0, %eax
; X86-AVX512F-NEXT: # kill: def $al killed $al killed $eax
; X86-AVX512F-NEXT: retl
[X86][AVX512] Regenerated and added 32-bit targets to select tests llvm-svn: 309098
2017-07-26 18:39:55 +08:00
;
[X86] Add avx512bw command lines to avx512-select.ll Prep for fixing PR42355 and ensuring we have coverage of ISD::SELECT for v64i8/v32i16 on KNL and SKX configs. llvm-svn: 364092
2019-06-22 02:49:42 +08:00
; X64-AVX512F-LABEL: select06_mem:
; X64-AVX512F: # %bb.0:
; X64-AVX512F-NEXT: kmovw (%rsi), %k0
; X64-AVX512F-NEXT: kmovw (%rdi), %k1
; X64-AVX512F-NEXT: kandw %k1, %k0, %k0
; X64-AVX512F-NEXT: kmovw %k0, %eax
; X64-AVX512F-NEXT: # kill: def $al killed $al killed $eax
; X64-AVX512F-NEXT: retq
;
; X86-AVX512BW-LABEL: select06_mem:
; X86-AVX512BW: # %bb.0:
; X86-AVX512BW-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-AVX512BW-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-AVX512BW-NEXT: kmovw (%ecx), %k0
; X86-AVX512BW-NEXT: kmovw (%eax), %k1
; X86-AVX512BW-NEXT: kandw %k1, %k0, %k0
; X86-AVX512BW-NEXT: kmovd %k0, %eax
; X86-AVX512BW-NEXT: # kill: def $al killed $al killed $eax
; X86-AVX512BW-NEXT: retl
;
; X64-AVX512BW-LABEL: select06_mem:
; X64-AVX512BW: # %bb.0:
; X64-AVX512BW-NEXT: kmovw (%rsi), %k0
; X64-AVX512BW-NEXT: kmovw (%rdi), %k1
; X64-AVX512BW-NEXT: kandw %k1, %k0, %k0
; X64-AVX512BW-NEXT: kmovd %k0, %eax
; X64-AVX512BW-NEXT: # kill: def $al killed $al killed $eax
; X64-AVX512BW-NEXT: retq
[DAGCombiner] Fold xor/and/or (bitcast(A), bitcast(B)) -> bitcast(op (A,B)) anytime before LegalizeVectorOprs xor/and/or (bitcast(A), bitcast(B)) -> bitcast(op (A,B)) was only being combined at the AfterLegalizeTypes stage, this patch permits the combine to occur anytime before then as well. The main aim with this to improve the ability to recognise bitmasks that can be converted to shuffles. I had to modify a number of AVX512 mask tests as the basic bitcast to/from scalar pattern was being stripped out, preventing testing of the mmask bitops. By replacing the bitcasts with loads we can get almost the same result. Differential Revision: http://reviews.llvm.org/D18944 llvm-svn: 265998
2016-04-12 05:10:33 +08:00
%mask = load <8 x i1> , <8 x i1>* %m
%a = load <8 x i1> , <8 x i1>* %a.0
%r = select <8 x i1> %mask, <8 x i1> %a, <8 x i1> zeroinitializer
%res = bitcast <8 x i1> %r to i8
ret i8 %res;
}
Revert "Temporarily revert r220777 to sort out build bot breakage." This reverts commit r221028. Later commits depend on this and reverting just this one causes even more bots to fail. llvm-svn: 221041
2014-11-01 11:19:45 +08:00
define i8 @select07(i8 %a.0, i8 %b.0, i8 %m) {
[X86] Add avx512bw command lines to avx512-select.ll Prep for fixing PR42355 and ensuring we have coverage of ISD::SELECT for v64i8/v32i16 on KNL and SKX configs. llvm-svn: 364092
2019-06-22 02:49:42 +08:00
; X86-AVX512F-LABEL: select07:
; X86-AVX512F: # %bb.0:
; X86-AVX512F-NEXT: movzbl {{[0-9]+}}(%esp), %eax
; X86-AVX512F-NEXT: kmovw %eax, %k0
; X86-AVX512F-NEXT: movzbl {{[0-9]+}}(%esp), %eax
; X86-AVX512F-NEXT: kmovw %eax, %k1
; X86-AVX512F-NEXT: movzbl {{[0-9]+}}(%esp), %eax
; X86-AVX512F-NEXT: kmovw %eax, %k2
; X86-AVX512F-NEXT: kandnw %k2, %k0, %k2
; X86-AVX512F-NEXT: kandw %k0, %k1, %k0
; X86-AVX512F-NEXT: korw %k2, %k0, %k0
; X86-AVX512F-NEXT: kmovw %k0, %eax
; X86-AVX512F-NEXT: # kill: def $al killed $al killed $eax
; X86-AVX512F-NEXT: retl
[X86][AVX512] Regenerated and added 32-bit targets to select tests llvm-svn: 309098
2017-07-26 18:39:55 +08:00
;
[X86] Add avx512bw command lines to avx512-select.ll Prep for fixing PR42355 and ensuring we have coverage of ISD::SELECT for v64i8/v32i16 on KNL and SKX configs. llvm-svn: 364092
2019-06-22 02:49:42 +08:00
; X64-AVX512F-LABEL: select07:
; X64-AVX512F: # %bb.0:
; X64-AVX512F-NEXT: kmovw %edx, %k0
; X64-AVX512F-NEXT: kmovw %edi, %k1
; X64-AVX512F-NEXT: kmovw %esi, %k2
; X64-AVX512F-NEXT: kandnw %k2, %k0, %k2
; X64-AVX512F-NEXT: kandw %k0, %k1, %k0
; X64-AVX512F-NEXT: korw %k2, %k0, %k0
; X64-AVX512F-NEXT: kmovw %k0, %eax
; X64-AVX512F-NEXT: # kill: def $al killed $al killed $eax
; X64-AVX512F-NEXT: retq
;
; X86-AVX512BW-LABEL: select07:
; X86-AVX512BW: # %bb.0:
; X86-AVX512BW-NEXT: movzbl {{[0-9]+}}(%esp), %eax
; X86-AVX512BW-NEXT: kmovd %eax, %k0
; X86-AVX512BW-NEXT: movzbl {{[0-9]+}}(%esp), %eax
; X86-AVX512BW-NEXT: kmovd %eax, %k1
; X86-AVX512BW-NEXT: movzbl {{[0-9]+}}(%esp), %eax
; X86-AVX512BW-NEXT: kmovd %eax, %k2
; X86-AVX512BW-NEXT: kandnw %k2, %k0, %k2
; X86-AVX512BW-NEXT: kandw %k0, %k1, %k0
; X86-AVX512BW-NEXT: korw %k2, %k0, %k0
; X86-AVX512BW-NEXT: kmovd %k0, %eax
; X86-AVX512BW-NEXT: # kill: def $al killed $al killed $eax
; X86-AVX512BW-NEXT: retl
;
; X64-AVX512BW-LABEL: select07:
; X64-AVX512BW: # %bb.0:
; X64-AVX512BW-NEXT: kmovd %edx, %k0
; X64-AVX512BW-NEXT: kmovd %edi, %k1
; X64-AVX512BW-NEXT: kmovd %esi, %k2
; X64-AVX512BW-NEXT: kandnw %k2, %k0, %k2
; X64-AVX512BW-NEXT: kandw %k0, %k1, %k0
; X64-AVX512BW-NEXT: korw %k2, %k0, %k0
; X64-AVX512BW-NEXT: kmovd %k0, %eax
; X64-AVX512BW-NEXT: # kill: def $al killed $al killed $eax
; X64-AVX512BW-NEXT: retq
Revert "Temporarily revert r220777 to sort out build bot breakage." This reverts commit r221028. Later commits depend on this and reverting just this one causes even more bots to fail. llvm-svn: 221041
2014-11-01 11:19:45 +08:00
%mask = bitcast i8 %m to <8 x i1>
%a = bitcast i8 %a.0 to <8 x i1>
%b = bitcast i8 %b.0 to <8 x i1>
%r = select <8 x i1> %mask, <8 x i1> %a, <8 x i1> %b
%res = bitcast <8 x i1> %r to i8
ret i8 %res;
}
add select i1 test, reproduser pr30249. llvm-svn: 281218
2016-09-12 23:27:02 +08:00
define i64 @pr30249() {
[X86][AVX512] Regenerated and added 32-bit targets to select tests llvm-svn: 309098
2017-07-26 18:39:55 +08:00
; X86-LABEL: pr30249:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; X86: # %bb.0:
[DAG] add undef simplifications for select nodes Sadly, this duplicates (twice) the logic from InstSimplify. There might be some way to at least share the DAG versions of the code, but copying the folds seems to be the standard method to ensure that we don't miss these folds. Unlike in IR, we don't run DAGCombiner to fixpoint, so there's no way to ensure that we do these kinds of simplifications unless the code is repeated at node creation time and during combines. There were other tests that would become worthless with this improvement that I changed as pre-commits: rL347161 rL347164 rL347165 rL347166 rL347167 I'm not sure how to salvage the remaining tests (diffs in this patch). So the x86 tests verify that the new code is working as intended. The AMDGPU test is actually similar to my motivating case: we have some undef value that has survived to machine IR in an x86 test, and then it gets folded in some weird way, or we crash if we don't transfer the undef flag. But we would have been better off never getting to that point by doing these simplifications. This will lead back to PR32023 someday... https://bugs.llvm.org/show_bug.cgi?id=32023 llvm-svn: 347170
2018-11-19 01:36:23 +08:00
; X86-NEXT: movl $1, %eax
[X86][AVX512] Regenerated and added 32-bit targets to select tests llvm-svn: 309098
2017-07-26 18:39:55 +08:00
; X86-NEXT: xorl %edx, %edx
; X86-NEXT: retl
;
; X64-LABEL: pr30249:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; X64: # %bb.0:
[DAG] add undef simplifications for select nodes Sadly, this duplicates (twice) the logic from InstSimplify. There might be some way to at least share the DAG versions of the code, but copying the folds seems to be the standard method to ensure that we don't miss these folds. Unlike in IR, we don't run DAGCombiner to fixpoint, so there's no way to ensure that we do these kinds of simplifications unless the code is repeated at node creation time and during combines. There were other tests that would become worthless with this improvement that I changed as pre-commits: rL347161 rL347164 rL347165 rL347166 rL347167 I'm not sure how to salvage the remaining tests (diffs in this patch). So the x86 tests verify that the new code is working as intended. The AMDGPU test is actually similar to my motivating case: we have some undef value that has survived to machine IR in an x86 test, and then it gets folded in some weird way, or we crash if we don't transfer the undef flag. But we would have been better off never getting to that point by doing these simplifications. This will lead back to PR32023 someday... https://bugs.llvm.org/show_bug.cgi?id=32023 llvm-svn: 347170
2018-11-19 01:36:23 +08:00
; X64-NEXT: movl $1, %eax
[X86][AVX512] Regenerated and added 32-bit targets to select tests llvm-svn: 309098
2017-07-26 18:39:55 +08:00
; X64-NEXT: retq
add select i1 test, reproduser pr30249. llvm-svn: 281218
2016-09-12 23:27:02 +08:00
%v = select i1 undef , i64 1, i64 2
ret i64 %v
}
Add test-cases which demontrate pr30561 llvm-svn: 283436
2016-10-06 18:04:00 +08:00
[X86] AVX512 fallback for floating-point scalar selects Summary: In the case where of 'select i1 , f32, f32' or select i1, f64, f64 prefer lowering to masked-moves over branches. Fixes pr30561 Reviewers: igorb, aymanmus, delena Differential Revision: https://reviews.llvm.org/D25310 llvm-svn: 285196
2016-10-26 22:12:46 +08:00
define double @pr30561_f64(double %b, double %a, i1 %c) {
[X86][AVX512] Regenerated and added 32-bit targets to select tests llvm-svn: 309098
2017-07-26 18:39:55 +08:00
; X86-LABEL: pr30561_f64:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; X86: # %bb.0:
[X86][AVX512] Regenerated and added 32-bit targets to select tests llvm-svn: 309098
2017-07-26 18:39:55 +08:00
; X86-NEXT: testb $1, {{[0-9]+}}(%esp)
; X86-NEXT: leal {{[0-9]+}}(%esp), %eax
; X86-NEXT: leal {{[0-9]+}}(%esp), %ecx
; X86-NEXT: cmovnel %eax, %ecx
; X86-NEXT: fldl (%ecx)
; X86-NEXT: retl
;
[X86] Add avx512bw command lines to avx512-select.ll Prep for fixing PR42355 and ensuring we have coverage of ISD::SELECT for v64i8/v32i16 on KNL and SKX configs. llvm-svn: 364092
2019-06-22 02:49:42 +08:00
; X64-AVX512F-LABEL: pr30561_f64:
; X64-AVX512F: # %bb.0:
; X64-AVX512F-NEXT: kmovw %edi, %k1
; X64-AVX512F-NEXT: vmovsd %xmm1, %xmm0, %xmm0 {%k1}
; X64-AVX512F-NEXT: retq
;
; X64-AVX512BW-LABEL: pr30561_f64:
; X64-AVX512BW: # %bb.0:
; X64-AVX512BW-NEXT: kmovd %edi, %k1
; X64-AVX512BW-NEXT: vmovsd %xmm1, %xmm0, %xmm0 {%k1}
; X64-AVX512BW-NEXT: retq
Add test-cases which demontrate pr30561 llvm-svn: 283436
2016-10-06 18:04:00 +08:00
%cond = select i1 %c, double %a, double %b
ret double %cond
}
[X86] AVX512 fallback for floating-point scalar selects Summary: In the case where of 'select i1 , f32, f32' or select i1, f64, f64 prefer lowering to masked-moves over branches. Fixes pr30561 Reviewers: igorb, aymanmus, delena Differential Revision: https://reviews.llvm.org/D25310 llvm-svn: 285196
2016-10-26 22:12:46 +08:00
define float @pr30561_f32(float %b, float %a, i1 %c) {
[X86][AVX512] Regenerated and added 32-bit targets to select tests llvm-svn: 309098
2017-07-26 18:39:55 +08:00
; X86-LABEL: pr30561_f32:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; X86: # %bb.0:
[X86][AVX512] Regenerated and added 32-bit targets to select tests llvm-svn: 309098
2017-07-26 18:39:55 +08:00
; X86-NEXT: testb $1, {{[0-9]+}}(%esp)
; X86-NEXT: leal {{[0-9]+}}(%esp), %eax
; X86-NEXT: leal {{[0-9]+}}(%esp), %ecx
; X86-NEXT: cmovnel %eax, %ecx
; X86-NEXT: flds (%ecx)
; X86-NEXT: retl
;
[X86] Add avx512bw command lines to avx512-select.ll Prep for fixing PR42355 and ensuring we have coverage of ISD::SELECT for v64i8/v32i16 on KNL and SKX configs. llvm-svn: 364092
2019-06-22 02:49:42 +08:00
; X64-AVX512F-LABEL: pr30561_f32:
; X64-AVX512F: # %bb.0:
; X64-AVX512F-NEXT: kmovw %edi, %k1
; X64-AVX512F-NEXT: vmovss %xmm1, %xmm0, %xmm0 {%k1}
; X64-AVX512F-NEXT: retq
;
; X64-AVX512BW-LABEL: pr30561_f32:
; X64-AVX512BW: # %bb.0:
; X64-AVX512BW-NEXT: kmovd %edi, %k1
; X64-AVX512BW-NEXT: vmovss %xmm1, %xmm0, %xmm0 {%k1}
; X64-AVX512BW-NEXT: retq
Add test-cases which demontrate pr30561 llvm-svn: 283436
2016-10-06 18:04:00 +08:00
%cond = select i1 %c, float %a, float %b
ret float %cond
}
[X86][AVX512] Fix PR31515 - Do not flip vselect condition if it's not a vXi1 mask r289653 added a case where `vselect <cond> <vector1> <all-zeros>` is transformed to: `vselect xor(cond, DAG.getConstant(1, DL, CondVT) <all-zeros> <vector1>` This was not aimed to catch cases where Cond is not a vXi1 mask but it does. Moreover, when Cond type is VxiN (N > 1) then xor(cond, DAG.getConstant(1, DL, CondVT) != NOT(cond). This patch changes the above to xor with allones, and avoids entering the case for non-mask Conds. llvm-svn: 291745
2017-01-12 14:49:03 +08:00
define <16 x i16> @pr31515(<16 x i1> %a, <16 x i1> %b, <16 x i16> %c) nounwind {
[X86] Add avx512bw command lines to avx512-select.ll Prep for fixing PR42355 and ensuring we have coverage of ISD::SELECT for v64i8/v32i16 on KNL and SKX configs. llvm-svn: 364092
2019-06-22 02:49:42 +08:00
; X86-AVX512F-LABEL: pr31515:
; X86-AVX512F: # %bb.0:
; X86-AVX512F-NEXT: vpand %xmm1, %xmm0, %xmm0
; X86-AVX512F-NEXT: vpmovzxbw {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
; X86-AVX512F-NEXT: vpsllw $15, %ymm0, %ymm0
; X86-AVX512F-NEXT: vpsraw $15, %ymm0, %ymm0
; X86-AVX512F-NEXT: vpandn %ymm2, %ymm0, %ymm0
; X86-AVX512F-NEXT: retl
[X86][AVX512] Regenerated and added 32-bit targets to select tests llvm-svn: 309098
2017-07-26 18:39:55 +08:00
;
[X86] Add avx512bw command lines to avx512-select.ll Prep for fixing PR42355 and ensuring we have coverage of ISD::SELECT for v64i8/v32i16 on KNL and SKX configs. llvm-svn: 364092
2019-06-22 02:49:42 +08:00
; X64-AVX512F-LABEL: pr31515:
; X64-AVX512F: # %bb.0:
; X64-AVX512F-NEXT: vpand %xmm1, %xmm0, %xmm0
; X64-AVX512F-NEXT: vpmovzxbw {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
; X64-AVX512F-NEXT: vpsllw $15, %ymm0, %ymm0
; X64-AVX512F-NEXT: vpsraw $15, %ymm0, %ymm0
; X64-AVX512F-NEXT: vpandn %ymm2, %ymm0, %ymm0
; X64-AVX512F-NEXT: retq
;
; X86-AVX512BW-LABEL: pr31515:
; X86-AVX512BW: # %bb.0:
; X86-AVX512BW-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2
; X86-AVX512BW-NEXT: vpand %xmm1, %xmm0, %xmm0
; X86-AVX512BW-NEXT: vpsllw $7, %xmm0, %xmm0
; X86-AVX512BW-NEXT: vpmovb2m %zmm0, %k0
; X86-AVX512BW-NEXT: knotw %k0, %k1
; X86-AVX512BW-NEXT: vmovdqu16 %zmm2, %zmm0 {%k1} {z}
; X86-AVX512BW-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0
; X86-AVX512BW-NEXT: retl
;
; X64-AVX512BW-LABEL: pr31515:
; X64-AVX512BW: # %bb.0:
; X64-AVX512BW-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2
; X64-AVX512BW-NEXT: vpand %xmm1, %xmm0, %xmm0
; X64-AVX512BW-NEXT: vpsllw $7, %xmm0, %xmm0
; X64-AVX512BW-NEXT: vpmovb2m %zmm0, %k0
; X64-AVX512BW-NEXT: knotw %k0, %k1
; X64-AVX512BW-NEXT: vmovdqu16 %zmm2, %zmm0 {%k1} {z}
; X64-AVX512BW-NEXT: # kill: def $ymm0 killed $ymm0 killed $zmm0
; X64-AVX512BW-NEXT: retq
[X86][AVX512] Fix PR31515 - Do not flip vselect condition if it's not a vXi1 mask r289653 added a case where `vselect <cond> <vector1> <all-zeros>` is transformed to: `vselect xor(cond, DAG.getConstant(1, DL, CondVT) <all-zeros> <vector1>` This was not aimed to catch cases where Cond is not a vXi1 mask but it does. Moreover, when Cond type is VxiN (N > 1) then xor(cond, DAG.getConstant(1, DL, CondVT) != NOT(cond). This patch changes the above to xor with allones, and avoids entering the case for non-mask Conds. llvm-svn: 291745
2017-01-12 14:49:03 +08:00
%mask = and <16 x i1> %a, %b
%res = select <16 x i1> %mask, <16 x i16> zeroinitializer, <16 x i16> %c
ret <16 x i16> %res
}
[X86] Don't mark v64i8/v32i16 ISD::SELECT as custom unless they are legal types. We don't have any Custom handling during type legalization. Only operation legalization. Fixes PR42355 llvm-svn: 364093
2019-06-22 02:50:00 +08:00
define <32 x i16> @pr42355_v32i16(i1 %c, <32 x i16> %x, <32 x i16> %y) {
; X86-AVX512F-LABEL: pr42355_v32i16:
; X86-AVX512F: # %bb.0:
[X86] Pass v32i16/v64i8 in zmm registers on KNL target. gcc and icc pass these types in zmm registers in zmm registers. This patch implements a quick hack to override the register type before calling convention handling to one that is legal. Longer term we might want to do something similar to 256-bit integer registers on AVX1 where we just split all the operations. Fixes PR42957 Differential Revision: https://reviews.llvm.org/D66708 llvm-svn: 370495
2019-08-31 01:35:08 +08:00
; X86-AVX512F-NEXT: testb $1, {{[0-9]+}}(%esp)
; X86-AVX512F-NEXT: jne .LBB14_1
; X86-AVX512F-NEXT: # %bb.2:
; X86-AVX512F-NEXT: vextractf64x4 $1, %zmm1, %ymm2
; X86-AVX512F-NEXT: vmovaps %ymm1, %ymm0
; X86-AVX512F-NEXT: vinsertf64x4 $1, %ymm2, %zmm0, %zmm0
; X86-AVX512F-NEXT: retl
; X86-AVX512F-NEXT: .LBB14_1:
; X86-AVX512F-NEXT: vextractf64x4 $1, %zmm0, %ymm2
; X86-AVX512F-NEXT: vinsertf64x4 $1, %ymm2, %zmm0, %zmm0
[X86] Don't mark v64i8/v32i16 ISD::SELECT as custom unless they are legal types. We don't have any Custom handling during type legalization. Only operation legalization. Fixes PR42355 llvm-svn: 364093
2019-06-22 02:50:00 +08:00
; X86-AVX512F-NEXT: retl
;
; X64-AVX512F-LABEL: pr42355_v32i16:
; X64-AVX512F: # %bb.0:
; X64-AVX512F-NEXT: testb $1, %dil
[X86] Pass v32i16/v64i8 in zmm registers on KNL target. gcc and icc pass these types in zmm registers in zmm registers. This patch implements a quick hack to override the register type before calling convention handling to one that is legal. Longer term we might want to do something similar to 256-bit integer registers on AVX1 where we just split all the operations. Fixes PR42957 Differential Revision: https://reviews.llvm.org/D66708 llvm-svn: 370495
2019-08-31 01:35:08 +08:00
; X64-AVX512F-NEXT: jne .LBB14_1
; X64-AVX512F-NEXT: # %bb.2:
; X64-AVX512F-NEXT: vextractf64x4 $1, %zmm1, %ymm2
; X64-AVX512F-NEXT: vmovaps %ymm1, %ymm0
; X64-AVX512F-NEXT: vinsertf64x4 $1, %ymm2, %zmm0, %zmm0
; X64-AVX512F-NEXT: retq
; X64-AVX512F-NEXT: .LBB14_1:
; X64-AVX512F-NEXT: vextractf64x4 $1, %zmm0, %ymm2
; X64-AVX512F-NEXT: vinsertf64x4 $1, %ymm2, %zmm0, %zmm0
[X86] Don't mark v64i8/v32i16 ISD::SELECT as custom unless they are legal types. We don't have any Custom handling during type legalization. Only operation legalization. Fixes PR42355 llvm-svn: 364093
2019-06-22 02:50:00 +08:00
; X64-AVX512F-NEXT: retq
;
; X86-AVX512BW-LABEL: pr42355_v32i16:
; X86-AVX512BW: # %bb.0:
; X86-AVX512BW-NEXT: testb $1, {{[0-9]+}}(%esp)
; X86-AVX512BW-NEXT: jne .LBB14_2
; X86-AVX512BW-NEXT: # %bb.1:
; X86-AVX512BW-NEXT: vmovaps %zmm1, %zmm0
; X86-AVX512BW-NEXT: .LBB14_2:
; X86-AVX512BW-NEXT: retl
;
; X64-AVX512BW-LABEL: pr42355_v32i16:
; X64-AVX512BW: # %bb.0:
; X64-AVX512BW-NEXT: testb $1, %dil
; X64-AVX512BW-NEXT: jne .LBB14_2
; X64-AVX512BW-NEXT: # %bb.1:
; X64-AVX512BW-NEXT: vmovaps %zmm1, %zmm0
; X64-AVX512BW-NEXT: .LBB14_2:
; X64-AVX512BW-NEXT: retq
%a = select i1 %c, <32 x i16> %x, <32 x i16> %y
ret <32 x i16> %a
}
define <64 x i8> @pr42355_v64i8(i1 %c, <64 x i8> %x, <64 x i8> %y) {
; X86-AVX512F-LABEL: pr42355_v64i8:
; X86-AVX512F: # %bb.0:
[X86] Pass v32i16/v64i8 in zmm registers on KNL target. gcc and icc pass these types in zmm registers in zmm registers. This patch implements a quick hack to override the register type before calling convention handling to one that is legal. Longer term we might want to do something similar to 256-bit integer registers on AVX1 where we just split all the operations. Fixes PR42957 Differential Revision: https://reviews.llvm.org/D66708 llvm-svn: 370495
2019-08-31 01:35:08 +08:00
; X86-AVX512F-NEXT: testb $1, {{[0-9]+}}(%esp)
; X86-AVX512F-NEXT: jne .LBB15_1
; X86-AVX512F-NEXT: # %bb.2:
; X86-AVX512F-NEXT: vextractf64x4 $1, %zmm1, %ymm2
; X86-AVX512F-NEXT: vmovaps %ymm1, %ymm0
; X86-AVX512F-NEXT: vinsertf64x4 $1, %ymm2, %zmm0, %zmm0
; X86-AVX512F-NEXT: retl
; X86-AVX512F-NEXT: .LBB15_1:
; X86-AVX512F-NEXT: vextractf64x4 $1, %zmm0, %ymm2
; X86-AVX512F-NEXT: vinsertf64x4 $1, %ymm2, %zmm0, %zmm0
[X86] Don't mark v64i8/v32i16 ISD::SELECT as custom unless they are legal types. We don't have any Custom handling during type legalization. Only operation legalization. Fixes PR42355 llvm-svn: 364093
2019-06-22 02:50:00 +08:00
; X86-AVX512F-NEXT: retl
;
; X64-AVX512F-LABEL: pr42355_v64i8:
; X64-AVX512F: # %bb.0:
; X64-AVX512F-NEXT: testb $1, %dil
[X86] Pass v32i16/v64i8 in zmm registers on KNL target. gcc and icc pass these types in zmm registers in zmm registers. This patch implements a quick hack to override the register type before calling convention handling to one that is legal. Longer term we might want to do something similar to 256-bit integer registers on AVX1 where we just split all the operations. Fixes PR42957 Differential Revision: https://reviews.llvm.org/D66708 llvm-svn: 370495
2019-08-31 01:35:08 +08:00
; X64-AVX512F-NEXT: jne .LBB15_1
; X64-AVX512F-NEXT: # %bb.2:
; X64-AVX512F-NEXT: vextractf64x4 $1, %zmm1, %ymm2
; X64-AVX512F-NEXT: vmovaps %ymm1, %ymm0
; X64-AVX512F-NEXT: vinsertf64x4 $1, %ymm2, %zmm0, %zmm0
; X64-AVX512F-NEXT: retq
; X64-AVX512F-NEXT: .LBB15_1:
; X64-AVX512F-NEXT: vextractf64x4 $1, %zmm0, %ymm2
; X64-AVX512F-NEXT: vinsertf64x4 $1, %ymm2, %zmm0, %zmm0
[X86] Don't mark v64i8/v32i16 ISD::SELECT as custom unless they are legal types. We don't have any Custom handling during type legalization. Only operation legalization. Fixes PR42355 llvm-svn: 364093
2019-06-22 02:50:00 +08:00
; X64-AVX512F-NEXT: retq
;
; X86-AVX512BW-LABEL: pr42355_v64i8:
; X86-AVX512BW: # %bb.0:
; X86-AVX512BW-NEXT: testb $1, {{[0-9]+}}(%esp)
; X86-AVX512BW-NEXT: jne .LBB15_2
; X86-AVX512BW-NEXT: # %bb.1:
; X86-AVX512BW-NEXT: vmovaps %zmm1, %zmm0
; X86-AVX512BW-NEXT: .LBB15_2:
; X86-AVX512BW-NEXT: retl
;
; X64-AVX512BW-LABEL: pr42355_v64i8:
; X64-AVX512BW: # %bb.0:
; X64-AVX512BW-NEXT: testb $1, %dil
; X64-AVX512BW-NEXT: jne .LBB15_2
; X64-AVX512BW-NEXT: # %bb.1:
; X64-AVX512BW-NEXT: vmovaps %zmm1, %zmm0
; X64-AVX512BW-NEXT: .LBB15_2:
; X64-AVX512BW-NEXT: retq
%a = select i1 %c, <64 x i8> %x, <64 x i8> %y
ret <64 x i8> %a
}
[x86] remove whitespace; NFC llvm-svn: 364588
2019-06-28 04:37:12 +08:00
; This would crash because AVX512 has legal vector select
[x86] prevent crashing from select narrowing with AVX512 llvm-svn: 364585
2019-06-28 04:16:58 +08:00
; condition values that are not 256/512-bit vectors.
define <16 x i64> @narrowExtractedVectorSelect_crash(<16 x i64> %arg, <16 x i16> %arg1) #0 {
; X86-AVX512F-LABEL: narrowExtractedVectorSelect_crash:
; X86-AVX512F: # %bb.0:
; X86-AVX512F-NEXT: vptestmq %zmm0, %zmm0, %k0
; X86-AVX512F-NEXT: vptestmq %zmm1, %zmm1, %k1
; X86-AVX512F-NEXT: kunpckbw %k0, %k1, %k1
; X86-AVX512F-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; X86-AVX512F-NEXT: vpmovdw %zmm0, %ymm0
; X86-AVX512F-NEXT: vpand %ymm2, %ymm0, %ymm1
; X86-AVX512F-NEXT: vpmovzxwq {{.*#+}} zmm0 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero,xmm1[2],zero,zero,zero,xmm1[3],zero,zero,zero,xmm1[4],zero,zero,zero,xmm1[5],zero,zero,zero,xmm1[6],zero,zero,zero,xmm1[7],zero,zero,zero
; X86-AVX512F-NEXT: vextracti128 $1, %ymm1, %xmm1
; X86-AVX512F-NEXT: vpmovzxwq {{.*#+}} zmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero,xmm1[2],zero,zero,zero,xmm1[3],zero,zero,zero,xmm1[4],zero,zero,zero,xmm1[5],zero,zero,zero,xmm1[6],zero,zero,zero,xmm1[7],zero,zero,zero
; X86-AVX512F-NEXT: retl
;
; X64-AVX512F-LABEL: narrowExtractedVectorSelect_crash:
; X64-AVX512F: # %bb.0:
; X64-AVX512F-NEXT: vptestmq %zmm0, %zmm0, %k0
; X64-AVX512F-NEXT: vptestmq %zmm1, %zmm1, %k1
; X64-AVX512F-NEXT: kunpckbw %k0, %k1, %k1
; X64-AVX512F-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; X64-AVX512F-NEXT: vpmovdw %zmm0, %ymm0
; X64-AVX512F-NEXT: vpand %ymm2, %ymm0, %ymm1
; X64-AVX512F-NEXT: vpmovzxwq {{.*#+}} zmm0 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero,xmm1[2],zero,zero,zero,xmm1[3],zero,zero,zero,xmm1[4],zero,zero,zero,xmm1[5],zero,zero,zero,xmm1[6],zero,zero,zero,xmm1[7],zero,zero,zero
; X64-AVX512F-NEXT: vextracti128 $1, %ymm1, %xmm1
; X64-AVX512F-NEXT: vpmovzxwq {{.*#+}} zmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero,xmm1[2],zero,zero,zero,xmm1[3],zero,zero,zero,xmm1[4],zero,zero,zero,xmm1[5],zero,zero,zero,xmm1[6],zero,zero,zero,xmm1[7],zero,zero,zero
; X64-AVX512F-NEXT: retq
;
; X86-AVX512BW-LABEL: narrowExtractedVectorSelect_crash:
; X86-AVX512BW: # %bb.0:
; X86-AVX512BW-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2
; X86-AVX512BW-NEXT: vptestmq %zmm0, %zmm0, %k0
; X86-AVX512BW-NEXT: vptestmq %zmm1, %zmm1, %k1
; X86-AVX512BW-NEXT: kunpckbw %k0, %k1, %k1
; X86-AVX512BW-NEXT: vmovdqu16 %zmm2, %zmm1 {%k1} {z}
; X86-AVX512BW-NEXT: vpmovzxwq {{.*#+}} zmm0 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero,xmm1[2],zero,zero,zero,xmm1[3],zero,zero,zero,xmm1[4],zero,zero,zero,xmm1[5],zero,zero,zero,xmm1[6],zero,zero,zero,xmm1[7],zero,zero,zero
; X86-AVX512BW-NEXT: vextracti128 $1, %ymm1, %xmm1
; X86-AVX512BW-NEXT: vpmovzxwq {{.*#+}} zmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero,xmm1[2],zero,zero,zero,xmm1[3],zero,zero,zero,xmm1[4],zero,zero,zero,xmm1[5],zero,zero,zero,xmm1[6],zero,zero,zero,xmm1[7],zero,zero,zero
; X86-AVX512BW-NEXT: retl
;
; X64-AVX512BW-LABEL: narrowExtractedVectorSelect_crash:
; X64-AVX512BW: # %bb.0:
; X64-AVX512BW-NEXT: # kill: def $ymm2 killed $ymm2 def $zmm2
; X64-AVX512BW-NEXT: vptestmq %zmm0, %zmm0, %k0
; X64-AVX512BW-NEXT: vptestmq %zmm1, %zmm1, %k1
; X64-AVX512BW-NEXT: kunpckbw %k0, %k1, %k1
; X64-AVX512BW-NEXT: vmovdqu16 %zmm2, %zmm1 {%k1} {z}
; X64-AVX512BW-NEXT: vpmovzxwq {{.*#+}} zmm0 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero,xmm1[2],zero,zero,zero,xmm1[3],zero,zero,zero,xmm1[4],zero,zero,zero,xmm1[5],zero,zero,zero,xmm1[6],zero,zero,zero,xmm1[7],zero,zero,zero
; X64-AVX512BW-NEXT: vextracti128 $1, %ymm1, %xmm1
; X64-AVX512BW-NEXT: vpmovzxwq {{.*#+}} zmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero,xmm1[2],zero,zero,zero,xmm1[3],zero,zero,zero,xmm1[4],zero,zero,zero,xmm1[5],zero,zero,zero,xmm1[6],zero,zero,zero,xmm1[7],zero,zero,zero
; X64-AVX512BW-NEXT: retq
%tmp = icmp ne <16 x i64> %arg, zeroinitializer
%tmp2 = select <16 x i1> %tmp, <16 x i16> %arg1, <16 x i16> zeroinitializer
%tmp3 = zext <16 x i16> %tmp2 to <16 x i64>
ret <16 x i64> %tmp3
}
[X86] Expand vselect of v1i1 under avx512. We already do this for v2i1, v4i1, etc.
2020-02-21 05:46:56 +08:00
define void @vselect_v1i1(<1 x i1>* %w, <1 x i1>* %x, <1 x i1>* %y) nounwind {
; X86-AVX512F-LABEL: vselect_v1i1:
; X86-AVX512F: # %bb.0:
; X86-AVX512F-NEXT: pushl %esi
; X86-AVX512F-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-AVX512F-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-AVX512F-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-AVX512F-NEXT: movzbl (%edx), %esi
; X86-AVX512F-NEXT: kmovw %esi, %k0
; X86-AVX512F-NEXT: movzbl (%ecx), %ecx
; X86-AVX512F-NEXT: kmovw %ecx, %k1
; X86-AVX512F-NEXT: movzbl (%eax), %eax
; X86-AVX512F-NEXT: kmovw %eax, %k2
; X86-AVX512F-NEXT: kandw %k2, %k0, %k0
; X86-AVX512F-NEXT: kxnorw %k0, %k0, %k3
; X86-AVX512F-NEXT: kxorw %k3, %k2, %k2
; X86-AVX512F-NEXT: kandw %k2, %k1, %k1
; X86-AVX512F-NEXT: korw %k1, %k0, %k0
; X86-AVX512F-NEXT: kmovw %k0, %eax
; X86-AVX512F-NEXT: movb %al, (%edx)
; X86-AVX512F-NEXT: popl %esi
; X86-AVX512F-NEXT: retl
;
; X64-AVX512F-LABEL: vselect_v1i1:
; X64-AVX512F: # %bb.0:
; X64-AVX512F-NEXT: movzbl (%rsi), %eax
; X64-AVX512F-NEXT: kmovw %eax, %k0
; X64-AVX512F-NEXT: movzbl (%rdx), %eax
; X64-AVX512F-NEXT: kmovw %eax, %k1
; X64-AVX512F-NEXT: movzbl (%rdi), %eax
; X64-AVX512F-NEXT: kmovw %eax, %k2
; X64-AVX512F-NEXT: kandw %k2, %k0, %k0
; X64-AVX512F-NEXT: kxnorw %k0, %k0, %k3
; X64-AVX512F-NEXT: kxorw %k3, %k2, %k2
; X64-AVX512F-NEXT: kandw %k2, %k1, %k1
; X64-AVX512F-NEXT: korw %k1, %k0, %k0
; X64-AVX512F-NEXT: kmovw %k0, %eax
; X64-AVX512F-NEXT: movb %al, (%rsi)
; X64-AVX512F-NEXT: retq
;
; X86-AVX512BW-LABEL: vselect_v1i1:
; X86-AVX512BW: # %bb.0:
; X86-AVX512BW-NEXT: pushl %esi
; X86-AVX512BW-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-AVX512BW-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-AVX512BW-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-AVX512BW-NEXT: movzbl (%edx), %esi
; X86-AVX512BW-NEXT: kmovd %esi, %k0
; X86-AVX512BW-NEXT: movzbl (%ecx), %ecx
; X86-AVX512BW-NEXT: kmovd %ecx, %k1
; X86-AVX512BW-NEXT: movzbl (%eax), %eax
; X86-AVX512BW-NEXT: kmovd %eax, %k2
; X86-AVX512BW-NEXT: kandw %k2, %k0, %k0
; X86-AVX512BW-NEXT: kxnorw %k0, %k0, %k3
; X86-AVX512BW-NEXT: kxorw %k3, %k2, %k2
; X86-AVX512BW-NEXT: kandw %k2, %k1, %k1
; X86-AVX512BW-NEXT: korw %k1, %k0, %k0
; X86-AVX512BW-NEXT: kmovd %k0, %eax
; X86-AVX512BW-NEXT: movb %al, (%edx)
; X86-AVX512BW-NEXT: popl %esi
; X86-AVX512BW-NEXT: retl
;
; X64-AVX512BW-LABEL: vselect_v1i1:
; X64-AVX512BW: # %bb.0:
; X64-AVX512BW-NEXT: movzbl (%rsi), %eax
; X64-AVX512BW-NEXT: kmovd %eax, %k0
; X64-AVX512BW-NEXT: movzbl (%rdx), %eax
; X64-AVX512BW-NEXT: kmovd %eax, %k1
; X64-AVX512BW-NEXT: movzbl (%rdi), %eax
; X64-AVX512BW-NEXT: kmovd %eax, %k2
; X64-AVX512BW-NEXT: kandw %k2, %k0, %k0
; X64-AVX512BW-NEXT: kxnorw %k0, %k0, %k3
; X64-AVX512BW-NEXT: kxorw %k3, %k2, %k2
; X64-AVX512BW-NEXT: kandw %k2, %k1, %k1
; X64-AVX512BW-NEXT: korw %k1, %k0, %k0
; X64-AVX512BW-NEXT: kmovd %k0, %eax
; X64-AVX512BW-NEXT: movb %al, (%rsi)
; X64-AVX512BW-NEXT: retq
%a = load <1 x i1>, <1 x i1>* %x
%b = load <1 x i1>, <1 x i1>* %y
%b2 = load <1 x i1>, <1 x i1>* %w
%c = select <1 x i1> %b2, <1 x i1> %a, <1 x i1> %b
store <1 x i1> %c, <1 x i1>* %x
ret void
}
[X86] Add CMOV_VK1 pseudo so we don't crash on v1i1 ISD::SELECT
2020-02-21 06:00:17 +08:00
; Scalar condition with v1i1 operands
define void @select_v1i1(<1 x i1>* %w, <1 x i1>* %x, <1 x i1>* %y, i1 %z) nounwind {
; X86-AVX512F-LABEL: select_v1i1:
; X86-AVX512F: # %bb.0:
; X86-AVX512F-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-AVX512F-NEXT: testb $1, {{[0-9]+}}(%esp)
; X86-AVX512F-NEXT: jne .LBB18_1
; X86-AVX512F-NEXT: # %bb.2:
; X86-AVX512F-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-AVX512F-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-AVX512F-NEXT: movzbl (%edx), %edx
; X86-AVX512F-NEXT: kmovw %edx, %k0
; X86-AVX512F-NEXT: movzbl (%ecx), %ecx
; X86-AVX512F-NEXT: kmovw %ecx, %k1
; X86-AVX512F-NEXT: kxorw %k1, %k0, %k0
; X86-AVX512F-NEXT: jmp .LBB18_3
; X86-AVX512F-NEXT: .LBB18_1:
; X86-AVX512F-NEXT: movzbl (%eax), %ecx
; X86-AVX512F-NEXT: kmovw %ecx, %k0
; X86-AVX512F-NEXT: .LBB18_3:
; X86-AVX512F-NEXT: kmovw %k0, %ecx
; X86-AVX512F-NEXT: movb %cl, (%eax)
; X86-AVX512F-NEXT: retl
;
; X64-AVX512F-LABEL: select_v1i1:
; X64-AVX512F: # %bb.0:
; X64-AVX512F-NEXT: testb $1, %cl
; X64-AVX512F-NEXT: jne .LBB18_1
; X64-AVX512F-NEXT: # %bb.2:
; X64-AVX512F-NEXT: movzbl (%rdx), %eax
; X64-AVX512F-NEXT: kmovw %eax, %k0
; X64-AVX512F-NEXT: movzbl (%rdi), %eax
; X64-AVX512F-NEXT: kmovw %eax, %k1
; X64-AVX512F-NEXT: kxorw %k1, %k0, %k0
; X64-AVX512F-NEXT: jmp .LBB18_3
; X64-AVX512F-NEXT: .LBB18_1:
; X64-AVX512F-NEXT: movzbl (%rsi), %eax
; X64-AVX512F-NEXT: kmovw %eax, %k0
; X64-AVX512F-NEXT: .LBB18_3:
; X64-AVX512F-NEXT: kmovw %k0, %eax
; X64-AVX512F-NEXT: movb %al, (%rsi)
; X64-AVX512F-NEXT: retq
;
; X86-AVX512BW-LABEL: select_v1i1:
; X86-AVX512BW: # %bb.0:
; X86-AVX512BW-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-AVX512BW-NEXT: testb $1, {{[0-9]+}}(%esp)
; X86-AVX512BW-NEXT: jne .LBB18_1
; X86-AVX512BW-NEXT: # %bb.2:
; X86-AVX512BW-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X86-AVX512BW-NEXT: movl {{[0-9]+}}(%esp), %edx
; X86-AVX512BW-NEXT: movzbl (%edx), %edx
; X86-AVX512BW-NEXT: kmovd %edx, %k0
; X86-AVX512BW-NEXT: movzbl (%ecx), %ecx
; X86-AVX512BW-NEXT: kmovd %ecx, %k1
; X86-AVX512BW-NEXT: kxorw %k1, %k0, %k0
; X86-AVX512BW-NEXT: jmp .LBB18_3
; X86-AVX512BW-NEXT: .LBB18_1:
; X86-AVX512BW-NEXT: movzbl (%eax), %ecx
; X86-AVX512BW-NEXT: kmovd %ecx, %k0
; X86-AVX512BW-NEXT: .LBB18_3:
; X86-AVX512BW-NEXT: kmovd %k0, %ecx
; X86-AVX512BW-NEXT: movb %cl, (%eax)
; X86-AVX512BW-NEXT: retl
;
; X64-AVX512BW-LABEL: select_v1i1:
; X64-AVX512BW: # %bb.0:
; X64-AVX512BW-NEXT: testb $1, %cl
; X64-AVX512BW-NEXT: jne .LBB18_1
; X64-AVX512BW-NEXT: # %bb.2:
; X64-AVX512BW-NEXT: movzbl (%rdx), %eax
; X64-AVX512BW-NEXT: kmovd %eax, %k0
; X64-AVX512BW-NEXT: movzbl (%rdi), %eax
; X64-AVX512BW-NEXT: kmovd %eax, %k1
; X64-AVX512BW-NEXT: kxorw %k1, %k0, %k0
; X64-AVX512BW-NEXT: jmp .LBB18_3
; X64-AVX512BW-NEXT: .LBB18_1:
; X64-AVX512BW-NEXT: movzbl (%rsi), %eax
; X64-AVX512BW-NEXT: kmovd %eax, %k0
; X64-AVX512BW-NEXT: .LBB18_3:
; X64-AVX512BW-NEXT: kmovd %k0, %eax
; X64-AVX512BW-NEXT: movb %al, (%rsi)
; X64-AVX512BW-NEXT: retq
%a = load <1 x i1>, <1 x i1>* %x
%b = load <1 x i1>, <1 x i1>* %y
%b2 = load <1 x i1>, <1 x i1>* %w
%b3 = xor <1 x i1> %b, %b2
%c = select i1 %z, <1 x i1> %a, <1 x i1> %b3
store <1 x i1> %c, <1 x i1>* %x
ret void
}