2018-12-18 21:22:53 +08:00
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=SSE,SSE2
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+ssse3 | FileCheck %s --check-prefixes=SSE,SSSE3
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=SSE,SSE41
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=AVX,AVX1
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=AVX,AVX2
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw,+avx512vl,+fast-variable-shuffle | FileCheck %s --check-prefixes=AVX,AVX512
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declare <1 x i8> @llvm.uadd.sat.v1i8(<1 x i8>, <1 x i8>)
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declare <2 x i8> @llvm.uadd.sat.v2i8(<2 x i8>, <2 x i8>)
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declare <4 x i8> @llvm.uadd.sat.v4i8(<4 x i8>, <4 x i8>)
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declare <8 x i8> @llvm.uadd.sat.v8i8(<8 x i8>, <8 x i8>)
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declare <12 x i8> @llvm.uadd.sat.v12i8(<12 x i8>, <12 x i8>)
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declare <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8>, <16 x i8>)
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declare <32 x i8> @llvm.uadd.sat.v32i8(<32 x i8>, <32 x i8>)
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declare <64 x i8> @llvm.uadd.sat.v64i8(<64 x i8>, <64 x i8>)
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declare <1 x i16> @llvm.uadd.sat.v1i16(<1 x i16>, <1 x i16>)
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declare <2 x i16> @llvm.uadd.sat.v2i16(<2 x i16>, <2 x i16>)
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declare <4 x i16> @llvm.uadd.sat.v4i16(<4 x i16>, <4 x i16>)
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declare <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16>, <8 x i16>)
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declare <12 x i16> @llvm.uadd.sat.v12i16(<12 x i16>, <12 x i16>)
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declare <16 x i16> @llvm.uadd.sat.v16i16(<16 x i16>, <16 x i16>)
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declare <32 x i16> @llvm.uadd.sat.v32i16(<32 x i16>, <32 x i16>)
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declare <16 x i1> @llvm.uadd.sat.v16i1(<16 x i1>, <16 x i1>)
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declare <16 x i4> @llvm.uadd.sat.v16i4(<16 x i4>, <16 x i4>)
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declare <2 x i32> @llvm.uadd.sat.v2i32(<2 x i32>, <2 x i32>)
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2019-01-17 04:53:23 +08:00
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declare <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32>, <4 x i32>)
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declare <8 x i32> @llvm.uadd.sat.v8i32(<8 x i32>, <8 x i32>)
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declare <16 x i32> @llvm.uadd.sat.v16i32(<16 x i32>, <16 x i32>)
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declare <2 x i64> @llvm.uadd.sat.v2i64(<2 x i64>, <2 x i64>)
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declare <4 x i64> @llvm.uadd.sat.v4i64(<4 x i64>, <4 x i64>)
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declare <8 x i64> @llvm.uadd.sat.v8i64(<8 x i64>, <8 x i64>)
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2018-12-18 21:22:53 +08:00
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declare <4 x i24> @llvm.uadd.sat.v4i24(<4 x i24>, <4 x i24>)
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declare <2 x i128> @llvm.uadd.sat.v2i128(<2 x i128>, <2 x i128>)
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; Legal types, depending on architecture.
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define <16 x i8> @v16i8(<16 x i8> %x, <16 x i8> %y) nounwind {
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2018-12-18 21:23:03 +08:00
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; SSE-LABEL: v16i8:
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; SSE: # %bb.0:
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; SSE-NEXT: paddusb %xmm1, %xmm0
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; SSE-NEXT: retq
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2018-12-18 21:22:53 +08:00
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;
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; AVX-LABEL: v16i8:
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; AVX: # %bb.0:
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2018-12-18 21:23:03 +08:00
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; AVX-NEXT: vpaddusb %xmm1, %xmm0, %xmm0
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2018-12-18 21:22:53 +08:00
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; AVX-NEXT: retq
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%z = call <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8> %x, <16 x i8> %y)
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ret <16 x i8> %z
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}
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define <32 x i8> @v32i8(<32 x i8> %x, <32 x i8> %y) nounwind {
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2018-12-18 21:23:03 +08:00
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; SSE-LABEL: v32i8:
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; SSE: # %bb.0:
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; SSE-NEXT: paddusb %xmm2, %xmm0
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; SSE-NEXT: paddusb %xmm3, %xmm1
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; SSE-NEXT: retq
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2018-12-18 21:22:53 +08:00
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;
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; AVX1-LABEL: v32i8:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3
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2018-12-18 21:23:03 +08:00
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; AVX1-NEXT: vpaddusb %xmm2, %xmm3, %xmm2
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; AVX1-NEXT: vpaddusb %xmm1, %xmm0, %xmm0
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2018-12-18 21:22:53 +08:00
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; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: v32i8:
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; AVX2: # %bb.0:
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2018-12-18 21:23:03 +08:00
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; AVX2-NEXT: vpaddusb %ymm1, %ymm0, %ymm0
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2018-12-18 21:22:53 +08:00
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; AVX2-NEXT: retq
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;
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; AVX512-LABEL: v32i8:
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; AVX512: # %bb.0:
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2018-12-18 21:23:03 +08:00
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; AVX512-NEXT: vpaddusb %ymm1, %ymm0, %ymm0
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2018-12-18 21:22:53 +08:00
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; AVX512-NEXT: retq
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%z = call <32 x i8> @llvm.uadd.sat.v32i8(<32 x i8> %x, <32 x i8> %y)
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ret <32 x i8> %z
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}
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define <64 x i8> @v64i8(<64 x i8> %x, <64 x i8> %y) nounwind {
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2018-12-18 21:23:03 +08:00
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; SSE-LABEL: v64i8:
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; SSE: # %bb.0:
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; SSE-NEXT: paddusb %xmm4, %xmm0
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; SSE-NEXT: paddusb %xmm5, %xmm1
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; SSE-NEXT: paddusb %xmm6, %xmm2
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; SSE-NEXT: paddusb %xmm7, %xmm3
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; SSE-NEXT: retq
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2018-12-18 21:22:53 +08:00
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;
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; AVX1-LABEL: v64i8:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm4
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm5
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2018-12-18 21:23:03 +08:00
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; AVX1-NEXT: vpaddusb %xmm4, %xmm5, %xmm4
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; AVX1-NEXT: vpaddusb %xmm2, %xmm0, %xmm0
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; AVX1-NEXT: vinsertf128 $1, %xmm4, %ymm0, %ymm0
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; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm2
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; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm4
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; AVX1-NEXT: vpaddusb %xmm2, %xmm4, %xmm2
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; AVX1-NEXT: vpaddusb %xmm3, %xmm1, %xmm1
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2018-12-18 21:22:53 +08:00
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; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: v64i8:
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; AVX2: # %bb.0:
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2018-12-18 21:23:03 +08:00
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; AVX2-NEXT: vpaddusb %ymm2, %ymm0, %ymm0
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; AVX2-NEXT: vpaddusb %ymm3, %ymm1, %ymm1
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2018-12-18 21:22:53 +08:00
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; AVX2-NEXT: retq
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;
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; AVX512-LABEL: v64i8:
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; AVX512: # %bb.0:
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2018-12-18 21:23:03 +08:00
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; AVX512-NEXT: vpaddusb %zmm1, %zmm0, %zmm0
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2018-12-18 21:22:53 +08:00
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; AVX512-NEXT: retq
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%z = call <64 x i8> @llvm.uadd.sat.v64i8(<64 x i8> %x, <64 x i8> %y)
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ret <64 x i8> %z
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}
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define <8 x i16> @v8i16(<8 x i16> %x, <8 x i16> %y) nounwind {
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2018-12-18 21:23:03 +08:00
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; SSE-LABEL: v8i16:
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; SSE: # %bb.0:
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; SSE-NEXT: paddusw %xmm1, %xmm0
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; SSE-NEXT: retq
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2018-12-18 21:22:53 +08:00
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;
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; AVX-LABEL: v8i16:
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; AVX: # %bb.0:
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2018-12-18 21:23:03 +08:00
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; AVX-NEXT: vpaddusw %xmm1, %xmm0, %xmm0
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2018-12-18 21:22:53 +08:00
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; AVX-NEXT: retq
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%z = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> %x, <8 x i16> %y)
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ret <8 x i16> %z
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}
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define <16 x i16> @v16i16(<16 x i16> %x, <16 x i16> %y) nounwind {
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2018-12-18 21:23:03 +08:00
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; SSE-LABEL: v16i16:
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; SSE: # %bb.0:
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; SSE-NEXT: paddusw %xmm2, %xmm0
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; SSE-NEXT: paddusw %xmm3, %xmm1
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; SSE-NEXT: retq
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2018-12-18 21:22:53 +08:00
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;
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; AVX1-LABEL: v16i16:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3
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2018-12-18 21:23:03 +08:00
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; AVX1-NEXT: vpaddusw %xmm2, %xmm3, %xmm2
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; AVX1-NEXT: vpaddusw %xmm1, %xmm0, %xmm0
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2018-12-18 21:22:53 +08:00
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; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: v16i16:
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; AVX2: # %bb.0:
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2018-12-18 21:23:03 +08:00
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; AVX2-NEXT: vpaddusw %ymm1, %ymm0, %ymm0
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2018-12-18 21:22:53 +08:00
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; AVX2-NEXT: retq
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;
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; AVX512-LABEL: v16i16:
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; AVX512: # %bb.0:
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2018-12-18 21:23:03 +08:00
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; AVX512-NEXT: vpaddusw %ymm1, %ymm0, %ymm0
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2018-12-18 21:22:53 +08:00
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; AVX512-NEXT: retq
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%z = call <16 x i16> @llvm.uadd.sat.v16i16(<16 x i16> %x, <16 x i16> %y)
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ret <16 x i16> %z
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}
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define <32 x i16> @v32i16(<32 x i16> %x, <32 x i16> %y) nounwind {
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2018-12-18 21:23:03 +08:00
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; SSE-LABEL: v32i16:
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; SSE: # %bb.0:
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; SSE-NEXT: paddusw %xmm4, %xmm0
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; SSE-NEXT: paddusw %xmm5, %xmm1
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; SSE-NEXT: paddusw %xmm6, %xmm2
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; SSE-NEXT: paddusw %xmm7, %xmm3
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; SSE-NEXT: retq
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2018-12-18 21:22:53 +08:00
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;
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; AVX1-LABEL: v32i16:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm4
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm5
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2018-12-18 21:23:03 +08:00
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; AVX1-NEXT: vpaddusw %xmm4, %xmm5, %xmm4
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; AVX1-NEXT: vpaddusw %xmm2, %xmm0, %xmm0
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2018-12-18 21:22:53 +08:00
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; AVX1-NEXT: vinsertf128 $1, %xmm4, %ymm0, %ymm0
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; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm2
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; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm4
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2018-12-18 21:23:03 +08:00
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; AVX1-NEXT: vpaddusw %xmm2, %xmm4, %xmm2
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; AVX1-NEXT: vpaddusw %xmm3, %xmm1, %xmm1
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2018-12-18 21:22:53 +08:00
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; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: v32i16:
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; AVX2: # %bb.0:
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2018-12-18 21:23:03 +08:00
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; AVX2-NEXT: vpaddusw %ymm2, %ymm0, %ymm0
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; AVX2-NEXT: vpaddusw %ymm3, %ymm1, %ymm1
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2018-12-18 21:22:53 +08:00
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; AVX2-NEXT: retq
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;
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; AVX512-LABEL: v32i16:
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; AVX512: # %bb.0:
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2018-12-18 21:23:03 +08:00
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; AVX512-NEXT: vpaddusw %zmm1, %zmm0, %zmm0
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2018-12-18 21:22:53 +08:00
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; AVX512-NEXT: retq
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%z = call <32 x i16> @llvm.uadd.sat.v32i16(<32 x i16> %x, <32 x i16> %y)
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ret <32 x i16> %z
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}
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; Too narrow vectors, legalized by widening.
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define void @v8i8(<8 x i8>* %px, <8 x i8>* %py, <8 x i8>* %pz) nounwind {
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2018-12-18 21:23:03 +08:00
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; SSE-LABEL: v8i8:
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; SSE: # %bb.0:
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; SSE-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
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; SSE-NEXT: movq {{.*#+}} xmm1 = mem[0],zero
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; SSE-NEXT: paddusb %xmm0, %xmm1
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; SSE-NEXT: movq %xmm1, (%rdx)
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; SSE-NEXT: retq
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2018-12-18 21:22:53 +08:00
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;
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; AVX1-LABEL: v8i8:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero
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2018-12-18 21:23:03 +08:00
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; AVX1-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero
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; AVX1-NEXT: vpaddusb %xmm1, %xmm0, %xmm0
|
2018-12-18 21:22:53 +08:00
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|
; AVX1-NEXT: vmovq %xmm0, (%rdx)
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: v8i8:
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; AVX2: # %bb.0:
|
|
|
|
|
; AVX2-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero
|
2018-12-18 21:23:03 +08:00
|
|
|
; AVX2-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero
|
|
|
|
|
; AVX2-NEXT: vpaddusb %xmm1, %xmm0, %xmm0
|
2018-12-18 21:22:53 +08:00
|
|
|
; AVX2-NEXT: vmovq %xmm0, (%rdx)
|
|
|
|
|
; AVX2-NEXT: retq
|
|
|
|
|
;
|
|
|
|
|
; AVX512-LABEL: v8i8:
|
|
|
|
|
; AVX512: # %bb.0:
|
|
|
|
|
; AVX512-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero
|
2018-12-18 21:23:03 +08:00
|
|
|
; AVX512-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero
|
|
|
|
|
; AVX512-NEXT: vpaddusb %xmm1, %xmm0, %xmm0
|
|
|
|
|
; AVX512-NEXT: vpmovzxbw {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
|
2018-12-18 21:22:53 +08:00
|
|
|
; AVX512-NEXT: vpmovwb %xmm0, (%rdx)
|
|
|
|
|
; AVX512-NEXT: retq
|
|
|
|
|
%x = load <8 x i8>, <8 x i8>* %px
|
|
|
|
|
%y = load <8 x i8>, <8 x i8>* %py
|
|
|
|
|
%z = call <8 x i8> @llvm.uadd.sat.v8i8(<8 x i8> %x, <8 x i8> %y)
|
|
|
|
|
store <8 x i8> %z, <8 x i8>* %pz
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define void @v4i8(<4 x i8>* %px, <4 x i8>* %py, <4 x i8>* %pz) nounwind {
|
2018-12-18 21:23:03 +08:00
|
|
|
; SSE-LABEL: v4i8:
|
|
|
|
|
; SSE: # %bb.0:
|
|
|
|
|
; SSE-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
|
|
|
|
|
; SSE-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
|
|
|
|
|
; SSE-NEXT: paddusb %xmm0, %xmm1
|
|
|
|
|
; SSE-NEXT: movd %xmm1, (%rdx)
|
|
|
|
|
; SSE-NEXT: retq
|
2018-12-18 21:22:53 +08:00
|
|
|
;
|
|
|
|
|
; AVX1-LABEL: v4i8:
|
|
|
|
|
; AVX1: # %bb.0:
|
2018-12-18 21:23:03 +08:00
|
|
|
; AVX1-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
|
|
|
|
|
; AVX1-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero
|
|
|
|
|
; AVX1-NEXT: vpaddusb %xmm1, %xmm0, %xmm0
|
2018-12-18 21:22:53 +08:00
|
|
|
; AVX1-NEXT: vmovd %xmm0, (%rdx)
|
|
|
|
|
; AVX1-NEXT: retq
|
|
|
|
|
;
|
|
|
|
|
; AVX2-LABEL: v4i8:
|
|
|
|
|
; AVX2: # %bb.0:
|
2018-12-18 21:23:03 +08:00
|
|
|
; AVX2-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
|
|
|
|
|
; AVX2-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero
|
|
|
|
|
; AVX2-NEXT: vpaddusb %xmm1, %xmm0, %xmm0
|
2018-12-18 21:22:53 +08:00
|
|
|
; AVX2-NEXT: vmovd %xmm0, (%rdx)
|
|
|
|
|
; AVX2-NEXT: retq
|
|
|
|
|
;
|
|
|
|
|
; AVX512-LABEL: v4i8:
|
|
|
|
|
; AVX512: # %bb.0:
|
|
|
|
|
; AVX512-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
|
|
|
|
|
; AVX512-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero
|
2018-12-18 21:23:03 +08:00
|
|
|
; AVX512-NEXT: vpaddusb %xmm1, %xmm0, %xmm0
|
|
|
|
|
; AVX512-NEXT: vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
|
2018-12-18 21:22:53 +08:00
|
|
|
; AVX512-NEXT: vpmovdb %xmm0, (%rdx)
|
|
|
|
|
; AVX512-NEXT: retq
|
|
|
|
|
%x = load <4 x i8>, <4 x i8>* %px
|
|
|
|
|
%y = load <4 x i8>, <4 x i8>* %py
|
|
|
|
|
%z = call <4 x i8> @llvm.uadd.sat.v4i8(<4 x i8> %x, <4 x i8> %y)
|
|
|
|
|
store <4 x i8> %z, <4 x i8>* %pz
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define void @v2i8(<2 x i8>* %px, <2 x i8>* %py, <2 x i8>* %pz) nounwind {
|
|
|
|
|
; SSE2-LABEL: v2i8:
|
|
|
|
|
; SSE2: # %bb.0:
|
|
|
|
|
; SSE2-NEXT: movzwl (%rdi), %eax
|
|
|
|
|
; SSE2-NEXT: movd %eax, %xmm0
|
|
|
|
|
; SSE2-NEXT: movzwl (%rsi), %eax
|
|
|
|
|
; SSE2-NEXT: movd %eax, %xmm1
|
2018-12-18 21:23:03 +08:00
|
|
|
; SSE2-NEXT: paddusb %xmm0, %xmm1
|
|
|
|
|
; SSE2-NEXT: movd %xmm1, %eax
|
2018-12-18 21:22:53 +08:00
|
|
|
; SSE2-NEXT: movw %ax, (%rdx)
|
|
|
|
|
; SSE2-NEXT: retq
|
|
|
|
|
;
|
|
|
|
|
; SSSE3-LABEL: v2i8:
|
|
|
|
|
; SSSE3: # %bb.0:
|
|
|
|
|
; SSSE3-NEXT: movzwl (%rdi), %eax
|
|
|
|
|
; SSSE3-NEXT: movd %eax, %xmm0
|
|
|
|
|
; SSSE3-NEXT: movzwl (%rsi), %eax
|
|
|
|
|
; SSSE3-NEXT: movd %eax, %xmm1
|
2018-12-18 21:23:03 +08:00
|
|
|
; SSSE3-NEXT: paddusb %xmm0, %xmm1
|
|
|
|
|
; SSSE3-NEXT: movd %xmm1, %eax
|
2018-12-18 21:22:53 +08:00
|
|
|
; SSSE3-NEXT: movw %ax, (%rdx)
|
|
|
|
|
; SSSE3-NEXT: retq
|
|
|
|
|
;
|
|
|
|
|
; SSE41-LABEL: v2i8:
|
|
|
|
|
; SSE41: # %bb.0:
|
2018-12-18 21:23:03 +08:00
|
|
|
; SSE41-NEXT: movzwl (%rdi), %eax
|
|
|
|
|
; SSE41-NEXT: movd %eax, %xmm0
|
|
|
|
|
; SSE41-NEXT: movzwl (%rsi), %eax
|
|
|
|
|
; SSE41-NEXT: movd %eax, %xmm1
|
|
|
|
|
; SSE41-NEXT: paddusb %xmm0, %xmm1
|
|
|
|
|
; SSE41-NEXT: pextrw $0, %xmm1, (%rdx)
|
2018-12-18 21:22:53 +08:00
|
|
|
; SSE41-NEXT: retq
|
|
|
|
|
;
|
|
|
|
|
; AVX1-LABEL: v2i8:
|
|
|
|
|
; AVX1: # %bb.0:
|
2018-12-18 21:23:03 +08:00
|
|
|
; AVX1-NEXT: movzwl (%rdi), %eax
|
|
|
|
|
; AVX1-NEXT: vmovd %eax, %xmm0
|
|
|
|
|
; AVX1-NEXT: movzwl (%rsi), %eax
|
|
|
|
|
; AVX1-NEXT: vmovd %eax, %xmm1
|
|
|
|
|
; AVX1-NEXT: vpaddusb %xmm1, %xmm0, %xmm0
|
2018-12-18 21:22:53 +08:00
|
|
|
; AVX1-NEXT: vpextrw $0, %xmm0, (%rdx)
|
|
|
|
|
; AVX1-NEXT: retq
|
|
|
|
|
;
|
|
|
|
|
; AVX2-LABEL: v2i8:
|
|
|
|
|
; AVX2: # %bb.0:
|
2018-12-18 21:23:03 +08:00
|
|
|
; AVX2-NEXT: movzwl (%rdi), %eax
|
|
|
|
|
; AVX2-NEXT: vmovd %eax, %xmm0
|
|
|
|
|
; AVX2-NEXT: movzwl (%rsi), %eax
|
|
|
|
|
; AVX2-NEXT: vmovd %eax, %xmm1
|
|
|
|
|
; AVX2-NEXT: vpaddusb %xmm1, %xmm0, %xmm0
|
2018-12-18 21:22:53 +08:00
|
|
|
; AVX2-NEXT: vpextrw $0, %xmm0, (%rdx)
|
|
|
|
|
; AVX2-NEXT: retq
|
|
|
|
|
;
|
|
|
|
|
; AVX512-LABEL: v2i8:
|
|
|
|
|
; AVX512: # %bb.0:
|
|
|
|
|
; AVX512-NEXT: movzwl (%rdi), %eax
|
|
|
|
|
; AVX512-NEXT: vmovd %eax, %xmm0
|
|
|
|
|
; AVX512-NEXT: movzwl (%rsi), %eax
|
|
|
|
|
; AVX512-NEXT: vmovd %eax, %xmm1
|
2018-12-18 21:23:03 +08:00
|
|
|
; AVX512-NEXT: vpaddusb %xmm1, %xmm0, %xmm0
|
|
|
|
|
; AVX512-NEXT: vpmovzxbq {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,zero,zero,zero,zero,xmm0[1],zero,zero,zero,zero,zero,zero,zero
|
2018-12-18 21:22:53 +08:00
|
|
|
; AVX512-NEXT: vpmovqb %xmm0, (%rdx)
|
|
|
|
|
; AVX512-NEXT: retq
|
|
|
|
|
%x = load <2 x i8>, <2 x i8>* %px
|
|
|
|
|
%y = load <2 x i8>, <2 x i8>* %py
|
|
|
|
|
%z = call <2 x i8> @llvm.uadd.sat.v2i8(<2 x i8> %x, <2 x i8> %y)
|
|
|
|
|
store <2 x i8> %z, <2 x i8>* %pz
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define void @v4i16(<4 x i16>* %px, <4 x i16>* %py, <4 x i16>* %pz) nounwind {
|
2018-12-18 21:23:03 +08:00
|
|
|
; SSE-LABEL: v4i16:
|
|
|
|
|
; SSE: # %bb.0:
|
|
|
|
|
; SSE-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
|
|
|
|
|
; SSE-NEXT: movq {{.*#+}} xmm1 = mem[0],zero
|
|
|
|
|
; SSE-NEXT: paddusw %xmm0, %xmm1
|
|
|
|
|
; SSE-NEXT: movq %xmm1, (%rdx)
|
|
|
|
|
; SSE-NEXT: retq
|
2018-12-18 21:22:53 +08:00
|
|
|
;
|
|
|
|
|
; AVX1-LABEL: v4i16:
|
|
|
|
|
; AVX1: # %bb.0:
|
|
|
|
|
; AVX1-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero
|
|
|
|
|
; AVX1-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero
|
2018-12-18 21:23:03 +08:00
|
|
|
; AVX1-NEXT: vpaddusw %xmm1, %xmm0, %xmm0
|
2018-12-18 21:22:53 +08:00
|
|
|
; AVX1-NEXT: vmovq %xmm0, (%rdx)
|
|
|
|
|
; AVX1-NEXT: retq
|
|
|
|
|
;
|
|
|
|
|
; AVX2-LABEL: v4i16:
|
|
|
|
|
; AVX2: # %bb.0:
|
|
|
|
|
; AVX2-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero
|
|
|
|
|
; AVX2-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero
|
2018-12-18 21:23:03 +08:00
|
|
|
; AVX2-NEXT: vpaddusw %xmm1, %xmm0, %xmm0
|
2018-12-18 21:22:53 +08:00
|
|
|
; AVX2-NEXT: vmovq %xmm0, (%rdx)
|
|
|
|
|
; AVX2-NEXT: retq
|
|
|
|
|
;
|
|
|
|
|
; AVX512-LABEL: v4i16:
|
|
|
|
|
; AVX512: # %bb.0:
|
|
|
|
|
; AVX512-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero
|
|
|
|
|
; AVX512-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero
|
2018-12-18 21:23:03 +08:00
|
|
|
; AVX512-NEXT: vpaddusw %xmm1, %xmm0, %xmm0
|
|
|
|
|
; AVX512-NEXT: vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
|
2018-12-18 21:22:53 +08:00
|
|
|
; AVX512-NEXT: vpmovdw %xmm0, (%rdx)
|
|
|
|
|
; AVX512-NEXT: retq
|
|
|
|
|
%x = load <4 x i16>, <4 x i16>* %px
|
|
|
|
|
%y = load <4 x i16>, <4 x i16>* %py
|
|
|
|
|
%z = call <4 x i16> @llvm.uadd.sat.v4i16(<4 x i16> %x, <4 x i16> %y)
|
|
|
|
|
store <4 x i16> %z, <4 x i16>* %pz
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define void @v2i16(<2 x i16>* %px, <2 x i16>* %py, <2 x i16>* %pz) nounwind {
|
2018-12-18 21:23:03 +08:00
|
|
|
; SSE-LABEL: v2i16:
|
|
|
|
|
; SSE: # %bb.0:
|
|
|
|
|
; SSE-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
|
|
|
|
|
; SSE-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
|
|
|
|
|
; SSE-NEXT: paddusw %xmm0, %xmm1
|
|
|
|
|
; SSE-NEXT: movd %xmm1, (%rdx)
|
|
|
|
|
; SSE-NEXT: retq
|
2018-12-18 21:22:53 +08:00
|
|
|
;
|
|
|
|
|
; AVX1-LABEL: v2i16:
|
|
|
|
|
; AVX1: # %bb.0:
|
2018-12-18 21:23:03 +08:00
|
|
|
; AVX1-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
|
|
|
|
|
; AVX1-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero
|
|
|
|
|
; AVX1-NEXT: vpaddusw %xmm1, %xmm0, %xmm0
|
2018-12-18 21:22:53 +08:00
|
|
|
; AVX1-NEXT: vmovd %xmm0, (%rdx)
|
|
|
|
|
; AVX1-NEXT: retq
|
|
|
|
|
;
|
|
|
|
|
; AVX2-LABEL: v2i16:
|
|
|
|
|
; AVX2: # %bb.0:
|
2018-12-18 21:23:03 +08:00
|
|
|
; AVX2-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
|
|
|
|
|
; AVX2-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero
|
|
|
|
|
; AVX2-NEXT: vpaddusw %xmm1, %xmm0, %xmm0
|
2018-12-18 21:22:53 +08:00
|
|
|
; AVX2-NEXT: vmovd %xmm0, (%rdx)
|
|
|
|
|
; AVX2-NEXT: retq
|
|
|
|
|
;
|
|
|
|
|
; AVX512-LABEL: v2i16:
|
|
|
|
|
; AVX512: # %bb.0:
|
|
|
|
|
; AVX512-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
|
|
|
|
|
; AVX512-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero
|
2018-12-18 21:23:03 +08:00
|
|
|
; AVX512-NEXT: vpaddusw %xmm1, %xmm0, %xmm0
|
|
|
|
|
; AVX512-NEXT: vpmovzxwq {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero
|
2018-12-18 21:22:53 +08:00
|
|
|
; AVX512-NEXT: vpmovqw %xmm0, (%rdx)
|
|
|
|
|
; AVX512-NEXT: retq
|
|
|
|
|
%x = load <2 x i16>, <2 x i16>* %px
|
|
|
|
|
%y = load <2 x i16>, <2 x i16>* %py
|
|
|
|
|
%z = call <2 x i16> @llvm.uadd.sat.v2i16(<2 x i16> %x, <2 x i16> %y)
|
|
|
|
|
store <2 x i16> %z, <2 x i16>* %pz
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define <12 x i8> @v12i8(<12 x i8> %x, <12 x i8> %y) nounwind {
|
2018-12-18 21:23:03 +08:00
|
|
|
; SSE-LABEL: v12i8:
|
|
|
|
|
; SSE: # %bb.0:
|
|
|
|
|
; SSE-NEXT: paddusb %xmm1, %xmm0
|
|
|
|
|
; SSE-NEXT: retq
|
2018-12-18 21:22:53 +08:00
|
|
|
;
|
|
|
|
|
; AVX-LABEL: v12i8:
|
|
|
|
|
; AVX: # %bb.0:
|
2018-12-18 21:23:03 +08:00
|
|
|
; AVX-NEXT: vpaddusb %xmm1, %xmm0, %xmm0
|
2018-12-18 21:22:53 +08:00
|
|
|
; AVX-NEXT: retq
|
|
|
|
|
%z = call <12 x i8> @llvm.uadd.sat.v12i8(<12 x i8> %x, <12 x i8> %y)
|
|
|
|
|
ret <12 x i8> %z
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define void @v12i16(<12 x i16>* %px, <12 x i16>* %py, <12 x i16>* %pz) nounwind {
|
2018-12-18 21:23:03 +08:00
|
|
|
; SSE-LABEL: v12i16:
|
|
|
|
|
; SSE: # %bb.0:
|
|
|
|
|
; SSE-NEXT: movdqa (%rdi), %xmm0
|
|
|
|
|
; SSE-NEXT: movdqa 16(%rdi), %xmm1
|
|
|
|
|
; SSE-NEXT: paddusw (%rsi), %xmm0
|
|
|
|
|
; SSE-NEXT: paddusw 16(%rsi), %xmm1
|
|
|
|
|
; SSE-NEXT: movq %xmm1, 16(%rdx)
|
|
|
|
|
; SSE-NEXT: movdqa %xmm0, (%rdx)
|
|
|
|
|
; SSE-NEXT: retq
|
2018-12-18 21:22:53 +08:00
|
|
|
;
|
2018-12-18 21:23:03 +08:00
|
|
|
; AVX1-LABEL: v12i16:
|
|
|
|
|
; AVX1: # %bb.0:
|
|
|
|
|
; AVX1-NEXT: vmovdqa (%rdi), %xmm0
|
|
|
|
|
; AVX1-NEXT: vmovdqa 16(%rdi), %xmm1
|
|
|
|
|
; AVX1-NEXT: vpaddusw 16(%rsi), %xmm1, %xmm1
|
[DAGCombiner] If a TokenFactor would be merged into its user, consider the user later.
Summary:
A number of optimizations are inhibited by single-use TokenFactors not
being merged into the TokenFactor using it. This makes we consider if
we can do the merge immediately.
Most tests changes here are due to the change in visitation causing
minor reorderings and associated reassociation of paired memory
operations.
CodeGen tests with non-reordering changes:
X86/aligned-variadic.ll -- memory-based add folded into stored leaq
value.
X86/constant-combiners.ll -- Optimizes out overlap between stores.
X86/pr40631_deadstore_elision -- folds constant byte store into
preceding quad word constant store.
Reviewers: RKSimon, craig.topper, spatel, efriedma, courbet
Reviewed By: courbet
Subscribers: dylanmckay, sdardis, nemanjai, jvesely, nhaehnle, javed.absar, eraman, hiraditya, kbarton, jrtc27, atanasyan, jsji, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D59260
llvm-svn: 356068
2019-03-14 01:07:09 +08:00
|
|
|
; AVX1-NEXT: vpaddusw (%rsi), %xmm0, %xmm0
|
2018-12-18 21:23:03 +08:00
|
|
|
; AVX1-NEXT: vmovdqa %xmm0, (%rdx)
|
[DAGCombiner] If a TokenFactor would be merged into its user, consider the user later.
Summary:
A number of optimizations are inhibited by single-use TokenFactors not
being merged into the TokenFactor using it. This makes we consider if
we can do the merge immediately.
Most tests changes here are due to the change in visitation causing
minor reorderings and associated reassociation of paired memory
operations.
CodeGen tests with non-reordering changes:
X86/aligned-variadic.ll -- memory-based add folded into stored leaq
value.
X86/constant-combiners.ll -- Optimizes out overlap between stores.
X86/pr40631_deadstore_elision -- folds constant byte store into
preceding quad word constant store.
Reviewers: RKSimon, craig.topper, spatel, efriedma, courbet
Reviewed By: courbet
Subscribers: dylanmckay, sdardis, nemanjai, jvesely, nhaehnle, javed.absar, eraman, hiraditya, kbarton, jrtc27, atanasyan, jsji, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D59260
llvm-svn: 356068
2019-03-14 01:07:09 +08:00
|
|
|
; AVX1-NEXT: vmovq %xmm1, 16(%rdx)
|
2018-12-18 21:23:03 +08:00
|
|
|
; AVX1-NEXT: retq
|
2018-12-18 21:22:53 +08:00
|
|
|
;
|
2018-12-18 21:23:03 +08:00
|
|
|
; AVX2-LABEL: v12i16:
|
|
|
|
|
; AVX2: # %bb.0:
|
|
|
|
|
; AVX2-NEXT: vmovdqa (%rdi), %ymm0
|
|
|
|
|
; AVX2-NEXT: vpaddusw (%rsi), %ymm0, %ymm0
|
|
|
|
|
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
|
|
|
|
|
; AVX2-NEXT: vmovq %xmm1, 16(%rdx)
|
|
|
|
|
; AVX2-NEXT: vmovdqa %xmm0, (%rdx)
|
|
|
|
|
; AVX2-NEXT: vzeroupper
|
|
|
|
|
; AVX2-NEXT: retq
|
2018-12-18 21:22:53 +08:00
|
|
|
;
|
2018-12-18 21:23:03 +08:00
|
|
|
; AVX512-LABEL: v12i16:
|
|
|
|
|
; AVX512: # %bb.0:
|
|
|
|
|
; AVX512-NEXT: vmovdqa (%rdi), %ymm0
|
|
|
|
|
; AVX512-NEXT: vpaddusw (%rsi), %ymm0, %ymm0
|
|
|
|
|
; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm1
|
|
|
|
|
; AVX512-NEXT: vmovq %xmm1, 16(%rdx)
|
|
|
|
|
; AVX512-NEXT: vmovdqa %xmm0, (%rdx)
|
|
|
|
|
; AVX512-NEXT: vzeroupper
|
|
|
|
|
; AVX512-NEXT: retq
|
2018-12-18 21:22:53 +08:00
|
|
|
%x = load <12 x i16>, <12 x i16>* %px
|
|
|
|
|
%y = load <12 x i16>, <12 x i16>* %py
|
|
|
|
|
%z = call <12 x i16> @llvm.uadd.sat.v12i16(<12 x i16> %x, <12 x i16> %y)
|
|
|
|
|
store <12 x i16> %z, <12 x i16>* %pz
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; Scalarization
|
|
|
|
|
|
|
|
|
|
define void @v1i8(<1 x i8>* %px, <1 x i8>* %py, <1 x i8>* %pz) nounwind {
|
|
|
|
|
; SSE-LABEL: v1i8:
|
|
|
|
|
; SSE: # %bb.0:
|
|
|
|
|
; SSE-NEXT: movb (%rdi), %al
|
|
|
|
|
; SSE-NEXT: addb (%rsi), %al
|
[X86] Promote i8 CMOV's (PR40965)
Summary:
@mclow.lists brought up this issue up in IRC, it came up during
implementation of libc++ `std::midpoint()` implementation (D59099)
https://godbolt.org/z/oLrHBP
Currently LLVM X86 backend only promotes i8 CMOV if it came from 2x`trunc`.
This differential proposes to always promote i8 CMOV.
There are several concerns here:
* Is this actually more performant, or is it just the ASM that looks cuter?
* Does this result in partial register stalls?
* What about branch predictor?
# Indeed, performance should be the main point here.
Let's look at a simple microbenchmark: {F8412076}
```
#include "benchmark/benchmark.h"
#include <algorithm>
#include <cmath>
#include <cstdint>
#include <iterator>
#include <limits>
#include <random>
#include <type_traits>
#include <utility>
#include <vector>
// Future preliminary libc++ code, from Marshall Clow.
namespace std {
template <class _Tp>
__inline _Tp midpoint(_Tp __a, _Tp __b) noexcept {
using _Up = typename std::make_unsigned<typename remove_cv<_Tp>::type>::type;
int __sign = 1;
_Up __m = __a;
_Up __M = __b;
if (__a > __b) {
__sign = -1;
__m = __b;
__M = __a;
}
return __a + __sign * _Tp(_Up(__M - __m) >> 1);
}
} // namespace std
template <typename T>
std::vector<T> getVectorOfRandomNumbers(size_t count) {
std::random_device rd;
std::mt19937 gen(rd());
std::uniform_int_distribution<T> dis(std::numeric_limits<T>::min(),
std::numeric_limits<T>::max());
std::vector<T> v;
v.reserve(count);
std::generate_n(std::back_inserter(v), count,
[&dis, &gen]() { return dis(gen); });
assert(v.size() == count);
return v;
}
struct RandRand {
template <typename T>
static std::pair<std::vector<T>, std::vector<T>> Gen(size_t count) {
return std::make_pair(getVectorOfRandomNumbers<T>(count),
getVectorOfRandomNumbers<T>(count));
}
};
struct ZeroRand {
template <typename T>
static std::pair<std::vector<T>, std::vector<T>> Gen(size_t count) {
return std::make_pair(std::vector<T>(count, T(0)),
getVectorOfRandomNumbers<T>(count));
}
};
template <class T, class Gen>
void BM_StdMidpoint(benchmark::State& state) {
const size_t Length = state.range(0);
const std::pair<std::vector<T>, std::vector<T>> Data =
Gen::template Gen<T>(Length);
const std::vector<T>& a = Data.first;
const std::vector<T>& b = Data.second;
assert(a.size() == Length && b.size() == a.size());
benchmark::ClobberMemory();
benchmark::DoNotOptimize(a);
benchmark::DoNotOptimize(a.data());
benchmark::DoNotOptimize(b);
benchmark::DoNotOptimize(b.data());
for (auto _ : state) {
for (size_t i = 0; i < Length; i++) {
const auto calculated = std::midpoint(a[i], b[i]);
benchmark::DoNotOptimize(calculated);
}
}
state.SetComplexityN(Length);
state.counters["midpoints"] =
benchmark::Counter(Length, benchmark::Counter::kIsIterationInvariant);
state.counters["midpoints/sec"] =
benchmark::Counter(Length, benchmark::Counter::kIsIterationInvariantRate);
const size_t BytesRead = 2 * sizeof(T) * Length;
state.counters["bytes_read/iteration"] =
benchmark::Counter(BytesRead, benchmark::Counter::kDefaults,
benchmark::Counter::OneK::kIs1024);
state.counters["bytes_read/sec"] = benchmark::Counter(
BytesRead, benchmark::Counter::kIsIterationInvariantRate,
benchmark::Counter::OneK::kIs1024);
}
template <typename T>
static void CustomArguments(benchmark::internal::Benchmark* b) {
const size_t L2SizeBytes = 2 * 1024 * 1024;
// What is the largest range we can check to always fit within given L2 cache?
const size_t MaxLen = L2SizeBytes / /*total bufs*/ 2 /
/*maximal elt size*/ sizeof(T) / /*safety margin*/ 2;
b->RangeMultiplier(2)->Range(1, MaxLen)->Complexity(benchmark::oN);
}
// Both of the values are random.
// The comparison is unpredictable.
BENCHMARK_TEMPLATE(BM_StdMidpoint, int32_t, RandRand)
->Apply(CustomArguments<int32_t>);
BENCHMARK_TEMPLATE(BM_StdMidpoint, uint32_t, RandRand)
->Apply(CustomArguments<uint32_t>);
BENCHMARK_TEMPLATE(BM_StdMidpoint, int64_t, RandRand)
->Apply(CustomArguments<int64_t>);
BENCHMARK_TEMPLATE(BM_StdMidpoint, uint64_t, RandRand)
->Apply(CustomArguments<uint64_t>);
BENCHMARK_TEMPLATE(BM_StdMidpoint, int16_t, RandRand)
->Apply(CustomArguments<int16_t>);
BENCHMARK_TEMPLATE(BM_StdMidpoint, uint16_t, RandRand)
->Apply(CustomArguments<uint16_t>);
BENCHMARK_TEMPLATE(BM_StdMidpoint, int8_t, RandRand)
->Apply(CustomArguments<int8_t>);
BENCHMARK_TEMPLATE(BM_StdMidpoint, uint8_t, RandRand)
->Apply(CustomArguments<uint8_t>);
// One value is always zero, and another is bigger or equal than zero.
// The comparison is predictable.
BENCHMARK_TEMPLATE(BM_StdMidpoint, uint32_t, ZeroRand)
->Apply(CustomArguments<uint32_t>);
BENCHMARK_TEMPLATE(BM_StdMidpoint, uint64_t, ZeroRand)
->Apply(CustomArguments<uint64_t>);
BENCHMARK_TEMPLATE(BM_StdMidpoint, uint16_t, ZeroRand)
->Apply(CustomArguments<uint16_t>);
BENCHMARK_TEMPLATE(BM_StdMidpoint, uint8_t, ZeroRand)
->Apply(CustomArguments<uint8_t>);
```
```
$ ~/src/googlebenchmark/tools/compare.py --no-utest benchmarks ./llvm-cmov-bench-OLD ./llvm-cmov-bench-NEW
RUNNING: ./llvm-cmov-bench-OLD --benchmark_out=/tmp/tmp5a5qjm
2019-03-06 21:53:31
Running ./llvm-cmov-bench-OLD
Run on (8 X 4000 MHz CPU s)
CPU Caches:
L1 Data 16K (x8)
L1 Instruction 64K (x4)
L2 Unified 2048K (x4)
L3 Unified 8192K (x1)
Load Average: 1.78, 1.81, 1.36
----------------------------------------------------------------------------------------------------
Benchmark Time CPU Iterations UserCounters<...>
----------------------------------------------------------------------------------------------------
<...>
BM_StdMidpoint<int32_t, RandRand>/131072 300398 ns 300404 ns 2330 bytes_read/iteration=1024k bytes_read/sec=3.25083G/s midpoints=305.398M midpoints/sec=436.319M/s
BM_StdMidpoint<int32_t, RandRand>_BigO 2.29 N 2.29 N
BM_StdMidpoint<int32_t, RandRand>_RMS 2 % 2 %
<...>
BM_StdMidpoint<uint32_t, RandRand>/131072 300433 ns 300433 ns 2330 bytes_read/iteration=1024k bytes_read/sec=3.25052G/s midpoints=305.398M midpoints/sec=436.278M/s
BM_StdMidpoint<uint32_t, RandRand>_BigO 2.29 N 2.29 N
BM_StdMidpoint<uint32_t, RandRand>_RMS 2 % 2 %
<...>
BM_StdMidpoint<int64_t, RandRand>/65536 169857 ns 169858 ns 4121 bytes_read/iteration=1024k bytes_read/sec=5.74929G/s midpoints=270.074M midpoints/sec=385.828M/s
BM_StdMidpoint<int64_t, RandRand>_BigO 2.59 N 2.59 N
BM_StdMidpoint<int64_t, RandRand>_RMS 3 % 3 %
<...>
BM_StdMidpoint<uint64_t, RandRand>/65536 169770 ns 169771 ns 4125 bytes_read/iteration=1024k bytes_read/sec=5.75223G/s midpoints=270.336M midpoints/sec=386.026M/s
BM_StdMidpoint<uint64_t, RandRand>_BigO 2.59 N 2.59 N
BM_StdMidpoint<uint64_t, RandRand>_RMS 3 % 3 %
<...>
BM_StdMidpoint<int16_t, RandRand>/262144 591169 ns 591179 ns 1182 bytes_read/iteration=1024k bytes_read/sec=1.65189G/s midpoints=309.854M midpoints/sec=443.426M/s
BM_StdMidpoint<int16_t, RandRand>_BigO 2.25 N 2.25 N
BM_StdMidpoint<int16_t, RandRand>_RMS 1 % 1 %
<...>
BM_StdMidpoint<uint16_t, RandRand>/262144 591264 ns 591274 ns 1184 bytes_read/iteration=1024k bytes_read/sec=1.65162G/s midpoints=310.378M midpoints/sec=443.354M/s
BM_StdMidpoint<uint16_t, RandRand>_BigO 2.25 N 2.25 N
BM_StdMidpoint<uint16_t, RandRand>_RMS 1 % 1 %
<...>
BM_StdMidpoint<int8_t, RandRand>/524288 2983669 ns 2983689 ns 235 bytes_read/iteration=1024k bytes_read/sec=335.156M/s midpoints=123.208M midpoints/sec=175.718M/s
BM_StdMidpoint<int8_t, RandRand>_BigO 5.69 N 5.69 N
BM_StdMidpoint<int8_t, RandRand>_RMS 0 % 0 %
<...>
BM_StdMidpoint<uint8_t, RandRand>/524288 2668398 ns 2668419 ns 262 bytes_read/iteration=1024k bytes_read/sec=374.754M/s midpoints=137.363M midpoints/sec=196.479M/s
BM_StdMidpoint<uint8_t, RandRand>_BigO 5.09 N 5.09 N
BM_StdMidpoint<uint8_t, RandRand>_RMS 0 % 0 %
<...>
BM_StdMidpoint<uint32_t, ZeroRand>/131072 300887 ns 300887 ns 2331 bytes_read/iteration=1024k bytes_read/sec=3.24561G/s midpoints=305.529M midpoints/sec=435.619M/s
BM_StdMidpoint<uint32_t, ZeroRand>_BigO 2.29 N 2.29 N
BM_StdMidpoint<uint32_t, ZeroRand>_RMS 2 % 2 %
<...>
BM_StdMidpoint<uint64_t, ZeroRand>/65536 169634 ns 169634 ns 4102 bytes_read/iteration=1024k bytes_read/sec=5.75688G/s midpoints=268.829M midpoints/sec=386.338M/s
BM_StdMidpoint<uint64_t, ZeroRand>_BigO 2.59 N 2.59 N
BM_StdMidpoint<uint64_t, ZeroRand>_RMS 3 % 3 %
<...>
BM_StdMidpoint<uint16_t, ZeroRand>/262144 592252 ns 592255 ns 1182 bytes_read/iteration=1024k bytes_read/sec=1.64889G/s midpoints=309.854M midpoints/sec=442.62M/s
BM_StdMidpoint<uint16_t, ZeroRand>_BigO 2.26 N 2.26 N
BM_StdMidpoint<uint16_t, ZeroRand>_RMS 1 % 1 %
<...>
BM_StdMidpoint<uint8_t, ZeroRand>/524288 987295 ns 987309 ns 711 bytes_read/iteration=1024k bytes_read/sec=1012.85M/s midpoints=372.769M midpoints/sec=531.028M/s
BM_StdMidpoint<uint8_t, ZeroRand>_BigO 1.88 N 1.88 N
BM_StdMidpoint<uint8_t, ZeroRand>_RMS 1 % 1 %
RUNNING: ./llvm-cmov-bench-NEW --benchmark_out=/tmp/tmpPvwpfW
2019-03-06 21:56:58
Running ./llvm-cmov-bench-NEW
Run on (8 X 4000 MHz CPU s)
CPU Caches:
L1 Data 16K (x8)
L1 Instruction 64K (x4)
L2 Unified 2048K (x4)
L3 Unified 8192K (x1)
Load Average: 1.17, 1.46, 1.30
----------------------------------------------------------------------------------------------------
Benchmark Time CPU Iterations UserCounters<...>
----------------------------------------------------------------------------------------------------
<...>
BM_StdMidpoint<int32_t, RandRand>/131072 300878 ns 300880 ns 2324 bytes_read/iteration=1024k bytes_read/sec=3.24569G/s midpoints=304.611M midpoints/sec=435.629M/s
BM_StdMidpoint<int32_t, RandRand>_BigO 2.29 N 2.29 N
BM_StdMidpoint<int32_t, RandRand>_RMS 2 % 2 %
<...>
BM_StdMidpoint<uint32_t, RandRand>/131072 300231 ns 300226 ns 2330 bytes_read/iteration=1024k bytes_read/sec=3.25276G/s midpoints=305.398M midpoints/sec=436.578M/s
BM_StdMidpoint<uint32_t, RandRand>_BigO 2.29 N 2.29 N
BM_StdMidpoint<uint32_t, RandRand>_RMS 2 % 2 %
<...>
BM_StdMidpoint<int64_t, RandRand>/65536 170819 ns 170777 ns 4115 bytes_read/iteration=1024k bytes_read/sec=5.71835G/s midpoints=269.681M midpoints/sec=383.752M/s
BM_StdMidpoint<int64_t, RandRand>_BigO 2.60 N 2.60 N
BM_StdMidpoint<int64_t, RandRand>_RMS 3 % 3 %
<...>
BM_StdMidpoint<uint64_t, RandRand>/65536 171705 ns 171708 ns 4106 bytes_read/iteration=1024k bytes_read/sec=5.68733G/s midpoints=269.091M midpoints/sec=381.671M/s
BM_StdMidpoint<uint64_t, RandRand>_BigO 2.62 N 2.62 N
BM_StdMidpoint<uint64_t, RandRand>_RMS 3 % 3 %
<...>
BM_StdMidpoint<int16_t, RandRand>/262144 592510 ns 592516 ns 1182 bytes_read/iteration=1024k bytes_read/sec=1.64816G/s midpoints=309.854M midpoints/sec=442.425M/s
BM_StdMidpoint<int16_t, RandRand>_BigO 2.26 N 2.26 N
BM_StdMidpoint<int16_t, RandRand>_RMS 1 % 1 %
<...>
BM_StdMidpoint<uint16_t, RandRand>/262144 614823 ns 614823 ns 1180 bytes_read/iteration=1024k bytes_read/sec=1.58836G/s midpoints=309.33M midpoints/sec=426.373M/s
BM_StdMidpoint<uint16_t, RandRand>_BigO 2.33 N 2.33 N
BM_StdMidpoint<uint16_t, RandRand>_RMS 4 % 4 %
<...>
BM_StdMidpoint<int8_t, RandRand>/524288 1073181 ns 1073201 ns 650 bytes_read/iteration=1024k bytes_read/sec=931.791M/s midpoints=340.787M midpoints/sec=488.527M/s
BM_StdMidpoint<int8_t, RandRand>_BigO 2.05 N 2.05 N
BM_StdMidpoint<int8_t, RandRand>_RMS 1 % 1 %
BM_StdMidpoint<uint8_t, RandRand>/524288 1071010 ns 1071020 ns 653 bytes_read/iteration=1024k bytes_read/sec=933.689M/s midpoints=342.36M midpoints/sec=489.522M/s
BM_StdMidpoint<uint8_t, RandRand>_BigO 2.05 N 2.05 N
BM_StdMidpoint<uint8_t, RandRand>_RMS 1 % 1 %
<...>
BM_StdMidpoint<uint32_t, ZeroRand>/131072 300413 ns 300416 ns 2330 bytes_read/iteration=1024k bytes_read/sec=3.2507G/s midpoints=305.398M midpoints/sec=436.302M/s
BM_StdMidpoint<uint32_t, ZeroRand>_BigO 2.29 N 2.29 N
BM_StdMidpoint<uint32_t, ZeroRand>_RMS 2 % 2 %
<...>
BM_StdMidpoint<uint64_t, ZeroRand>/65536 169667 ns 169669 ns 4123 bytes_read/iteration=1024k bytes_read/sec=5.75568G/s midpoints=270.205M midpoints/sec=386.257M/s
BM_StdMidpoint<uint64_t, ZeroRand>_BigO 2.59 N 2.59 N
BM_StdMidpoint<uint64_t, ZeroRand>_RMS 3 % 3 %
<...>
BM_StdMidpoint<uint16_t, ZeroRand>/262144 591396 ns 591404 ns 1184 bytes_read/iteration=1024k bytes_read/sec=1.65126G/s midpoints=310.378M midpoints/sec=443.257M/s
BM_StdMidpoint<uint16_t, ZeroRand>_BigO 2.26 N 2.26 N
BM_StdMidpoint<uint16_t, ZeroRand>_RMS 1 % 1 %
<...>
BM_StdMidpoint<uint8_t, ZeroRand>/524288 1069421 ns 1069413 ns 655 bytes_read/iteration=1024k bytes_read/sec=935.092M/s midpoints=343.409M midpoints/sec=490.258M/s
BM_StdMidpoint<uint8_t, ZeroRand>_BigO 2.04 N 2.04 N
BM_StdMidpoint<uint8_t, ZeroRand>_RMS 0 % 0 %
Comparing ./llvm-cmov-bench-OLD to ./llvm-cmov-bench-NEW
Benchmark Time CPU Time Old Time New CPU Old CPU New
----------------------------------------------------------------------------------------------------------------------------------------
<...>
BM_StdMidpoint<int32_t, RandRand>/131072 +0.0016 +0.0016 300398 300878 300404 300880
<...>
BM_StdMidpoint<uint32_t, RandRand>/131072 -0.0007 -0.0007 300433 300231 300433 300226
<...>
BM_StdMidpoint<int64_t, RandRand>/65536 +0.0057 +0.0054 169857 170819 169858 170777
<...>
BM_StdMidpoint<uint64_t, RandRand>/65536 +0.0114 +0.0114 169770 171705 169771 171708
<...>
BM_StdMidpoint<int16_t, RandRand>/262144 +0.0023 +0.0023 591169 592510 591179 592516
<...>
BM_StdMidpoint<uint16_t, RandRand>/262144 +0.0398 +0.0398 591264 614823 591274 614823
<...>
BM_StdMidpoint<int8_t, RandRand>/524288 -0.6403 -0.6403 2983669 1073181 2983689 1073201
<...>
BM_StdMidpoint<uint8_t, RandRand>/524288 -0.5986 -0.5986 2668398 1071010 2668419 1071020
<...>
BM_StdMidpoint<uint32_t, ZeroRand>/131072 -0.0016 -0.0016 300887 300413 300887 300416
<...>
BM_StdMidpoint<uint64_t, ZeroRand>/65536 +0.0002 +0.0002 169634 169667 169634 169669
<...>
BM_StdMidpoint<uint16_t, ZeroRand>/262144 -0.0014 -0.0014 592252 591396 592255 591404
<...>
BM_StdMidpoint<uint8_t, ZeroRand>/524288 +0.0832 +0.0832 987295 1069421 987309 1069413
```
What can we tell from the benchmark?
* `BM_StdMidpoint<[u]int8_t, RandRand>` indeed has the worst performance.
* All `BM_StdMidpoint<uint{8,16,32}_t, ZeroRand>` are all performant, even the 8-bit case.
That is because there we are computing mid point between zero and some random number,
thus if the branch predictor is in use, it is in optimal situation.
* Promoting 8-bit CMOV did improve performance of `BM_StdMidpoint<[u]int8_t, RandRand>`, by -59%..-64%.
# What about branch predictor?
* `BM_StdMidpoint<uint8_t, ZeroRand>` was faster than `BM_StdMidpoint<uint{16,32,64}_t, ZeroRand>`,
which may mean that well-predicted branch is better than `cmov`.
* Promoting 8-bit CMOV degraded performance of `BM_StdMidpoint<uint8_t, ZeroRand>`,
`cmov` is up to +10% worse than well-predicted branch.
* However, i do not believe this is a concern. If the branch is well predicted, then the PGO
will also say that it is well predicted, and LLVM will happily expand cmov back into branch:
https://godbolt.org/z/P5ufig
# What about partial register stalls?
I'm not really able to answer that.
What i can say is that if the branch is unpredictable (if it is predictable, then use PGO and you'll have branch)
in ~50% of cases you will have to pay branch misprediction penalty.
```
$ grep -i MispredictPenalty X86Sched*.td
X86SchedBroadwell.td: let MispredictPenalty = 16;
X86SchedHaswell.td: let MispredictPenalty = 16;
X86SchedSandyBridge.td: let MispredictPenalty = 16;
X86SchedSkylakeClient.td: let MispredictPenalty = 14;
X86SchedSkylakeServer.td: let MispredictPenalty = 14;
X86ScheduleBdVer2.td: let MispredictPenalty = 20; // Minimum branch misdirection penalty.
X86ScheduleBtVer2.td: let MispredictPenalty = 14; // Minimum branch misdirection penalty
X86ScheduleSLM.td: let MispredictPenalty = 10;
X86ScheduleZnver1.td: let MispredictPenalty = 17;
```
.. which it can be as small as 10 cycles and as large as 20 cycles.
Partial register stalls do not seem to be an issue for AMD CPU's.
For intel CPU's, they should be around ~5 cycles?
Is that actually an issue here? I'm not sure.
In short, i'd say this is an improvement, at least on this microbenchmark.
Fixes [[ https://bugs.llvm.org/show_bug.cgi?id=40965 | PR40965 ]].
Reviewers: craig.topper, RKSimon, spatel, andreadb, nikic
Reviewed By: craig.topper, andreadb
Subscribers: jfb, jdoerfert, llvm-commits, mclow.lists
Tags: #llvm, #libc
Differential Revision: https://reviews.llvm.org/D59035
llvm-svn: 356300
2019-03-16 05:17:53 +08:00
|
|
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; SSE-NEXT: movzbl %al, %eax
|
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; SSE-NEXT: movl $255, %ecx
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; SSE-NEXT: cmovael %eax, %ecx
|
2018-12-18 21:22:53 +08:00
|
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; SSE-NEXT: movb %cl, (%rdx)
|
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; SSE-NEXT: retq
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;
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; AVX-LABEL: v1i8:
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; AVX: # %bb.0:
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; AVX-NEXT: movb (%rdi), %al
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; AVX-NEXT: addb (%rsi), %al
|
[X86] Promote i8 CMOV's (PR40965)
Summary:
@mclow.lists brought up this issue up in IRC, it came up during
implementation of libc++ `std::midpoint()` implementation (D59099)
https://godbolt.org/z/oLrHBP
Currently LLVM X86 backend only promotes i8 CMOV if it came from 2x`trunc`.
This differential proposes to always promote i8 CMOV.
There are several concerns here:
* Is this actually more performant, or is it just the ASM that looks cuter?
* Does this result in partial register stalls?
* What about branch predictor?
# Indeed, performance should be the main point here.
Let's look at a simple microbenchmark: {F8412076}
```
#include "benchmark/benchmark.h"
#include <algorithm>
#include <cmath>
#include <cstdint>
#include <iterator>
#include <limits>
#include <random>
#include <type_traits>
#include <utility>
#include <vector>
// Future preliminary libc++ code, from Marshall Clow.
namespace std {
template <class _Tp>
__inline _Tp midpoint(_Tp __a, _Tp __b) noexcept {
using _Up = typename std::make_unsigned<typename remove_cv<_Tp>::type>::type;
int __sign = 1;
_Up __m = __a;
_Up __M = __b;
if (__a > __b) {
__sign = -1;
__m = __b;
__M = __a;
}
return __a + __sign * _Tp(_Up(__M - __m) >> 1);
}
} // namespace std
template <typename T>
std::vector<T> getVectorOfRandomNumbers(size_t count) {
std::random_device rd;
std::mt19937 gen(rd());
std::uniform_int_distribution<T> dis(std::numeric_limits<T>::min(),
std::numeric_limits<T>::max());
std::vector<T> v;
v.reserve(count);
std::generate_n(std::back_inserter(v), count,
[&dis, &gen]() { return dis(gen); });
assert(v.size() == count);
return v;
}
struct RandRand {
template <typename T>
static std::pair<std::vector<T>, std::vector<T>> Gen(size_t count) {
return std::make_pair(getVectorOfRandomNumbers<T>(count),
getVectorOfRandomNumbers<T>(count));
}
};
struct ZeroRand {
template <typename T>
static std::pair<std::vector<T>, std::vector<T>> Gen(size_t count) {
return std::make_pair(std::vector<T>(count, T(0)),
getVectorOfRandomNumbers<T>(count));
}
};
template <class T, class Gen>
void BM_StdMidpoint(benchmark::State& state) {
const size_t Length = state.range(0);
const std::pair<std::vector<T>, std::vector<T>> Data =
Gen::template Gen<T>(Length);
const std::vector<T>& a = Data.first;
const std::vector<T>& b = Data.second;
assert(a.size() == Length && b.size() == a.size());
benchmark::ClobberMemory();
benchmark::DoNotOptimize(a);
benchmark::DoNotOptimize(a.data());
benchmark::DoNotOptimize(b);
benchmark::DoNotOptimize(b.data());
for (auto _ : state) {
for (size_t i = 0; i < Length; i++) {
const auto calculated = std::midpoint(a[i], b[i]);
benchmark::DoNotOptimize(calculated);
}
}
state.SetComplexityN(Length);
state.counters["midpoints"] =
benchmark::Counter(Length, benchmark::Counter::kIsIterationInvariant);
state.counters["midpoints/sec"] =
benchmark::Counter(Length, benchmark::Counter::kIsIterationInvariantRate);
const size_t BytesRead = 2 * sizeof(T) * Length;
state.counters["bytes_read/iteration"] =
benchmark::Counter(BytesRead, benchmark::Counter::kDefaults,
benchmark::Counter::OneK::kIs1024);
state.counters["bytes_read/sec"] = benchmark::Counter(
BytesRead, benchmark::Counter::kIsIterationInvariantRate,
benchmark::Counter::OneK::kIs1024);
}
template <typename T>
static void CustomArguments(benchmark::internal::Benchmark* b) {
const size_t L2SizeBytes = 2 * 1024 * 1024;
// What is the largest range we can check to always fit within given L2 cache?
const size_t MaxLen = L2SizeBytes / /*total bufs*/ 2 /
/*maximal elt size*/ sizeof(T) / /*safety margin*/ 2;
b->RangeMultiplier(2)->Range(1, MaxLen)->Complexity(benchmark::oN);
}
// Both of the values are random.
// The comparison is unpredictable.
BENCHMARK_TEMPLATE(BM_StdMidpoint, int32_t, RandRand)
->Apply(CustomArguments<int32_t>);
BENCHMARK_TEMPLATE(BM_StdMidpoint, uint32_t, RandRand)
->Apply(CustomArguments<uint32_t>);
BENCHMARK_TEMPLATE(BM_StdMidpoint, int64_t, RandRand)
->Apply(CustomArguments<int64_t>);
BENCHMARK_TEMPLATE(BM_StdMidpoint, uint64_t, RandRand)
->Apply(CustomArguments<uint64_t>);
BENCHMARK_TEMPLATE(BM_StdMidpoint, int16_t, RandRand)
->Apply(CustomArguments<int16_t>);
BENCHMARK_TEMPLATE(BM_StdMidpoint, uint16_t, RandRand)
->Apply(CustomArguments<uint16_t>);
BENCHMARK_TEMPLATE(BM_StdMidpoint, int8_t, RandRand)
->Apply(CustomArguments<int8_t>);
BENCHMARK_TEMPLATE(BM_StdMidpoint, uint8_t, RandRand)
->Apply(CustomArguments<uint8_t>);
// One value is always zero, and another is bigger or equal than zero.
// The comparison is predictable.
BENCHMARK_TEMPLATE(BM_StdMidpoint, uint32_t, ZeroRand)
->Apply(CustomArguments<uint32_t>);
BENCHMARK_TEMPLATE(BM_StdMidpoint, uint64_t, ZeroRand)
->Apply(CustomArguments<uint64_t>);
BENCHMARK_TEMPLATE(BM_StdMidpoint, uint16_t, ZeroRand)
->Apply(CustomArguments<uint16_t>);
BENCHMARK_TEMPLATE(BM_StdMidpoint, uint8_t, ZeroRand)
->Apply(CustomArguments<uint8_t>);
```
```
$ ~/src/googlebenchmark/tools/compare.py --no-utest benchmarks ./llvm-cmov-bench-OLD ./llvm-cmov-bench-NEW
RUNNING: ./llvm-cmov-bench-OLD --benchmark_out=/tmp/tmp5a5qjm
2019-03-06 21:53:31
Running ./llvm-cmov-bench-OLD
Run on (8 X 4000 MHz CPU s)
CPU Caches:
L1 Data 16K (x8)
L1 Instruction 64K (x4)
L2 Unified 2048K (x4)
L3 Unified 8192K (x1)
Load Average: 1.78, 1.81, 1.36
----------------------------------------------------------------------------------------------------
Benchmark Time CPU Iterations UserCounters<...>
----------------------------------------------------------------------------------------------------
<...>
BM_StdMidpoint<int32_t, RandRand>/131072 300398 ns 300404 ns 2330 bytes_read/iteration=1024k bytes_read/sec=3.25083G/s midpoints=305.398M midpoints/sec=436.319M/s
BM_StdMidpoint<int32_t, RandRand>_BigO 2.29 N 2.29 N
BM_StdMidpoint<int32_t, RandRand>_RMS 2 % 2 %
<...>
BM_StdMidpoint<uint32_t, RandRand>/131072 300433 ns 300433 ns 2330 bytes_read/iteration=1024k bytes_read/sec=3.25052G/s midpoints=305.398M midpoints/sec=436.278M/s
BM_StdMidpoint<uint32_t, RandRand>_BigO 2.29 N 2.29 N
BM_StdMidpoint<uint32_t, RandRand>_RMS 2 % 2 %
<...>
BM_StdMidpoint<int64_t, RandRand>/65536 169857 ns 169858 ns 4121 bytes_read/iteration=1024k bytes_read/sec=5.74929G/s midpoints=270.074M midpoints/sec=385.828M/s
BM_StdMidpoint<int64_t, RandRand>_BigO 2.59 N 2.59 N
BM_StdMidpoint<int64_t, RandRand>_RMS 3 % 3 %
<...>
BM_StdMidpoint<uint64_t, RandRand>/65536 169770 ns 169771 ns 4125 bytes_read/iteration=1024k bytes_read/sec=5.75223G/s midpoints=270.336M midpoints/sec=386.026M/s
BM_StdMidpoint<uint64_t, RandRand>_BigO 2.59 N 2.59 N
BM_StdMidpoint<uint64_t, RandRand>_RMS 3 % 3 %
<...>
BM_StdMidpoint<int16_t, RandRand>/262144 591169 ns 591179 ns 1182 bytes_read/iteration=1024k bytes_read/sec=1.65189G/s midpoints=309.854M midpoints/sec=443.426M/s
BM_StdMidpoint<int16_t, RandRand>_BigO 2.25 N 2.25 N
BM_StdMidpoint<int16_t, RandRand>_RMS 1 % 1 %
<...>
BM_StdMidpoint<uint16_t, RandRand>/262144 591264 ns 591274 ns 1184 bytes_read/iteration=1024k bytes_read/sec=1.65162G/s midpoints=310.378M midpoints/sec=443.354M/s
BM_StdMidpoint<uint16_t, RandRand>_BigO 2.25 N 2.25 N
BM_StdMidpoint<uint16_t, RandRand>_RMS 1 % 1 %
<...>
BM_StdMidpoint<int8_t, RandRand>/524288 2983669 ns 2983689 ns 235 bytes_read/iteration=1024k bytes_read/sec=335.156M/s midpoints=123.208M midpoints/sec=175.718M/s
BM_StdMidpoint<int8_t, RandRand>_BigO 5.69 N 5.69 N
BM_StdMidpoint<int8_t, RandRand>_RMS 0 % 0 %
<...>
BM_StdMidpoint<uint8_t, RandRand>/524288 2668398 ns 2668419 ns 262 bytes_read/iteration=1024k bytes_read/sec=374.754M/s midpoints=137.363M midpoints/sec=196.479M/s
BM_StdMidpoint<uint8_t, RandRand>_BigO 5.09 N 5.09 N
BM_StdMidpoint<uint8_t, RandRand>_RMS 0 % 0 %
<...>
BM_StdMidpoint<uint32_t, ZeroRand>/131072 300887 ns 300887 ns 2331 bytes_read/iteration=1024k bytes_read/sec=3.24561G/s midpoints=305.529M midpoints/sec=435.619M/s
BM_StdMidpoint<uint32_t, ZeroRand>_BigO 2.29 N 2.29 N
BM_StdMidpoint<uint32_t, ZeroRand>_RMS 2 % 2 %
<...>
BM_StdMidpoint<uint64_t, ZeroRand>/65536 169634 ns 169634 ns 4102 bytes_read/iteration=1024k bytes_read/sec=5.75688G/s midpoints=268.829M midpoints/sec=386.338M/s
BM_StdMidpoint<uint64_t, ZeroRand>_BigO 2.59 N 2.59 N
BM_StdMidpoint<uint64_t, ZeroRand>_RMS 3 % 3 %
<...>
BM_StdMidpoint<uint16_t, ZeroRand>/262144 592252 ns 592255 ns 1182 bytes_read/iteration=1024k bytes_read/sec=1.64889G/s midpoints=309.854M midpoints/sec=442.62M/s
BM_StdMidpoint<uint16_t, ZeroRand>_BigO 2.26 N 2.26 N
BM_StdMidpoint<uint16_t, ZeroRand>_RMS 1 % 1 %
<...>
BM_StdMidpoint<uint8_t, ZeroRand>/524288 987295 ns 987309 ns 711 bytes_read/iteration=1024k bytes_read/sec=1012.85M/s midpoints=372.769M midpoints/sec=531.028M/s
BM_StdMidpoint<uint8_t, ZeroRand>_BigO 1.88 N 1.88 N
BM_StdMidpoint<uint8_t, ZeroRand>_RMS 1 % 1 %
RUNNING: ./llvm-cmov-bench-NEW --benchmark_out=/tmp/tmpPvwpfW
2019-03-06 21:56:58
Running ./llvm-cmov-bench-NEW
Run on (8 X 4000 MHz CPU s)
CPU Caches:
L1 Data 16K (x8)
L1 Instruction 64K (x4)
L2 Unified 2048K (x4)
L3 Unified 8192K (x1)
Load Average: 1.17, 1.46, 1.30
----------------------------------------------------------------------------------------------------
Benchmark Time CPU Iterations UserCounters<...>
----------------------------------------------------------------------------------------------------
<...>
BM_StdMidpoint<int32_t, RandRand>/131072 300878 ns 300880 ns 2324 bytes_read/iteration=1024k bytes_read/sec=3.24569G/s midpoints=304.611M midpoints/sec=435.629M/s
BM_StdMidpoint<int32_t, RandRand>_BigO 2.29 N 2.29 N
BM_StdMidpoint<int32_t, RandRand>_RMS 2 % 2 %
<...>
BM_StdMidpoint<uint32_t, RandRand>/131072 300231 ns 300226 ns 2330 bytes_read/iteration=1024k bytes_read/sec=3.25276G/s midpoints=305.398M midpoints/sec=436.578M/s
BM_StdMidpoint<uint32_t, RandRand>_BigO 2.29 N 2.29 N
BM_StdMidpoint<uint32_t, RandRand>_RMS 2 % 2 %
<...>
BM_StdMidpoint<int64_t, RandRand>/65536 170819 ns 170777 ns 4115 bytes_read/iteration=1024k bytes_read/sec=5.71835G/s midpoints=269.681M midpoints/sec=383.752M/s
BM_StdMidpoint<int64_t, RandRand>_BigO 2.60 N 2.60 N
BM_StdMidpoint<int64_t, RandRand>_RMS 3 % 3 %
<...>
BM_StdMidpoint<uint64_t, RandRand>/65536 171705 ns 171708 ns 4106 bytes_read/iteration=1024k bytes_read/sec=5.68733G/s midpoints=269.091M midpoints/sec=381.671M/s
BM_StdMidpoint<uint64_t, RandRand>_BigO 2.62 N 2.62 N
BM_StdMidpoint<uint64_t, RandRand>_RMS 3 % 3 %
<...>
BM_StdMidpoint<int16_t, RandRand>/262144 592510 ns 592516 ns 1182 bytes_read/iteration=1024k bytes_read/sec=1.64816G/s midpoints=309.854M midpoints/sec=442.425M/s
BM_StdMidpoint<int16_t, RandRand>_BigO 2.26 N 2.26 N
BM_StdMidpoint<int16_t, RandRand>_RMS 1 % 1 %
<...>
BM_StdMidpoint<uint16_t, RandRand>/262144 614823 ns 614823 ns 1180 bytes_read/iteration=1024k bytes_read/sec=1.58836G/s midpoints=309.33M midpoints/sec=426.373M/s
BM_StdMidpoint<uint16_t, RandRand>_BigO 2.33 N 2.33 N
BM_StdMidpoint<uint16_t, RandRand>_RMS 4 % 4 %
<...>
BM_StdMidpoint<int8_t, RandRand>/524288 1073181 ns 1073201 ns 650 bytes_read/iteration=1024k bytes_read/sec=931.791M/s midpoints=340.787M midpoints/sec=488.527M/s
BM_StdMidpoint<int8_t, RandRand>_BigO 2.05 N 2.05 N
BM_StdMidpoint<int8_t, RandRand>_RMS 1 % 1 %
BM_StdMidpoint<uint8_t, RandRand>/524288 1071010 ns 1071020 ns 653 bytes_read/iteration=1024k bytes_read/sec=933.689M/s midpoints=342.36M midpoints/sec=489.522M/s
BM_StdMidpoint<uint8_t, RandRand>_BigO 2.05 N 2.05 N
BM_StdMidpoint<uint8_t, RandRand>_RMS 1 % 1 %
<...>
BM_StdMidpoint<uint32_t, ZeroRand>/131072 300413 ns 300416 ns 2330 bytes_read/iteration=1024k bytes_read/sec=3.2507G/s midpoints=305.398M midpoints/sec=436.302M/s
BM_StdMidpoint<uint32_t, ZeroRand>_BigO 2.29 N 2.29 N
BM_StdMidpoint<uint32_t, ZeroRand>_RMS 2 % 2 %
<...>
BM_StdMidpoint<uint64_t, ZeroRand>/65536 169667 ns 169669 ns 4123 bytes_read/iteration=1024k bytes_read/sec=5.75568G/s midpoints=270.205M midpoints/sec=386.257M/s
BM_StdMidpoint<uint64_t, ZeroRand>_BigO 2.59 N 2.59 N
BM_StdMidpoint<uint64_t, ZeroRand>_RMS 3 % 3 %
<...>
BM_StdMidpoint<uint16_t, ZeroRand>/262144 591396 ns 591404 ns 1184 bytes_read/iteration=1024k bytes_read/sec=1.65126G/s midpoints=310.378M midpoints/sec=443.257M/s
BM_StdMidpoint<uint16_t, ZeroRand>_BigO 2.26 N 2.26 N
BM_StdMidpoint<uint16_t, ZeroRand>_RMS 1 % 1 %
<...>
BM_StdMidpoint<uint8_t, ZeroRand>/524288 1069421 ns 1069413 ns 655 bytes_read/iteration=1024k bytes_read/sec=935.092M/s midpoints=343.409M midpoints/sec=490.258M/s
BM_StdMidpoint<uint8_t, ZeroRand>_BigO 2.04 N 2.04 N
BM_StdMidpoint<uint8_t, ZeroRand>_RMS 0 % 0 %
Comparing ./llvm-cmov-bench-OLD to ./llvm-cmov-bench-NEW
Benchmark Time CPU Time Old Time New CPU Old CPU New
----------------------------------------------------------------------------------------------------------------------------------------
<...>
BM_StdMidpoint<int32_t, RandRand>/131072 +0.0016 +0.0016 300398 300878 300404 300880
<...>
BM_StdMidpoint<uint32_t, RandRand>/131072 -0.0007 -0.0007 300433 300231 300433 300226
<...>
BM_StdMidpoint<int64_t, RandRand>/65536 +0.0057 +0.0054 169857 170819 169858 170777
<...>
BM_StdMidpoint<uint64_t, RandRand>/65536 +0.0114 +0.0114 169770 171705 169771 171708
<...>
BM_StdMidpoint<int16_t, RandRand>/262144 +0.0023 +0.0023 591169 592510 591179 592516
<...>
BM_StdMidpoint<uint16_t, RandRand>/262144 +0.0398 +0.0398 591264 614823 591274 614823
<...>
BM_StdMidpoint<int8_t, RandRand>/524288 -0.6403 -0.6403 2983669 1073181 2983689 1073201
<...>
BM_StdMidpoint<uint8_t, RandRand>/524288 -0.5986 -0.5986 2668398 1071010 2668419 1071020
<...>
BM_StdMidpoint<uint32_t, ZeroRand>/131072 -0.0016 -0.0016 300887 300413 300887 300416
<...>
BM_StdMidpoint<uint64_t, ZeroRand>/65536 +0.0002 +0.0002 169634 169667 169634 169669
<...>
BM_StdMidpoint<uint16_t, ZeroRand>/262144 -0.0014 -0.0014 592252 591396 592255 591404
<...>
BM_StdMidpoint<uint8_t, ZeroRand>/524288 +0.0832 +0.0832 987295 1069421 987309 1069413
```
What can we tell from the benchmark?
* `BM_StdMidpoint<[u]int8_t, RandRand>` indeed has the worst performance.
* All `BM_StdMidpoint<uint{8,16,32}_t, ZeroRand>` are all performant, even the 8-bit case.
That is because there we are computing mid point between zero and some random number,
thus if the branch predictor is in use, it is in optimal situation.
* Promoting 8-bit CMOV did improve performance of `BM_StdMidpoint<[u]int8_t, RandRand>`, by -59%..-64%.
# What about branch predictor?
* `BM_StdMidpoint<uint8_t, ZeroRand>` was faster than `BM_StdMidpoint<uint{16,32,64}_t, ZeroRand>`,
which may mean that well-predicted branch is better than `cmov`.
* Promoting 8-bit CMOV degraded performance of `BM_StdMidpoint<uint8_t, ZeroRand>`,
`cmov` is up to +10% worse than well-predicted branch.
* However, i do not believe this is a concern. If the branch is well predicted, then the PGO
will also say that it is well predicted, and LLVM will happily expand cmov back into branch:
https://godbolt.org/z/P5ufig
# What about partial register stalls?
I'm not really able to answer that.
What i can say is that if the branch is unpredictable (if it is predictable, then use PGO and you'll have branch)
in ~50% of cases you will have to pay branch misprediction penalty.
```
$ grep -i MispredictPenalty X86Sched*.td
X86SchedBroadwell.td: let MispredictPenalty = 16;
X86SchedHaswell.td: let MispredictPenalty = 16;
X86SchedSandyBridge.td: let MispredictPenalty = 16;
X86SchedSkylakeClient.td: let MispredictPenalty = 14;
X86SchedSkylakeServer.td: let MispredictPenalty = 14;
X86ScheduleBdVer2.td: let MispredictPenalty = 20; // Minimum branch misdirection penalty.
X86ScheduleBtVer2.td: let MispredictPenalty = 14; // Minimum branch misdirection penalty
X86ScheduleSLM.td: let MispredictPenalty = 10;
X86ScheduleZnver1.td: let MispredictPenalty = 17;
```
.. which it can be as small as 10 cycles and as large as 20 cycles.
Partial register stalls do not seem to be an issue for AMD CPU's.
For intel CPU's, they should be around ~5 cycles?
Is that actually an issue here? I'm not sure.
In short, i'd say this is an improvement, at least on this microbenchmark.
Fixes [[ https://bugs.llvm.org/show_bug.cgi?id=40965 | PR40965 ]].
Reviewers: craig.topper, RKSimon, spatel, andreadb, nikic
Reviewed By: craig.topper, andreadb
Subscribers: jfb, jdoerfert, llvm-commits, mclow.lists
Tags: #llvm, #libc
Differential Revision: https://reviews.llvm.org/D59035
llvm-svn: 356300
2019-03-16 05:17:53 +08:00
|
|
|
; AVX-NEXT: movzbl %al, %eax
|
|
|
|
|
; AVX-NEXT: movl $255, %ecx
|
|
|
|
|
; AVX-NEXT: cmovael %eax, %ecx
|
2018-12-18 21:22:53 +08:00
|
|
|
; AVX-NEXT: movb %cl, (%rdx)
|
|
|
|
|
; AVX-NEXT: retq
|
|
|
|
|
%x = load <1 x i8>, <1 x i8>* %px
|
|
|
|
|
%y = load <1 x i8>, <1 x i8>* %py
|
|
|
|
|
%z = call <1 x i8> @llvm.uadd.sat.v1i8(<1 x i8> %x, <1 x i8> %y)
|
|
|
|
|
store <1 x i8> %z, <1 x i8>* %pz
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define void @v1i16(<1 x i16>* %px, <1 x i16>* %py, <1 x i16>* %pz) nounwind {
|
|
|
|
|
; SSE-LABEL: v1i16:
|
|
|
|
|
; SSE: # %bb.0:
|
|
|
|
|
; SSE-NEXT: movzwl (%rdi), %eax
|
|
|
|
|
; SSE-NEXT: addw (%rsi), %ax
|
|
|
|
|
; SSE-NEXT: movl $65535, %ecx # imm = 0xFFFF
|
|
|
|
|
; SSE-NEXT: cmovael %eax, %ecx
|
|
|
|
|
; SSE-NEXT: movw %cx, (%rdx)
|
|
|
|
|
; SSE-NEXT: retq
|
|
|
|
|
;
|
|
|
|
|
; AVX-LABEL: v1i16:
|
|
|
|
|
; AVX: # %bb.0:
|
|
|
|
|
; AVX-NEXT: movzwl (%rdi), %eax
|
|
|
|
|
; AVX-NEXT: addw (%rsi), %ax
|
|
|
|
|
; AVX-NEXT: movl $65535, %ecx # imm = 0xFFFF
|
|
|
|
|
; AVX-NEXT: cmovael %eax, %ecx
|
|
|
|
|
; AVX-NEXT: movw %cx, (%rdx)
|
|
|
|
|
; AVX-NEXT: retq
|
|
|
|
|
%x = load <1 x i16>, <1 x i16>* %px
|
|
|
|
|
%y = load <1 x i16>, <1 x i16>* %py
|
|
|
|
|
%z = call <1 x i16> @llvm.uadd.sat.v1i16(<1 x i16> %x, <1 x i16> %y)
|
|
|
|
|
store <1 x i16> %z, <1 x i16>* %pz
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; Promotion
|
|
|
|
|
|
|
|
|
|
define <16 x i4> @v16i4(<16 x i4> %x, <16 x i4> %y) nounwind {
|
2018-12-18 21:23:03 +08:00
|
|
|
; SSE-LABEL: v16i4:
|
|
|
|
|
; SSE: # %bb.0:
|
|
|
|
|
; SSE-NEXT: psllw $4, %xmm1
|
|
|
|
|
; SSE-NEXT: movdqa {{.*#+}} xmm2 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240]
|
|
|
|
|
; SSE-NEXT: pand %xmm2, %xmm1
|
|
|
|
|
; SSE-NEXT: psllw $4, %xmm0
|
|
|
|
|
; SSE-NEXT: pand %xmm2, %xmm0
|
|
|
|
|
; SSE-NEXT: paddusb %xmm1, %xmm0
|
|
|
|
|
; SSE-NEXT: psrlw $4, %xmm0
|
|
|
|
|
; SSE-NEXT: pand {{.*}}(%rip), %xmm0
|
|
|
|
|
; SSE-NEXT: retq
|
2018-12-18 21:22:53 +08:00
|
|
|
;
|
|
|
|
|
; AVX-LABEL: v16i4:
|
|
|
|
|
; AVX: # %bb.0:
|
|
|
|
|
; AVX-NEXT: vpsllw $4, %xmm1, %xmm1
|
|
|
|
|
; AVX-NEXT: vmovdqa {{.*#+}} xmm2 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240]
|
|
|
|
|
; AVX-NEXT: vpand %xmm2, %xmm1, %xmm1
|
|
|
|
|
; AVX-NEXT: vpsllw $4, %xmm0, %xmm0
|
|
|
|
|
; AVX-NEXT: vpand %xmm2, %xmm0, %xmm0
|
2018-12-18 21:23:03 +08:00
|
|
|
; AVX-NEXT: vpaddusb %xmm1, %xmm0, %xmm0
|
2018-12-18 21:22:53 +08:00
|
|
|
; AVX-NEXT: vpsrlw $4, %xmm0, %xmm0
|
|
|
|
|
; AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
|
|
|
|
|
; AVX-NEXT: retq
|
|
|
|
|
%z = call <16 x i4> @llvm.uadd.sat.v16i4(<16 x i4> %x, <16 x i4> %y)
|
|
|
|
|
ret <16 x i4> %z
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define <16 x i1> @v16i1(<16 x i1> %x, <16 x i1> %y) nounwind {
|
2018-12-18 21:23:03 +08:00
|
|
|
; SSE-LABEL: v16i1:
|
|
|
|
|
; SSE: # %bb.0:
|
|
|
|
|
; SSE-NEXT: psllw $7, %xmm1
|
|
|
|
|
; SSE-NEXT: movdqa {{.*#+}} xmm2 = [128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128]
|
|
|
|
|
; SSE-NEXT: pand %xmm2, %xmm1
|
|
|
|
|
; SSE-NEXT: psllw $7, %xmm0
|
|
|
|
|
; SSE-NEXT: pand %xmm2, %xmm0
|
|
|
|
|
; SSE-NEXT: paddusb %xmm1, %xmm0
|
|
|
|
|
; SSE-NEXT: psrlw $7, %xmm0
|
|
|
|
|
; SSE-NEXT: pand {{.*}}(%rip), %xmm0
|
|
|
|
|
; SSE-NEXT: retq
|
2018-12-18 21:22:53 +08:00
|
|
|
;
|
|
|
|
|
; AVX1-LABEL: v16i1:
|
|
|
|
|
; AVX1: # %bb.0:
|
|
|
|
|
; AVX1-NEXT: vpsllw $7, %xmm1, %xmm1
|
|
|
|
|
; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128]
|
|
|
|
|
; AVX1-NEXT: vpand %xmm2, %xmm1, %xmm1
|
|
|
|
|
; AVX1-NEXT: vpsllw $7, %xmm0, %xmm0
|
|
|
|
|
; AVX1-NEXT: vpand %xmm2, %xmm0, %xmm0
|
2018-12-18 21:23:03 +08:00
|
|
|
; AVX1-NEXT: vpaddusb %xmm1, %xmm0, %xmm0
|
2018-12-18 21:22:53 +08:00
|
|
|
; AVX1-NEXT: vpsrlw $7, %xmm0, %xmm0
|
|
|
|
|
; AVX1-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
|
|
|
|
|
; AVX1-NEXT: retq
|
|
|
|
|
;
|
|
|
|
|
; AVX2-LABEL: v16i1:
|
|
|
|
|
; AVX2: # %bb.0:
|
|
|
|
|
; AVX2-NEXT: vpsllw $7, %xmm1, %xmm1
|
|
|
|
|
; AVX2-NEXT: vmovdqa {{.*#+}} xmm2 = [128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128]
|
|
|
|
|
; AVX2-NEXT: vpand %xmm2, %xmm1, %xmm1
|
|
|
|
|
; AVX2-NEXT: vpsllw $7, %xmm0, %xmm0
|
|
|
|
|
; AVX2-NEXT: vpand %xmm2, %xmm0, %xmm0
|
2018-12-18 21:23:03 +08:00
|
|
|
; AVX2-NEXT: vpaddusb %xmm1, %xmm0, %xmm0
|
2018-12-18 21:22:53 +08:00
|
|
|
; AVX2-NEXT: vpsrlw $7, %xmm0, %xmm0
|
|
|
|
|
; AVX2-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
|
|
|
|
|
; AVX2-NEXT: retq
|
|
|
|
|
;
|
|
|
|
|
; AVX512-LABEL: v16i1:
|
|
|
|
|
; AVX512: # %bb.0:
|
2018-12-18 21:23:03 +08:00
|
|
|
; AVX512-NEXT: vpsllw $7, %xmm1, %xmm1
|
|
|
|
|
; AVX512-NEXT: vpmovb2m %xmm1, %k0
|
2018-12-18 21:22:53 +08:00
|
|
|
; AVX512-NEXT: vpsllw $7, %xmm0, %xmm0
|
|
|
|
|
; AVX512-NEXT: vpmovb2m %xmm0, %k1
|
2018-12-18 21:23:03 +08:00
|
|
|
; AVX512-NEXT: korw %k0, %k1, %k0
|
2018-12-18 21:22:53 +08:00
|
|
|
; AVX512-NEXT: vpmovm2b %k0, %xmm0
|
|
|
|
|
; AVX512-NEXT: retq
|
|
|
|
|
%z = call <16 x i1> @llvm.uadd.sat.v16i1(<16 x i1> %x, <16 x i1> %y)
|
|
|
|
|
ret <16 x i1> %z
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; Expanded
|
|
|
|
|
|
|
|
|
|
define <2 x i32> @v2i32(<2 x i32> %x, <2 x i32> %y) nounwind {
|
|
|
|
|
; SSE2-LABEL: v2i32:
|
|
|
|
|
; SSE2: # %bb.0:
|
|
|
|
|
; SSE2-NEXT: psllq $32, %xmm0
|
2019-01-29 03:19:09 +08:00
|
|
|
; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [9223372039002259456,9223372039002259456]
|
|
|
|
|
; SSE2-NEXT: psllq $32, %xmm1
|
2019-03-24 21:55:54 +08:00
|
|
|
; SSE2-NEXT: paddq %xmm0, %xmm1
|
|
|
|
|
; SSE2-NEXT: pxor %xmm2, %xmm0
|
|
|
|
|
; SSE2-NEXT: pxor %xmm1, %xmm2
|
|
|
|
|
; SSE2-NEXT: movdqa %xmm0, %xmm3
|
2019-01-29 03:19:09 +08:00
|
|
|
; SSE2-NEXT: pcmpeqd %xmm2, %xmm3
|
2019-03-24 21:55:54 +08:00
|
|
|
; SSE2-NEXT: pcmpgtd %xmm2, %xmm0
|
|
|
|
|
; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[0,0,2,2]
|
|
|
|
|
; SSE2-NEXT: pand %xmm2, %xmm3
|
|
|
|
|
; SSE2-NEXT: por %xmm1, %xmm0
|
2019-01-29 03:19:09 +08:00
|
|
|
; SSE2-NEXT: por %xmm3, %xmm0
|
|
|
|
|
; SSE2-NEXT: psrlq $32, %xmm0
|
2018-12-18 21:22:53 +08:00
|
|
|
; SSE2-NEXT: retq
|
|
|
|
|
;
|
|
|
|
|
; SSSE3-LABEL: v2i32:
|
|
|
|
|
; SSSE3: # %bb.0:
|
|
|
|
|
; SSSE3-NEXT: psllq $32, %xmm0
|
2019-01-29 03:19:09 +08:00
|
|
|
; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [9223372039002259456,9223372039002259456]
|
|
|
|
|
; SSSE3-NEXT: psllq $32, %xmm1
|
2019-03-24 21:55:54 +08:00
|
|
|
; SSSE3-NEXT: paddq %xmm0, %xmm1
|
|
|
|
|
; SSSE3-NEXT: pxor %xmm2, %xmm0
|
|
|
|
|
; SSSE3-NEXT: pxor %xmm1, %xmm2
|
|
|
|
|
; SSSE3-NEXT: movdqa %xmm0, %xmm3
|
2019-01-29 03:19:09 +08:00
|
|
|
; SSSE3-NEXT: pcmpeqd %xmm2, %xmm3
|
2019-03-24 21:55:54 +08:00
|
|
|
; SSSE3-NEXT: pcmpgtd %xmm2, %xmm0
|
|
|
|
|
; SSSE3-NEXT: pshufd {{.*#+}} xmm2 = xmm0[0,0,2,2]
|
|
|
|
|
; SSSE3-NEXT: pand %xmm2, %xmm3
|
|
|
|
|
; SSSE3-NEXT: por %xmm1, %xmm0
|
2019-01-29 03:19:09 +08:00
|
|
|
; SSSE3-NEXT: por %xmm3, %xmm0
|
|
|
|
|
; SSSE3-NEXT: psrlq $32, %xmm0
|
2018-12-18 21:22:53 +08:00
|
|
|
; SSSE3-NEXT: retq
|
|
|
|
|
;
|
|
|
|
|
; SSE41-LABEL: v2i32:
|
|
|
|
|
; SSE41: # %bb.0:
|
2019-03-24 21:55:54 +08:00
|
|
|
; SSE41-NEXT: psllq $32, %xmm0
|
|
|
|
|
; SSE41-NEXT: movdqa {{.*#+}} xmm2 = [9223372039002259456,9223372039002259456]
|
2018-12-18 21:22:53 +08:00
|
|
|
; SSE41-NEXT: psllq $32, %xmm1
|
2019-03-24 21:55:54 +08:00
|
|
|
; SSE41-NEXT: paddq %xmm0, %xmm1
|
|
|
|
|
; SSE41-NEXT: movdqa %xmm0, %xmm3
|
|
|
|
|
; SSE41-NEXT: pxor %xmm2, %xmm3
|
|
|
|
|
; SSE41-NEXT: pxor %xmm1, %xmm2
|
2019-01-29 03:19:09 +08:00
|
|
|
; SSE41-NEXT: movdqa %xmm3, %xmm0
|
2019-03-28 03:54:41 +08:00
|
|
|
; SSE41-NEXT: pcmpgtd %xmm2, %xmm0
|
|
|
|
|
; SSE41-NEXT: pshufd {{.*#+}} xmm4 = xmm0[0,0,2,2]
|
|
|
|
|
; SSE41-NEXT: pcmpeqd %xmm3, %xmm2
|
|
|
|
|
; SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
|
|
|
|
|
; SSE41-NEXT: pand %xmm4, %xmm2
|
|
|
|
|
; SSE41-NEXT: por %xmm2, %xmm0
|
2019-03-24 21:55:54 +08:00
|
|
|
; SSE41-NEXT: pcmpeqd %xmm2, %xmm2
|
|
|
|
|
; SSE41-NEXT: blendvpd %xmm0, %xmm2, %xmm1
|
|
|
|
|
; SSE41-NEXT: psrlq $32, %xmm1
|
|
|
|
|
; SSE41-NEXT: movdqa %xmm1, %xmm0
|
2018-12-18 21:22:53 +08:00
|
|
|
; SSE41-NEXT: retq
|
|
|
|
|
;
|
2019-01-29 03:19:09 +08:00
|
|
|
; AVX1-LABEL: v2i32:
|
|
|
|
|
; AVX1: # %bb.0:
|
|
|
|
|
; AVX1-NEXT: vpsllq $32, %xmm0, %xmm0
|
2019-03-24 21:55:54 +08:00
|
|
|
; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808]
|
|
|
|
|
; AVX1-NEXT: vpxor %xmm2, %xmm0, %xmm3
|
|
|
|
|
; AVX1-NEXT: vpsllq $32, %xmm1, %xmm1
|
2019-01-29 03:19:09 +08:00
|
|
|
; AVX1-NEXT: vpaddq %xmm1, %xmm0, %xmm0
|
2019-03-24 21:55:54 +08:00
|
|
|
; AVX1-NEXT: vpxor %xmm2, %xmm0, %xmm1
|
|
|
|
|
; AVX1-NEXT: vpcmpgtq %xmm1, %xmm3, %xmm1
|
|
|
|
|
; AVX1-NEXT: vpor %xmm0, %xmm1, %xmm0
|
2019-01-29 03:19:09 +08:00
|
|
|
; AVX1-NEXT: vpsrlq $32, %xmm0, %xmm0
|
|
|
|
|
; AVX1-NEXT: retq
|
|
|
|
|
;
|
|
|
|
|
; AVX2-LABEL: v2i32:
|
|
|
|
|
; AVX2: # %bb.0:
|
|
|
|
|
; AVX2-NEXT: vpsllq $32, %xmm0, %xmm0
|
2019-03-24 21:55:54 +08:00
|
|
|
; AVX2-NEXT: vmovdqa {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808]
|
|
|
|
|
; AVX2-NEXT: vpxor %xmm2, %xmm0, %xmm3
|
|
|
|
|
; AVX2-NEXT: vpsllq $32, %xmm1, %xmm1
|
2019-01-29 03:19:09 +08:00
|
|
|
; AVX2-NEXT: vpaddq %xmm1, %xmm0, %xmm0
|
2019-03-24 21:55:54 +08:00
|
|
|
; AVX2-NEXT: vpxor %xmm2, %xmm0, %xmm1
|
|
|
|
|
; AVX2-NEXT: vpcmpgtq %xmm1, %xmm3, %xmm1
|
|
|
|
|
; AVX2-NEXT: vpor %xmm0, %xmm1, %xmm0
|
2019-01-29 03:19:09 +08:00
|
|
|
; AVX2-NEXT: vpsrlq $32, %xmm0, %xmm0
|
|
|
|
|
; AVX2-NEXT: retq
|
|
|
|
|
;
|
|
|
|
|
; AVX512-LABEL: v2i32:
|
|
|
|
|
; AVX512: # %bb.0:
|
|
|
|
|
; AVX512-NEXT: vpsllq $32, %xmm0, %xmm0
|
|
|
|
|
; AVX512-NEXT: vpsllq $32, %xmm1, %xmm1
|
|
|
|
|
; AVX512-NEXT: vmovdqa %xmm1, %xmm2
|
|
|
|
|
; AVX512-NEXT: vpternlogq $15, %xmm1, %xmm1, %xmm2
|
|
|
|
|
; AVX512-NEXT: vpminuq %xmm2, %xmm0, %xmm0
|
|
|
|
|
; AVX512-NEXT: vpaddq %xmm1, %xmm0, %xmm0
|
|
|
|
|
; AVX512-NEXT: vpsrlq $32, %xmm0, %xmm0
|
|
|
|
|
; AVX512-NEXT: retq
|
2018-12-18 21:22:53 +08:00
|
|
|
%z = call <2 x i32> @llvm.uadd.sat.v2i32(<2 x i32> %x, <2 x i32> %y)
|
|
|
|
|
ret <2 x i32> %z
|
|
|
|
|
}
|
|
|
|
|
|
2019-01-17 04:53:23 +08:00
|
|
|
define <4 x i32> @v4i32(<4 x i32> %x, <4 x i32> %y) nounwind {
|
|
|
|
|
; SSE2-LABEL: v4i32:
|
2018-12-18 21:22:53 +08:00
|
|
|
; SSE2: # %bb.0:
|
2019-01-29 03:19:09 +08:00
|
|
|
; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648]
|
2019-03-24 21:55:54 +08:00
|
|
|
; SSE2-NEXT: paddd %xmm0, %xmm1
|
|
|
|
|
; SSE2-NEXT: pxor %xmm2, %xmm0
|
|
|
|
|
; SSE2-NEXT: pxor %xmm1, %xmm2
|
|
|
|
|
; SSE2-NEXT: pcmpgtd %xmm2, %xmm0
|
|
|
|
|
; SSE2-NEXT: por %xmm1, %xmm0
|
2018-12-18 21:22:53 +08:00
|
|
|
; SSE2-NEXT: retq
|
|
|
|
|
;
|
2019-01-17 04:53:23 +08:00
|
|
|
; SSSE3-LABEL: v4i32:
|
2018-12-18 21:22:53 +08:00
|
|
|
; SSSE3: # %bb.0:
|
2019-01-29 03:19:09 +08:00
|
|
|
; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [2147483648,2147483648,2147483648,2147483648]
|
2019-03-24 21:55:54 +08:00
|
|
|
; SSSE3-NEXT: paddd %xmm0, %xmm1
|
|
|
|
|
; SSSE3-NEXT: pxor %xmm2, %xmm0
|
|
|
|
|
; SSSE3-NEXT: pxor %xmm1, %xmm2
|
|
|
|
|
; SSSE3-NEXT: pcmpgtd %xmm2, %xmm0
|
|
|
|
|
; SSSE3-NEXT: por %xmm1, %xmm0
|
2018-12-18 21:22:53 +08:00
|
|
|
; SSSE3-NEXT: retq
|
|
|
|
|
;
|
2019-01-17 04:53:23 +08:00
|
|
|
; SSE41-LABEL: v4i32:
|
2018-12-18 21:22:53 +08:00
|
|
|
; SSE41: # %bb.0:
|
2019-01-29 03:19:09 +08:00
|
|
|
; SSE41-NEXT: pcmpeqd %xmm2, %xmm2
|
|
|
|
|
; SSE41-NEXT: pxor %xmm1, %xmm2
|
|
|
|
|
; SSE41-NEXT: pminud %xmm2, %xmm0
|
|
|
|
|
; SSE41-NEXT: paddd %xmm1, %xmm0
|
2018-12-18 21:22:53 +08:00
|
|
|
; SSE41-NEXT: retq
|
|
|
|
|
;
|
2019-01-29 03:19:09 +08:00
|
|
|
; AVX1-LABEL: v4i32:
|
|
|
|
|
; AVX1: # %bb.0:
|
|
|
|
|
; AVX1-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
|
|
|
|
|
; AVX1-NEXT: vpxor %xmm2, %xmm1, %xmm2
|
|
|
|
|
; AVX1-NEXT: vpminud %xmm2, %xmm0, %xmm0
|
|
|
|
|
; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm0
|
|
|
|
|
; AVX1-NEXT: retq
|
|
|
|
|
;
|
|
|
|
|
; AVX2-LABEL: v4i32:
|
|
|
|
|
; AVX2: # %bb.0:
|
|
|
|
|
; AVX2-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
|
|
|
|
|
; AVX2-NEXT: vpxor %xmm2, %xmm1, %xmm2
|
|
|
|
|
; AVX2-NEXT: vpminud %xmm2, %xmm0, %xmm0
|
|
|
|
|
; AVX2-NEXT: vpaddd %xmm1, %xmm0, %xmm0
|
|
|
|
|
; AVX2-NEXT: retq
|
|
|
|
|
;
|
|
|
|
|
; AVX512-LABEL: v4i32:
|
|
|
|
|
; AVX512: # %bb.0:
|
|
|
|
|
; AVX512-NEXT: vmovdqa %xmm1, %xmm2
|
|
|
|
|
; AVX512-NEXT: vpternlogq $15, %xmm1, %xmm1, %xmm2
|
|
|
|
|
; AVX512-NEXT: vpminud %xmm2, %xmm0, %xmm0
|
|
|
|
|
; AVX512-NEXT: vpaddd %xmm1, %xmm0, %xmm0
|
|
|
|
|
; AVX512-NEXT: retq
|
2019-01-17 04:53:23 +08:00
|
|
|
%z = call <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32> %x, <4 x i32> %y)
|
|
|
|
|
ret <4 x i32> %z
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define <8 x i32> @v8i32(<8 x i32> %x, <8 x i32> %y) nounwind {
|
|
|
|
|
; SSE2-LABEL: v8i32:
|
|
|
|
|
; SSE2: # %bb.0:
|
2019-01-29 03:19:09 +08:00
|
|
|
; SSE2-NEXT: movdqa {{.*#+}} xmm4 = [2147483648,2147483648,2147483648,2147483648]
|
2019-03-24 21:55:54 +08:00
|
|
|
; SSE2-NEXT: paddd %xmm0, %xmm2
|
|
|
|
|
; SSE2-NEXT: pxor %xmm4, %xmm0
|
2019-01-29 03:19:09 +08:00
|
|
|
; SSE2-NEXT: movdqa %xmm2, %xmm5
|
2019-03-24 21:55:54 +08:00
|
|
|
; SSE2-NEXT: pxor %xmm4, %xmm5
|
|
|
|
|
; SSE2-NEXT: pcmpgtd %xmm5, %xmm0
|
|
|
|
|
; SSE2-NEXT: por %xmm2, %xmm0
|
|
|
|
|
; SSE2-NEXT: paddd %xmm1, %xmm3
|
|
|
|
|
; SSE2-NEXT: pxor %xmm4, %xmm1
|
|
|
|
|
; SSE2-NEXT: pxor %xmm3, %xmm4
|
|
|
|
|
; SSE2-NEXT: pcmpgtd %xmm4, %xmm1
|
|
|
|
|
; SSE2-NEXT: por %xmm3, %xmm1
|
2019-01-17 04:53:23 +08:00
|
|
|
; SSE2-NEXT: retq
|
|
|
|
|
;
|
|
|
|
|
; SSSE3-LABEL: v8i32:
|
|
|
|
|
; SSSE3: # %bb.0:
|
2019-01-29 03:19:09 +08:00
|
|
|
; SSSE3-NEXT: movdqa {{.*#+}} xmm4 = [2147483648,2147483648,2147483648,2147483648]
|
2019-03-24 21:55:54 +08:00
|
|
|
; SSSE3-NEXT: paddd %xmm0, %xmm2
|
|
|
|
|
; SSSE3-NEXT: pxor %xmm4, %xmm0
|
2019-01-29 03:19:09 +08:00
|
|
|
; SSSE3-NEXT: movdqa %xmm2, %xmm5
|
2019-03-24 21:55:54 +08:00
|
|
|
; SSSE3-NEXT: pxor %xmm4, %xmm5
|
|
|
|
|
; SSSE3-NEXT: pcmpgtd %xmm5, %xmm0
|
|
|
|
|
; SSSE3-NEXT: por %xmm2, %xmm0
|
|
|
|
|
; SSSE3-NEXT: paddd %xmm1, %xmm3
|
|
|
|
|
; SSSE3-NEXT: pxor %xmm4, %xmm1
|
|
|
|
|
; SSSE3-NEXT: pxor %xmm3, %xmm4
|
|
|
|
|
; SSSE3-NEXT: pcmpgtd %xmm4, %xmm1
|
|
|
|
|
; SSSE3-NEXT: por %xmm3, %xmm1
|
2019-01-17 04:53:23 +08:00
|
|
|
; SSSE3-NEXT: retq
|
|
|
|
|
;
|
|
|
|
|
; SSE41-LABEL: v8i32:
|
|
|
|
|
; SSE41: # %bb.0:
|
2019-01-29 03:19:09 +08:00
|
|
|
; SSE41-NEXT: pcmpeqd %xmm4, %xmm4
|
|
|
|
|
; SSE41-NEXT: movdqa %xmm2, %xmm5
|
|
|
|
|
; SSE41-NEXT: pxor %xmm4, %xmm5
|
|
|
|
|
; SSE41-NEXT: pminud %xmm5, %xmm0
|
|
|
|
|
; SSE41-NEXT: paddd %xmm2, %xmm0
|
|
|
|
|
; SSE41-NEXT: pxor %xmm3, %xmm4
|
|
|
|
|
; SSE41-NEXT: pminud %xmm4, %xmm1
|
|
|
|
|
; SSE41-NEXT: paddd %xmm3, %xmm1
|
2019-01-17 04:53:23 +08:00
|
|
|
; SSE41-NEXT: retq
|
|
|
|
|
;
|
|
|
|
|
; AVX1-LABEL: v8i32:
|
|
|
|
|
; AVX1: # %bb.0:
|
2019-01-29 03:19:09 +08:00
|
|
|
; AVX1-NEXT: vxorps %xmm2, %xmm2, %xmm2
|
|
|
|
|
; AVX1-NEXT: vcmptrueps %ymm2, %ymm2, %ymm2
|
|
|
|
|
; AVX1-NEXT: vxorps %ymm2, %ymm1, %ymm2
|
|
|
|
|
; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm3
|
|
|
|
|
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm4
|
|
|
|
|
; AVX1-NEXT: vpminud %xmm3, %xmm4, %xmm3
|
|
|
|
|
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm4
|
|
|
|
|
; AVX1-NEXT: vpaddd %xmm4, %xmm3, %xmm3
|
|
|
|
|
; AVX1-NEXT: vpminud %xmm2, %xmm0, %xmm0
|
|
|
|
|
; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm0
|
|
|
|
|
; AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm0, %ymm0
|
2019-01-17 04:53:23 +08:00
|
|
|
; AVX1-NEXT: retq
|
|
|
|
|
;
|
|
|
|
|
; AVX2-LABEL: v8i32:
|
|
|
|
|
; AVX2: # %bb.0:
|
2019-01-29 03:19:09 +08:00
|
|
|
; AVX2-NEXT: vpcmpeqd %ymm2, %ymm2, %ymm2
|
|
|
|
|
; AVX2-NEXT: vpxor %ymm2, %ymm1, %ymm2
|
|
|
|
|
; AVX2-NEXT: vpminud %ymm2, %ymm0, %ymm0
|
|
|
|
|
; AVX2-NEXT: vpaddd %ymm1, %ymm0, %ymm0
|
2019-01-17 04:53:23 +08:00
|
|
|
; AVX2-NEXT: retq
|
|
|
|
|
;
|
|
|
|
|
; AVX512-LABEL: v8i32:
|
|
|
|
|
; AVX512: # %bb.0:
|
2019-01-29 03:19:09 +08:00
|
|
|
; AVX512-NEXT: vmovdqa %ymm1, %ymm2
|
|
|
|
|
; AVX512-NEXT: vpternlogq $15, %ymm1, %ymm1, %ymm2
|
|
|
|
|
; AVX512-NEXT: vpminud %ymm2, %ymm0, %ymm0
|
|
|
|
|
; AVX512-NEXT: vpaddd %ymm1, %ymm0, %ymm0
|
2019-01-17 04:53:23 +08:00
|
|
|
; AVX512-NEXT: retq
|
|
|
|
|
%z = call <8 x i32> @llvm.uadd.sat.v8i32(<8 x i32> %x, <8 x i32> %y)
|
|
|
|
|
ret <8 x i32> %z
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define <16 x i32> @v16i32(<16 x i32> %x, <16 x i32> %y) nounwind {
|
|
|
|
|
; SSE2-LABEL: v16i32:
|
|
|
|
|
; SSE2: # %bb.0:
|
2019-03-24 21:55:54 +08:00
|
|
|
; SSE2-NEXT: movdqa {{.*#+}} xmm8 = [2147483648,2147483648,2147483648,2147483648]
|
|
|
|
|
; SSE2-NEXT: paddd %xmm0, %xmm4
|
|
|
|
|
; SSE2-NEXT: pxor %xmm8, %xmm0
|
|
|
|
|
; SSE2-NEXT: movdqa %xmm4, %xmm9
|
|
|
|
|
; SSE2-NEXT: pxor %xmm8, %xmm9
|
|
|
|
|
; SSE2-NEXT: pcmpgtd %xmm9, %xmm0
|
|
|
|
|
; SSE2-NEXT: por %xmm4, %xmm0
|
|
|
|
|
; SSE2-NEXT: paddd %xmm1, %xmm5
|
|
|
|
|
; SSE2-NEXT: pxor %xmm8, %xmm1
|
2019-01-29 03:19:09 +08:00
|
|
|
; SSE2-NEXT: movdqa %xmm5, %xmm4
|
2019-03-24 21:55:54 +08:00
|
|
|
; SSE2-NEXT: pxor %xmm8, %xmm4
|
|
|
|
|
; SSE2-NEXT: pcmpgtd %xmm4, %xmm1
|
|
|
|
|
; SSE2-NEXT: por %xmm5, %xmm1
|
|
|
|
|
; SSE2-NEXT: paddd %xmm2, %xmm6
|
|
|
|
|
; SSE2-NEXT: pxor %xmm8, %xmm2
|
2019-01-29 03:19:09 +08:00
|
|
|
; SSE2-NEXT: movdqa %xmm6, %xmm4
|
2019-03-24 21:55:54 +08:00
|
|
|
; SSE2-NEXT: pxor %xmm8, %xmm4
|
|
|
|
|
; SSE2-NEXT: pcmpgtd %xmm4, %xmm2
|
|
|
|
|
; SSE2-NEXT: por %xmm6, %xmm2
|
|
|
|
|
; SSE2-NEXT: paddd %xmm3, %xmm7
|
|
|
|
|
; SSE2-NEXT: pxor %xmm8, %xmm3
|
2019-01-29 03:19:09 +08:00
|
|
|
; SSE2-NEXT: pxor %xmm7, %xmm8
|
2019-03-24 21:55:54 +08:00
|
|
|
; SSE2-NEXT: pcmpgtd %xmm8, %xmm3
|
|
|
|
|
; SSE2-NEXT: por %xmm7, %xmm3
|
2019-01-17 04:53:23 +08:00
|
|
|
; SSE2-NEXT: retq
|
|
|
|
|
;
|
|
|
|
|
; SSSE3-LABEL: v16i32:
|
|
|
|
|
; SSSE3: # %bb.0:
|
2019-03-24 21:55:54 +08:00
|
|
|
; SSSE3-NEXT: movdqa {{.*#+}} xmm8 = [2147483648,2147483648,2147483648,2147483648]
|
|
|
|
|
; SSSE3-NEXT: paddd %xmm0, %xmm4
|
|
|
|
|
; SSSE3-NEXT: pxor %xmm8, %xmm0
|
|
|
|
|
; SSSE3-NEXT: movdqa %xmm4, %xmm9
|
|
|
|
|
; SSSE3-NEXT: pxor %xmm8, %xmm9
|
|
|
|
|
; SSSE3-NEXT: pcmpgtd %xmm9, %xmm0
|
|
|
|
|
; SSSE3-NEXT: por %xmm4, %xmm0
|
|
|
|
|
; SSSE3-NEXT: paddd %xmm1, %xmm5
|
|
|
|
|
; SSSE3-NEXT: pxor %xmm8, %xmm1
|
2019-01-29 03:19:09 +08:00
|
|
|
; SSSE3-NEXT: movdqa %xmm5, %xmm4
|
2019-03-24 21:55:54 +08:00
|
|
|
; SSSE3-NEXT: pxor %xmm8, %xmm4
|
|
|
|
|
; SSSE3-NEXT: pcmpgtd %xmm4, %xmm1
|
|
|
|
|
; SSSE3-NEXT: por %xmm5, %xmm1
|
|
|
|
|
; SSSE3-NEXT: paddd %xmm2, %xmm6
|
|
|
|
|
; SSSE3-NEXT: pxor %xmm8, %xmm2
|
2019-01-29 03:19:09 +08:00
|
|
|
; SSSE3-NEXT: movdqa %xmm6, %xmm4
|
2019-03-24 21:55:54 +08:00
|
|
|
; SSSE3-NEXT: pxor %xmm8, %xmm4
|
|
|
|
|
; SSSE3-NEXT: pcmpgtd %xmm4, %xmm2
|
|
|
|
|
; SSSE3-NEXT: por %xmm6, %xmm2
|
|
|
|
|
; SSSE3-NEXT: paddd %xmm3, %xmm7
|
|
|
|
|
; SSSE3-NEXT: pxor %xmm8, %xmm3
|
2019-01-29 03:19:09 +08:00
|
|
|
; SSSE3-NEXT: pxor %xmm7, %xmm8
|
2019-03-24 21:55:54 +08:00
|
|
|
; SSSE3-NEXT: pcmpgtd %xmm8, %xmm3
|
|
|
|
|
; SSSE3-NEXT: por %xmm7, %xmm3
|
2019-01-17 04:53:23 +08:00
|
|
|
; SSSE3-NEXT: retq
|
|
|
|
|
;
|
|
|
|
|
; SSE41-LABEL: v16i32:
|
|
|
|
|
; SSE41: # %bb.0:
|
2019-01-29 03:19:09 +08:00
|
|
|
; SSE41-NEXT: pcmpeqd %xmm8, %xmm8
|
|
|
|
|
; SSE41-NEXT: movdqa %xmm4, %xmm9
|
|
|
|
|
; SSE41-NEXT: pxor %xmm8, %xmm9
|
|
|
|
|
; SSE41-NEXT: pminud %xmm9, %xmm0
|
|
|
|
|
; SSE41-NEXT: paddd %xmm4, %xmm0
|
|
|
|
|
; SSE41-NEXT: movdqa %xmm5, %xmm4
|
|
|
|
|
; SSE41-NEXT: pxor %xmm8, %xmm4
|
|
|
|
|
; SSE41-NEXT: pminud %xmm4, %xmm1
|
|
|
|
|
; SSE41-NEXT: paddd %xmm5, %xmm1
|
|
|
|
|
; SSE41-NEXT: movdqa %xmm6, %xmm4
|
|
|
|
|
; SSE41-NEXT: pxor %xmm8, %xmm4
|
|
|
|
|
; SSE41-NEXT: pminud %xmm4, %xmm2
|
|
|
|
|
; SSE41-NEXT: paddd %xmm6, %xmm2
|
|
|
|
|
; SSE41-NEXT: pxor %xmm7, %xmm8
|
|
|
|
|
; SSE41-NEXT: pminud %xmm8, %xmm3
|
|
|
|
|
; SSE41-NEXT: paddd %xmm7, %xmm3
|
2019-01-17 04:53:23 +08:00
|
|
|
; SSE41-NEXT: retq
|
|
|
|
|
;
|
|
|
|
|
; AVX1-LABEL: v16i32:
|
|
|
|
|
; AVX1: # %bb.0:
|
2019-01-29 03:19:09 +08:00
|
|
|
; AVX1-NEXT: vxorps %xmm4, %xmm4, %xmm4
|
|
|
|
|
; AVX1-NEXT: vcmptrueps %ymm4, %ymm4, %ymm4
|
|
|
|
|
; AVX1-NEXT: vxorps %ymm4, %ymm2, %ymm5
|
|
|
|
|
; AVX1-NEXT: vextractf128 $1, %ymm5, %xmm6
|
|
|
|
|
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm7
|
|
|
|
|
; AVX1-NEXT: vpminud %xmm6, %xmm7, %xmm6
|
|
|
|
|
; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm7
|
|
|
|
|
; AVX1-NEXT: vpaddd %xmm7, %xmm6, %xmm6
|
|
|
|
|
; AVX1-NEXT: vpminud %xmm5, %xmm0, %xmm0
|
|
|
|
|
; AVX1-NEXT: vpaddd %xmm2, %xmm0, %xmm0
|
|
|
|
|
; AVX1-NEXT: vinsertf128 $1, %xmm6, %ymm0, %ymm0
|
|
|
|
|
; AVX1-NEXT: vxorps %ymm4, %ymm3, %ymm2
|
2019-01-17 04:53:23 +08:00
|
|
|
; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm4
|
2019-01-29 03:19:09 +08:00
|
|
|
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm5
|
|
|
|
|
; AVX1-NEXT: vpminud %xmm4, %xmm5, %xmm4
|
|
|
|
|
; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm5
|
|
|
|
|
; AVX1-NEXT: vpaddd %xmm5, %xmm4, %xmm4
|
|
|
|
|
; AVX1-NEXT: vpminud %xmm2, %xmm1, %xmm1
|
|
|
|
|
; AVX1-NEXT: vpaddd %xmm3, %xmm1, %xmm1
|
|
|
|
|
; AVX1-NEXT: vinsertf128 $1, %xmm4, %ymm1, %ymm1
|
2019-01-17 04:53:23 +08:00
|
|
|
; AVX1-NEXT: retq
|
|
|
|
|
;
|
|
|
|
|
; AVX2-LABEL: v16i32:
|
|
|
|
|
; AVX2: # %bb.0:
|
2019-01-29 03:19:09 +08:00
|
|
|
; AVX2-NEXT: vpcmpeqd %ymm4, %ymm4, %ymm4
|
|
|
|
|
; AVX2-NEXT: vpxor %ymm4, %ymm2, %ymm5
|
|
|
|
|
; AVX2-NEXT: vpminud %ymm5, %ymm0, %ymm0
|
|
|
|
|
; AVX2-NEXT: vpaddd %ymm2, %ymm0, %ymm0
|
|
|
|
|
; AVX2-NEXT: vpxor %ymm4, %ymm3, %ymm2
|
|
|
|
|
; AVX2-NEXT: vpminud %ymm2, %ymm1, %ymm1
|
|
|
|
|
; AVX2-NEXT: vpaddd %ymm3, %ymm1, %ymm1
|
2019-01-17 04:53:23 +08:00
|
|
|
; AVX2-NEXT: retq
|
|
|
|
|
;
|
|
|
|
|
; AVX512-LABEL: v16i32:
|
|
|
|
|
; AVX512: # %bb.0:
|
2019-01-29 03:19:09 +08:00
|
|
|
; AVX512-NEXT: vmovdqa64 %zmm1, %zmm2
|
|
|
|
|
; AVX512-NEXT: vpternlogq $15, %zmm1, %zmm1, %zmm2
|
|
|
|
|
; AVX512-NEXT: vpminud %zmm2, %zmm0, %zmm0
|
|
|
|
|
; AVX512-NEXT: vpaddd %zmm1, %zmm0, %zmm0
|
2019-01-17 04:53:23 +08:00
|
|
|
; AVX512-NEXT: retq
|
|
|
|
|
%z = call <16 x i32> @llvm.uadd.sat.v16i32(<16 x i32> %x, <16 x i32> %y)
|
|
|
|
|
ret <16 x i32> %z
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define <2 x i64> @v2i64(<2 x i64> %x, <2 x i64> %y) nounwind {
|
|
|
|
|
; SSE2-LABEL: v2i64:
|
|
|
|
|
; SSE2: # %bb.0:
|
2019-01-29 03:19:09 +08:00
|
|
|
; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [9223372039002259456,9223372039002259456]
|
2019-03-24 21:55:54 +08:00
|
|
|
; SSE2-NEXT: paddq %xmm0, %xmm1
|
|
|
|
|
; SSE2-NEXT: pxor %xmm2, %xmm0
|
|
|
|
|
; SSE2-NEXT: pxor %xmm1, %xmm2
|
|
|
|
|
; SSE2-NEXT: movdqa %xmm0, %xmm3
|
|
|
|
|
; SSE2-NEXT: pcmpgtd %xmm2, %xmm3
|
|
|
|
|
; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm3[0,0,2,2]
|
|
|
|
|
; SSE2-NEXT: pcmpeqd %xmm0, %xmm2
|
|
|
|
|
; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
|
|
|
|
|
; SSE2-NEXT: pand %xmm4, %xmm2
|
|
|
|
|
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm3[1,1,3,3]
|
|
|
|
|
; SSE2-NEXT: por %xmm1, %xmm0
|
|
|
|
|
; SSE2-NEXT: por %xmm2, %xmm0
|
2019-01-17 04:53:23 +08:00
|
|
|
; SSE2-NEXT: retq
|
|
|
|
|
;
|
|
|
|
|
; SSSE3-LABEL: v2i64:
|
|
|
|
|
; SSSE3: # %bb.0:
|
2019-01-29 03:19:09 +08:00
|
|
|
; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [9223372039002259456,9223372039002259456]
|
2019-03-24 21:55:54 +08:00
|
|
|
; SSSE3-NEXT: paddq %xmm0, %xmm1
|
|
|
|
|
; SSSE3-NEXT: pxor %xmm2, %xmm0
|
|
|
|
|
; SSSE3-NEXT: pxor %xmm1, %xmm2
|
|
|
|
|
; SSSE3-NEXT: movdqa %xmm0, %xmm3
|
|
|
|
|
; SSSE3-NEXT: pcmpgtd %xmm2, %xmm3
|
|
|
|
|
; SSSE3-NEXT: pshufd {{.*#+}} xmm4 = xmm3[0,0,2,2]
|
|
|
|
|
; SSSE3-NEXT: pcmpeqd %xmm0, %xmm2
|
|
|
|
|
; SSSE3-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
|
|
|
|
|
; SSSE3-NEXT: pand %xmm4, %xmm2
|
|
|
|
|
; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm3[1,1,3,3]
|
|
|
|
|
; SSSE3-NEXT: por %xmm1, %xmm0
|
|
|
|
|
; SSSE3-NEXT: por %xmm2, %xmm0
|
2019-01-17 04:53:23 +08:00
|
|
|
; SSSE3-NEXT: retq
|
|
|
|
|
;
|
|
|
|
|
; SSE41-LABEL: v2i64:
|
|
|
|
|
; SSE41: # %bb.0:
|
2019-03-24 21:55:54 +08:00
|
|
|
; SSE41-NEXT: movdqa {{.*#+}} xmm2 = [9223372039002259456,9223372039002259456]
|
|
|
|
|
; SSE41-NEXT: paddq %xmm0, %xmm1
|
|
|
|
|
; SSE41-NEXT: movdqa %xmm0, %xmm3
|
|
|
|
|
; SSE41-NEXT: pxor %xmm2, %xmm3
|
|
|
|
|
; SSE41-NEXT: pxor %xmm1, %xmm2
|
2019-01-29 03:19:09 +08:00
|
|
|
; SSE41-NEXT: movdqa %xmm3, %xmm0
|
2019-03-28 03:54:41 +08:00
|
|
|
; SSE41-NEXT: pcmpgtd %xmm2, %xmm0
|
|
|
|
|
; SSE41-NEXT: pshufd {{.*#+}} xmm4 = xmm0[0,0,2,2]
|
|
|
|
|
; SSE41-NEXT: pcmpeqd %xmm3, %xmm2
|
|
|
|
|
; SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
|
|
|
|
|
; SSE41-NEXT: pand %xmm4, %xmm2
|
|
|
|
|
; SSE41-NEXT: por %xmm2, %xmm0
|
2019-03-24 21:55:54 +08:00
|
|
|
; SSE41-NEXT: pcmpeqd %xmm2, %xmm2
|
|
|
|
|
; SSE41-NEXT: blendvpd %xmm0, %xmm2, %xmm1
|
|
|
|
|
; SSE41-NEXT: movapd %xmm1, %xmm0
|
2019-01-17 04:53:23 +08:00
|
|
|
; SSE41-NEXT: retq
|
|
|
|
|
;
|
2019-01-29 03:19:09 +08:00
|
|
|
; AVX1-LABEL: v2i64:
|
|
|
|
|
; AVX1: # %bb.0:
|
2019-03-24 21:55:54 +08:00
|
|
|
; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808]
|
|
|
|
|
; AVX1-NEXT: vpxor %xmm2, %xmm0, %xmm3
|
2019-01-29 03:19:09 +08:00
|
|
|
; AVX1-NEXT: vpaddq %xmm1, %xmm0, %xmm0
|
2019-03-24 21:55:54 +08:00
|
|
|
; AVX1-NEXT: vpxor %xmm2, %xmm0, %xmm1
|
|
|
|
|
; AVX1-NEXT: vpcmpgtq %xmm1, %xmm3, %xmm1
|
|
|
|
|
; AVX1-NEXT: vpor %xmm0, %xmm1, %xmm0
|
2019-01-29 03:19:09 +08:00
|
|
|
; AVX1-NEXT: retq
|
|
|
|
|
;
|
|
|
|
|
; AVX2-LABEL: v2i64:
|
|
|
|
|
; AVX2: # %bb.0:
|
2019-03-24 21:55:54 +08:00
|
|
|
; AVX2-NEXT: vmovdqa {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808]
|
|
|
|
|
; AVX2-NEXT: vpxor %xmm2, %xmm0, %xmm3
|
2019-01-29 03:19:09 +08:00
|
|
|
; AVX2-NEXT: vpaddq %xmm1, %xmm0, %xmm0
|
2019-03-24 21:55:54 +08:00
|
|
|
; AVX2-NEXT: vpxor %xmm2, %xmm0, %xmm1
|
|
|
|
|
; AVX2-NEXT: vpcmpgtq %xmm1, %xmm3, %xmm1
|
|
|
|
|
; AVX2-NEXT: vpor %xmm0, %xmm1, %xmm0
|
2019-01-29 03:19:09 +08:00
|
|
|
; AVX2-NEXT: retq
|
|
|
|
|
;
|
|
|
|
|
; AVX512-LABEL: v2i64:
|
|
|
|
|
; AVX512: # %bb.0:
|
|
|
|
|
; AVX512-NEXT: vmovdqa %xmm1, %xmm2
|
|
|
|
|
; AVX512-NEXT: vpternlogq $15, %xmm1, %xmm1, %xmm2
|
|
|
|
|
; AVX512-NEXT: vpminuq %xmm2, %xmm0, %xmm0
|
|
|
|
|
; AVX512-NEXT: vpaddq %xmm1, %xmm0, %xmm0
|
|
|
|
|
; AVX512-NEXT: retq
|
2019-01-17 04:53:23 +08:00
|
|
|
%z = call <2 x i64> @llvm.uadd.sat.v2i64(<2 x i64> %x, <2 x i64> %y)
|
|
|
|
|
ret <2 x i64> %z
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define <4 x i64> @v4i64(<4 x i64> %x, <4 x i64> %y) nounwind {
|
|
|
|
|
; SSE2-LABEL: v4i64:
|
|
|
|
|
; SSE2: # %bb.0:
|
2019-03-24 21:55:54 +08:00
|
|
|
; SSE2-NEXT: movdqa {{.*#+}} xmm4 = [9223372039002259456,9223372039002259456]
|
|
|
|
|
; SSE2-NEXT: paddq %xmm0, %xmm2
|
|
|
|
|
; SSE2-NEXT: pxor %xmm4, %xmm0
|
|
|
|
|
; SSE2-NEXT: movdqa %xmm2, %xmm5
|
|
|
|
|
; SSE2-NEXT: pxor %xmm4, %xmm5
|
2019-01-29 03:19:09 +08:00
|
|
|
; SSE2-NEXT: movdqa %xmm0, %xmm6
|
2019-03-24 21:55:54 +08:00
|
|
|
; SSE2-NEXT: pcmpgtd %xmm5, %xmm6
|
|
|
|
|
; SSE2-NEXT: pshufd {{.*#+}} xmm7 = xmm6[0,0,2,2]
|
|
|
|
|
; SSE2-NEXT: pcmpeqd %xmm0, %xmm5
|
2019-01-29 03:19:09 +08:00
|
|
|
; SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm5[1,1,3,3]
|
2019-03-24 21:55:54 +08:00
|
|
|
; SSE2-NEXT: pand %xmm7, %xmm5
|
|
|
|
|
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm6[1,1,3,3]
|
|
|
|
|
; SSE2-NEXT: por %xmm2, %xmm0
|
|
|
|
|
; SSE2-NEXT: por %xmm5, %xmm0
|
|
|
|
|
; SSE2-NEXT: paddq %xmm1, %xmm3
|
|
|
|
|
; SSE2-NEXT: pxor %xmm4, %xmm1
|
|
|
|
|
; SSE2-NEXT: pxor %xmm3, %xmm4
|
|
|
|
|
; SSE2-NEXT: movdqa %xmm1, %xmm2
|
|
|
|
|
; SSE2-NEXT: pcmpgtd %xmm4, %xmm2
|
|
|
|
|
; SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm2[0,0,2,2]
|
|
|
|
|
; SSE2-NEXT: pcmpeqd %xmm1, %xmm4
|
|
|
|
|
; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,1,3,3]
|
|
|
|
|
; SSE2-NEXT: pand %xmm5, %xmm4
|
|
|
|
|
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,1,3,3]
|
|
|
|
|
; SSE2-NEXT: por %xmm3, %xmm1
|
2019-01-29 03:19:09 +08:00
|
|
|
; SSE2-NEXT: por %xmm4, %xmm1
|
2019-01-17 04:53:23 +08:00
|
|
|
; SSE2-NEXT: retq
|
|
|
|
|
;
|
|
|
|
|
; SSSE3-LABEL: v4i64:
|
|
|
|
|
; SSSE3: # %bb.0:
|
2019-03-24 21:55:54 +08:00
|
|
|
; SSSE3-NEXT: movdqa {{.*#+}} xmm4 = [9223372039002259456,9223372039002259456]
|
|
|
|
|
; SSSE3-NEXT: paddq %xmm0, %xmm2
|
|
|
|
|
; SSSE3-NEXT: pxor %xmm4, %xmm0
|
|
|
|
|
; SSSE3-NEXT: movdqa %xmm2, %xmm5
|
|
|
|
|
; SSSE3-NEXT: pxor %xmm4, %xmm5
|
2019-01-29 03:19:09 +08:00
|
|
|
; SSSE3-NEXT: movdqa %xmm0, %xmm6
|
2019-03-24 21:55:54 +08:00
|
|
|
; SSSE3-NEXT: pcmpgtd %xmm5, %xmm6
|
|
|
|
|
; SSSE3-NEXT: pshufd {{.*#+}} xmm7 = xmm6[0,0,2,2]
|
|
|
|
|
; SSSE3-NEXT: pcmpeqd %xmm0, %xmm5
|
2019-01-29 03:19:09 +08:00
|
|
|
; SSSE3-NEXT: pshufd {{.*#+}} xmm5 = xmm5[1,1,3,3]
|
2019-03-24 21:55:54 +08:00
|
|
|
; SSSE3-NEXT: pand %xmm7, %xmm5
|
|
|
|
|
; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm6[1,1,3,3]
|
|
|
|
|
; SSSE3-NEXT: por %xmm2, %xmm0
|
|
|
|
|
; SSSE3-NEXT: por %xmm5, %xmm0
|
|
|
|
|
; SSSE3-NEXT: paddq %xmm1, %xmm3
|
|
|
|
|
; SSSE3-NEXT: pxor %xmm4, %xmm1
|
|
|
|
|
; SSSE3-NEXT: pxor %xmm3, %xmm4
|
|
|
|
|
; SSSE3-NEXT: movdqa %xmm1, %xmm2
|
|
|
|
|
; SSSE3-NEXT: pcmpgtd %xmm4, %xmm2
|
|
|
|
|
; SSSE3-NEXT: pshufd {{.*#+}} xmm5 = xmm2[0,0,2,2]
|
|
|
|
|
; SSSE3-NEXT: pcmpeqd %xmm1, %xmm4
|
|
|
|
|
; SSSE3-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,1,3,3]
|
|
|
|
|
; SSSE3-NEXT: pand %xmm5, %xmm4
|
|
|
|
|
; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm2[1,1,3,3]
|
|
|
|
|
; SSSE3-NEXT: por %xmm3, %xmm1
|
2019-01-29 03:19:09 +08:00
|
|
|
; SSSE3-NEXT: por %xmm4, %xmm1
|
2019-01-17 04:53:23 +08:00
|
|
|
; SSSE3-NEXT: retq
|
|
|
|
|
;
|
|
|
|
|
; SSE41-LABEL: v4i64:
|
|
|
|
|
; SSE41: # %bb.0:
|
2019-03-24 21:55:54 +08:00
|
|
|
; SSE41-NEXT: movdqa {{.*#+}} xmm4 = [9223372039002259456,9223372039002259456]
|
|
|
|
|
; SSE41-NEXT: paddq %xmm0, %xmm2
|
|
|
|
|
; SSE41-NEXT: movdqa %xmm0, %xmm5
|
2019-01-29 03:19:09 +08:00
|
|
|
; SSE41-NEXT: pxor %xmm4, %xmm5
|
|
|
|
|
; SSE41-NEXT: movdqa %xmm2, %xmm6
|
2019-03-24 21:55:54 +08:00
|
|
|
; SSE41-NEXT: pxor %xmm4, %xmm6
|
|
|
|
|
; SSE41-NEXT: movdqa %xmm5, %xmm0
|
2019-03-28 03:54:41 +08:00
|
|
|
; SSE41-NEXT: pcmpgtd %xmm6, %xmm0
|
|
|
|
|
; SSE41-NEXT: pshufd {{.*#+}} xmm7 = xmm0[0,0,2,2]
|
|
|
|
|
; SSE41-NEXT: pcmpeqd %xmm5, %xmm6
|
|
|
|
|
; SSE41-NEXT: pshufd {{.*#+}} xmm5 = xmm6[1,1,3,3]
|
|
|
|
|
; SSE41-NEXT: pand %xmm7, %xmm5
|
2019-03-24 21:55:54 +08:00
|
|
|
; SSE41-NEXT: por %xmm5, %xmm0
|
|
|
|
|
; SSE41-NEXT: pcmpeqd %xmm5, %xmm5
|
|
|
|
|
; SSE41-NEXT: blendvpd %xmm0, %xmm5, %xmm2
|
|
|
|
|
; SSE41-NEXT: paddq %xmm1, %xmm3
|
|
|
|
|
; SSE41-NEXT: pxor %xmm4, %xmm1
|
2019-01-29 03:19:09 +08:00
|
|
|
; SSE41-NEXT: pxor %xmm3, %xmm4
|
2019-03-24 21:55:54 +08:00
|
|
|
; SSE41-NEXT: movdqa %xmm1, %xmm6
|
2019-03-28 03:54:41 +08:00
|
|
|
; SSE41-NEXT: pcmpgtd %xmm4, %xmm6
|
|
|
|
|
; SSE41-NEXT: pshufd {{.*#+}} xmm7 = xmm6[0,0,2,2]
|
|
|
|
|
; SSE41-NEXT: pcmpeqd %xmm1, %xmm4
|
|
|
|
|
; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm4[1,1,3,3]
|
|
|
|
|
; SSE41-NEXT: pand %xmm7, %xmm0
|
|
|
|
|
; SSE41-NEXT: por %xmm6, %xmm0
|
2019-03-24 21:55:54 +08:00
|
|
|
; SSE41-NEXT: blendvpd %xmm0, %xmm5, %xmm3
|
|
|
|
|
; SSE41-NEXT: movapd %xmm2, %xmm0
|
|
|
|
|
; SSE41-NEXT: movapd %xmm3, %xmm1
|
2019-01-17 04:53:23 +08:00
|
|
|
; SSE41-NEXT: retq
|
|
|
|
|
;
|
|
|
|
|
; AVX1-LABEL: v4i64:
|
|
|
|
|
; AVX1: # %bb.0:
|
2019-01-29 03:19:09 +08:00
|
|
|
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
|
|
|
|
|
; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [9223372036854775808,9223372036854775808]
|
2019-06-07 21:17:46 +08:00
|
|
|
; AVX1-NEXT: vpxor %xmm3, %xmm2, %xmm4
|
|
|
|
|
; AVX1-NEXT: vxorps %xmm5, %xmm5, %xmm5
|
|
|
|
|
; AVX1-NEXT: vcmptrueps %ymm5, %ymm5, %ymm5
|
|
|
|
|
; AVX1-NEXT: vxorps %ymm5, %ymm1, %ymm5
|
|
|
|
|
; AVX1-NEXT: vextractf128 $1, %ymm5, %xmm6
|
|
|
|
|
; AVX1-NEXT: vpxor %xmm3, %xmm6, %xmm7
|
|
|
|
|
; AVX1-NEXT: vpcmpgtq %xmm4, %xmm7, %xmm4
|
|
|
|
|
; AVX1-NEXT: vblendvpd %xmm4, %xmm2, %xmm6, %xmm2
|
|
|
|
|
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm4
|
|
|
|
|
; AVX1-NEXT: vpaddq %xmm4, %xmm2, %xmm2
|
|
|
|
|
; AVX1-NEXT: vpxor %xmm3, %xmm0, %xmm4
|
|
|
|
|
; AVX1-NEXT: vxorps %xmm3, %xmm5, %xmm3
|
|
|
|
|
; AVX1-NEXT: vpcmpgtq %xmm4, %xmm3, %xmm3
|
|
|
|
|
; AVX1-NEXT: vblendvpd %xmm3, %xmm0, %xmm5, %xmm0
|
2019-01-29 03:19:09 +08:00
|
|
|
; AVX1-NEXT: vpaddq %xmm1, %xmm0, %xmm0
|
2019-01-17 04:53:23 +08:00
|
|
|
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
|
|
|
|
|
; AVX1-NEXT: retq
|
|
|
|
|
;
|
|
|
|
|
; AVX2-LABEL: v4i64:
|
|
|
|
|
; AVX2: # %bb.0:
|
2019-01-29 03:19:09 +08:00
|
|
|
; AVX2-NEXT: vpbroadcastq {{.*#+}} ymm2 = [9223372036854775808,9223372036854775808,9223372036854775808,9223372036854775808]
|
|
|
|
|
; AVX2-NEXT: vpxor %ymm2, %ymm0, %ymm2
|
|
|
|
|
; AVX2-NEXT: vpbroadcastq {{.*#+}} ymm3 = [9223372036854775807,9223372036854775807,9223372036854775807,9223372036854775807]
|
|
|
|
|
; AVX2-NEXT: vpxor %ymm3, %ymm1, %ymm3
|
|
|
|
|
; AVX2-NEXT: vpcmpgtq %ymm2, %ymm3, %ymm2
|
|
|
|
|
; AVX2-NEXT: vpcmpeqd %ymm3, %ymm3, %ymm3
|
|
|
|
|
; AVX2-NEXT: vpxor %ymm3, %ymm1, %ymm3
|
|
|
|
|
; AVX2-NEXT: vblendvpd %ymm2, %ymm0, %ymm3, %ymm0
|
|
|
|
|
; AVX2-NEXT: vpaddq %ymm1, %ymm0, %ymm0
|
2019-01-17 04:53:23 +08:00
|
|
|
; AVX2-NEXT: retq
|
|
|
|
|
;
|
|
|
|
|
; AVX512-LABEL: v4i64:
|
|
|
|
|
; AVX512: # %bb.0:
|
2019-01-29 03:19:09 +08:00
|
|
|
; AVX512-NEXT: vmovdqa %ymm1, %ymm2
|
|
|
|
|
; AVX512-NEXT: vpternlogq $15, %ymm1, %ymm1, %ymm2
|
|
|
|
|
; AVX512-NEXT: vpminuq %ymm2, %ymm0, %ymm0
|
|
|
|
|
; AVX512-NEXT: vpaddq %ymm1, %ymm0, %ymm0
|
2019-01-17 04:53:23 +08:00
|
|
|
; AVX512-NEXT: retq
|
|
|
|
|
%z = call <4 x i64> @llvm.uadd.sat.v4i64(<4 x i64> %x, <4 x i64> %y)
|
|
|
|
|
ret <4 x i64> %z
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define <8 x i64> @v8i64(<8 x i64> %x, <8 x i64> %y) nounwind {
|
|
|
|
|
; SSE2-LABEL: v8i64:
|
|
|
|
|
; SSE2: # %bb.0:
|
2019-01-29 03:19:09 +08:00
|
|
|
; SSE2-NEXT: movdqa {{.*#+}} xmm8 = [9223372039002259456,9223372039002259456]
|
2019-03-24 21:55:54 +08:00
|
|
|
; SSE2-NEXT: paddq %xmm0, %xmm4
|
|
|
|
|
; SSE2-NEXT: pxor %xmm8, %xmm0
|
|
|
|
|
; SSE2-NEXT: movdqa %xmm4, %xmm9
|
|
|
|
|
; SSE2-NEXT: pxor %xmm8, %xmm9
|
2019-01-29 03:19:09 +08:00
|
|
|
; SSE2-NEXT: movdqa %xmm0, %xmm10
|
2019-03-24 21:55:54 +08:00
|
|
|
; SSE2-NEXT: pcmpgtd %xmm9, %xmm10
|
|
|
|
|
; SSE2-NEXT: pshufd {{.*#+}} xmm11 = xmm10[0,0,2,2]
|
|
|
|
|
; SSE2-NEXT: pcmpeqd %xmm0, %xmm9
|
|
|
|
|
; SSE2-NEXT: pshufd {{.*#+}} xmm9 = xmm9[1,1,3,3]
|
|
|
|
|
; SSE2-NEXT: pand %xmm11, %xmm9
|
|
|
|
|
; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm10[1,1,3,3]
|
|
|
|
|
; SSE2-NEXT: por %xmm4, %xmm0
|
|
|
|
|
; SSE2-NEXT: por %xmm9, %xmm0
|
|
|
|
|
; SSE2-NEXT: paddq %xmm1, %xmm5
|
|
|
|
|
; SSE2-NEXT: pxor %xmm8, %xmm1
|
2019-01-29 03:19:09 +08:00
|
|
|
; SSE2-NEXT: movdqa %xmm5, %xmm4
|
|
|
|
|
; SSE2-NEXT: pxor %xmm8, %xmm4
|
2019-03-24 21:55:54 +08:00
|
|
|
; SSE2-NEXT: movdqa %xmm1, %xmm9
|
|
|
|
|
; SSE2-NEXT: pcmpgtd %xmm4, %xmm9
|
|
|
|
|
; SSE2-NEXT: pshufd {{.*#+}} xmm10 = xmm9[0,0,2,2]
|
|
|
|
|
; SSE2-NEXT: pcmpeqd %xmm1, %xmm4
|
|
|
|
|
; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,1,3,3]
|
|
|
|
|
; SSE2-NEXT: pand %xmm10, %xmm4
|
|
|
|
|
; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm9[1,1,3,3]
|
|
|
|
|
; SSE2-NEXT: por %xmm5, %xmm1
|
|
|
|
|
; SSE2-NEXT: por %xmm4, %xmm1
|
|
|
|
|
; SSE2-NEXT: paddq %xmm2, %xmm6
|
|
|
|
|
; SSE2-NEXT: pxor %xmm8, %xmm2
|
2019-01-29 03:19:09 +08:00
|
|
|
; SSE2-NEXT: movdqa %xmm6, %xmm4
|
2019-03-24 21:55:54 +08:00
|
|
|
; SSE2-NEXT: pxor %xmm8, %xmm4
|
|
|
|
|
; SSE2-NEXT: movdqa %xmm2, %xmm5
|
|
|
|
|
; SSE2-NEXT: pcmpgtd %xmm4, %xmm5
|
|
|
|
|
; SSE2-NEXT: pshufd {{.*#+}} xmm9 = xmm5[0,0,2,2]
|
|
|
|
|
; SSE2-NEXT: pcmpeqd %xmm2, %xmm4
|
|
|
|
|
; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,1,3,3]
|
|
|
|
|
; SSE2-NEXT: pand %xmm9, %xmm4
|
|
|
|
|
; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm5[1,1,3,3]
|
|
|
|
|
; SSE2-NEXT: por %xmm6, %xmm2
|
2019-01-29 03:19:09 +08:00
|
|
|
; SSE2-NEXT: por %xmm4, %xmm2
|
2019-03-24 21:55:54 +08:00
|
|
|
; SSE2-NEXT: paddq %xmm3, %xmm7
|
|
|
|
|
; SSE2-NEXT: pxor %xmm8, %xmm3
|
|
|
|
|
; SSE2-NEXT: pxor %xmm7, %xmm8
|
|
|
|
|
; SSE2-NEXT: movdqa %xmm3, %xmm4
|
2019-01-29 03:19:09 +08:00
|
|
|
; SSE2-NEXT: pcmpgtd %xmm8, %xmm4
|
|
|
|
|
; SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2]
|
2019-03-24 21:55:54 +08:00
|
|
|
; SSE2-NEXT: pcmpeqd %xmm3, %xmm8
|
|
|
|
|
; SSE2-NEXT: pshufd {{.*#+}} xmm6 = xmm8[1,1,3,3]
|
2019-01-29 03:19:09 +08:00
|
|
|
; SSE2-NEXT: pand %xmm5, %xmm6
|
2019-03-24 21:55:54 +08:00
|
|
|
; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm4[1,1,3,3]
|
|
|
|
|
; SSE2-NEXT: por %xmm7, %xmm3
|
|
|
|
|
; SSE2-NEXT: por %xmm6, %xmm3
|
2019-01-17 04:53:23 +08:00
|
|
|
; SSE2-NEXT: retq
|
|
|
|
|
;
|
|
|
|
|
; SSSE3-LABEL: v8i64:
|
|
|
|
|
; SSSE3: # %bb.0:
|
2019-01-29 03:19:09 +08:00
|
|
|
; SSSE3-NEXT: movdqa {{.*#+}} xmm8 = [9223372039002259456,9223372039002259456]
|
2019-03-24 21:55:54 +08:00
|
|
|
; SSSE3-NEXT: paddq %xmm0, %xmm4
|
|
|
|
|
; SSSE3-NEXT: pxor %xmm8, %xmm0
|
|
|
|
|
; SSSE3-NEXT: movdqa %xmm4, %xmm9
|
|
|
|
|
; SSSE3-NEXT: pxor %xmm8, %xmm9
|
2019-01-29 03:19:09 +08:00
|
|
|
; SSSE3-NEXT: movdqa %xmm0, %xmm10
|
2019-03-24 21:55:54 +08:00
|
|
|
; SSSE3-NEXT: pcmpgtd %xmm9, %xmm10
|
|
|
|
|
; SSSE3-NEXT: pshufd {{.*#+}} xmm11 = xmm10[0,0,2,2]
|
|
|
|
|
; SSSE3-NEXT: pcmpeqd %xmm0, %xmm9
|
|
|
|
|
; SSSE3-NEXT: pshufd {{.*#+}} xmm9 = xmm9[1,1,3,3]
|
|
|
|
|
; SSSE3-NEXT: pand %xmm11, %xmm9
|
|
|
|
|
; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm10[1,1,3,3]
|
|
|
|
|
; SSSE3-NEXT: por %xmm4, %xmm0
|
|
|
|
|
; SSSE3-NEXT: por %xmm9, %xmm0
|
|
|
|
|
; SSSE3-NEXT: paddq %xmm1, %xmm5
|
|
|
|
|
; SSSE3-NEXT: pxor %xmm8, %xmm1
|
2019-01-29 03:19:09 +08:00
|
|
|
; SSSE3-NEXT: movdqa %xmm5, %xmm4
|
|
|
|
|
; SSSE3-NEXT: pxor %xmm8, %xmm4
|
2019-03-24 21:55:54 +08:00
|
|
|
; SSSE3-NEXT: movdqa %xmm1, %xmm9
|
|
|
|
|
; SSSE3-NEXT: pcmpgtd %xmm4, %xmm9
|
|
|
|
|
; SSSE3-NEXT: pshufd {{.*#+}} xmm10 = xmm9[0,0,2,2]
|
|
|
|
|
; SSSE3-NEXT: pcmpeqd %xmm1, %xmm4
|
|
|
|
|
; SSSE3-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,1,3,3]
|
|
|
|
|
; SSSE3-NEXT: pand %xmm10, %xmm4
|
|
|
|
|
; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm9[1,1,3,3]
|
|
|
|
|
; SSSE3-NEXT: por %xmm5, %xmm1
|
|
|
|
|
; SSSE3-NEXT: por %xmm4, %xmm1
|
|
|
|
|
; SSSE3-NEXT: paddq %xmm2, %xmm6
|
|
|
|
|
; SSSE3-NEXT: pxor %xmm8, %xmm2
|
2019-01-29 03:19:09 +08:00
|
|
|
; SSSE3-NEXT: movdqa %xmm6, %xmm4
|
2019-03-24 21:55:54 +08:00
|
|
|
; SSSE3-NEXT: pxor %xmm8, %xmm4
|
|
|
|
|
; SSSE3-NEXT: movdqa %xmm2, %xmm5
|
|
|
|
|
; SSSE3-NEXT: pcmpgtd %xmm4, %xmm5
|
|
|
|
|
; SSSE3-NEXT: pshufd {{.*#+}} xmm9 = xmm5[0,0,2,2]
|
|
|
|
|
; SSSE3-NEXT: pcmpeqd %xmm2, %xmm4
|
|
|
|
|
; SSSE3-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,1,3,3]
|
|
|
|
|
; SSSE3-NEXT: pand %xmm9, %xmm4
|
|
|
|
|
; SSSE3-NEXT: pshufd {{.*#+}} xmm2 = xmm5[1,1,3,3]
|
|
|
|
|
; SSSE3-NEXT: por %xmm6, %xmm2
|
2019-01-29 03:19:09 +08:00
|
|
|
; SSSE3-NEXT: por %xmm4, %xmm2
|
2019-03-24 21:55:54 +08:00
|
|
|
; SSSE3-NEXT: paddq %xmm3, %xmm7
|
|
|
|
|
; SSSE3-NEXT: pxor %xmm8, %xmm3
|
|
|
|
|
; SSSE3-NEXT: pxor %xmm7, %xmm8
|
|
|
|
|
; SSSE3-NEXT: movdqa %xmm3, %xmm4
|
2019-01-29 03:19:09 +08:00
|
|
|
; SSSE3-NEXT: pcmpgtd %xmm8, %xmm4
|
|
|
|
|
; SSSE3-NEXT: pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2]
|
2019-03-24 21:55:54 +08:00
|
|
|
; SSSE3-NEXT: pcmpeqd %xmm3, %xmm8
|
|
|
|
|
; SSSE3-NEXT: pshufd {{.*#+}} xmm6 = xmm8[1,1,3,3]
|
2019-01-29 03:19:09 +08:00
|
|
|
; SSSE3-NEXT: pand %xmm5, %xmm6
|
2019-03-24 21:55:54 +08:00
|
|
|
; SSSE3-NEXT: pshufd {{.*#+}} xmm3 = xmm4[1,1,3,3]
|
|
|
|
|
; SSSE3-NEXT: por %xmm7, %xmm3
|
|
|
|
|
; SSSE3-NEXT: por %xmm6, %xmm3
|
2019-01-17 04:53:23 +08:00
|
|
|
; SSSE3-NEXT: retq
|
|
|
|
|
;
|
|
|
|
|
; SSE41-LABEL: v8i64:
|
|
|
|
|
; SSE41: # %bb.0:
|
2019-03-24 21:55:54 +08:00
|
|
|
; SSE41-NEXT: movdqa %xmm7, %xmm8
|
|
|
|
|
; SSE41-NEXT: movdqa %xmm6, %xmm10
|
|
|
|
|
; SSE41-NEXT: movdqa %xmm5, %xmm11
|
2019-03-28 03:54:41 +08:00
|
|
|
; SSE41-NEXT: movdqa %xmm4, %xmm12
|
2019-03-24 21:55:54 +08:00
|
|
|
; SSE41-NEXT: movdqa {{.*#+}} xmm7 = [9223372039002259456,9223372039002259456]
|
2019-03-28 03:54:41 +08:00
|
|
|
; SSE41-NEXT: paddq %xmm0, %xmm12
|
2019-03-24 21:55:54 +08:00
|
|
|
; SSE41-NEXT: movdqa %xmm0, %xmm6
|
|
|
|
|
; SSE41-NEXT: pxor %xmm7, %xmm6
|
2019-03-28 03:54:41 +08:00
|
|
|
; SSE41-NEXT: movdqa %xmm12, %xmm4
|
2019-03-24 21:55:54 +08:00
|
|
|
; SSE41-NEXT: pxor %xmm7, %xmm4
|
|
|
|
|
; SSE41-NEXT: movdqa %xmm6, %xmm0
|
2019-03-28 03:54:41 +08:00
|
|
|
; SSE41-NEXT: pcmpgtd %xmm4, %xmm0
|
|
|
|
|
; SSE41-NEXT: pshufd {{.*#+}} xmm5 = xmm0[0,0,2,2]
|
|
|
|
|
; SSE41-NEXT: pcmpeqd %xmm6, %xmm4
|
|
|
|
|
; SSE41-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,1,3,3]
|
|
|
|
|
; SSE41-NEXT: pand %xmm5, %xmm4
|
|
|
|
|
; SSE41-NEXT: por %xmm4, %xmm0
|
2019-03-24 21:55:54 +08:00
|
|
|
; SSE41-NEXT: pcmpeqd %xmm9, %xmm9
|
2019-03-28 03:54:41 +08:00
|
|
|
; SSE41-NEXT: blendvpd %xmm0, %xmm9, %xmm12
|
2019-03-24 21:55:54 +08:00
|
|
|
; SSE41-NEXT: paddq %xmm1, %xmm11
|
|
|
|
|
; SSE41-NEXT: pxor %xmm7, %xmm1
|
|
|
|
|
; SSE41-NEXT: movdqa %xmm11, %xmm0
|
|
|
|
|
; SSE41-NEXT: pxor %xmm7, %xmm0
|
2019-01-29 03:19:09 +08:00
|
|
|
; SSE41-NEXT: movdqa %xmm1, %xmm4
|
2019-03-28 03:54:41 +08:00
|
|
|
; SSE41-NEXT: pcmpgtd %xmm0, %xmm4
|
|
|
|
|
; SSE41-NEXT: pshufd {{.*#+}} xmm5 = xmm4[0,0,2,2]
|
|
|
|
|
; SSE41-NEXT: pcmpeqd %xmm1, %xmm0
|
|
|
|
|
; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
|
|
|
|
|
; SSE41-NEXT: pand %xmm5, %xmm0
|
|
|
|
|
; SSE41-NEXT: por %xmm4, %xmm0
|
2019-03-24 21:55:54 +08:00
|
|
|
; SSE41-NEXT: blendvpd %xmm0, %xmm9, %xmm11
|
|
|
|
|
; SSE41-NEXT: paddq %xmm2, %xmm10
|
|
|
|
|
; SSE41-NEXT: pxor %xmm7, %xmm2
|
|
|
|
|
; SSE41-NEXT: movdqa %xmm10, %xmm0
|
|
|
|
|
; SSE41-NEXT: pxor %xmm7, %xmm0
|
|
|
|
|
; SSE41-NEXT: movdqa %xmm2, %xmm1
|
2019-03-28 03:54:41 +08:00
|
|
|
; SSE41-NEXT: pcmpgtd %xmm0, %xmm1
|
|
|
|
|
; SSE41-NEXT: pshufd {{.*#+}} xmm4 = xmm1[0,0,2,2]
|
|
|
|
|
; SSE41-NEXT: pcmpeqd %xmm2, %xmm0
|
|
|
|
|
; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
|
|
|
|
|
; SSE41-NEXT: pand %xmm4, %xmm0
|
|
|
|
|
; SSE41-NEXT: por %xmm1, %xmm0
|
2019-03-24 21:55:54 +08:00
|
|
|
; SSE41-NEXT: blendvpd %xmm0, %xmm9, %xmm10
|
|
|
|
|
; SSE41-NEXT: paddq %xmm3, %xmm8
|
|
|
|
|
; SSE41-NEXT: pxor %xmm7, %xmm3
|
|
|
|
|
; SSE41-NEXT: pxor %xmm8, %xmm7
|
|
|
|
|
; SSE41-NEXT: movdqa %xmm3, %xmm1
|
2019-03-28 03:54:41 +08:00
|
|
|
; SSE41-NEXT: pcmpgtd %xmm7, %xmm1
|
|
|
|
|
; SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm1[0,0,2,2]
|
|
|
|
|
; SSE41-NEXT: pcmpeqd %xmm3, %xmm7
|
|
|
|
|
; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm7[1,1,3,3]
|
|
|
|
|
; SSE41-NEXT: pand %xmm2, %xmm0
|
|
|
|
|
; SSE41-NEXT: por %xmm1, %xmm0
|
2019-03-24 21:55:54 +08:00
|
|
|
; SSE41-NEXT: blendvpd %xmm0, %xmm9, %xmm8
|
2019-03-28 03:54:41 +08:00
|
|
|
; SSE41-NEXT: movapd %xmm12, %xmm0
|
2019-03-24 21:55:54 +08:00
|
|
|
; SSE41-NEXT: movapd %xmm11, %xmm1
|
|
|
|
|
; SSE41-NEXT: movapd %xmm10, %xmm2
|
|
|
|
|
; SSE41-NEXT: movapd %xmm8, %xmm3
|
2019-01-17 04:53:23 +08:00
|
|
|
; SSE41-NEXT: retq
|
|
|
|
|
;
|
|
|
|
|
; AVX1-LABEL: v8i64:
|
|
|
|
|
; AVX1: # %bb.0:
|
|
|
|
|
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm5
|
2019-01-29 03:19:09 +08:00
|
|
|
; AVX1-NEXT: vmovdqa {{.*#+}} xmm4 = [9223372036854775808,9223372036854775808]
|
2019-06-07 21:17:46 +08:00
|
|
|
; AVX1-NEXT: vpxor %xmm4, %xmm5, %xmm9
|
|
|
|
|
; AVX1-NEXT: vxorps %xmm7, %xmm7, %xmm7
|
|
|
|
|
; AVX1-NEXT: vcmptrueps %ymm7, %ymm7, %ymm10
|
|
|
|
|
; AVX1-NEXT: vxorps %ymm10, %ymm2, %ymm8
|
|
|
|
|
; AVX1-NEXT: vextractf128 $1, %ymm8, %xmm6
|
|
|
|
|
; AVX1-NEXT: vpxor %xmm4, %xmm6, %xmm7
|
|
|
|
|
; AVX1-NEXT: vpcmpgtq %xmm9, %xmm7, %xmm7
|
|
|
|
|
; AVX1-NEXT: vblendvpd %xmm7, %xmm5, %xmm6, %xmm5
|
2019-01-29 03:19:09 +08:00
|
|
|
; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm6
|
|
|
|
|
; AVX1-NEXT: vpaddq %xmm6, %xmm5, %xmm5
|
2019-06-07 21:17:46 +08:00
|
|
|
; AVX1-NEXT: vpxor %xmm4, %xmm0, %xmm6
|
|
|
|
|
; AVX1-NEXT: vxorps %xmm4, %xmm8, %xmm7
|
|
|
|
|
; AVX1-NEXT: vpcmpgtq %xmm6, %xmm7, %xmm6
|
|
|
|
|
; AVX1-NEXT: vblendvpd %xmm6, %xmm0, %xmm8, %xmm0
|
2019-01-29 03:19:09 +08:00
|
|
|
; AVX1-NEXT: vpaddq %xmm2, %xmm0, %xmm0
|
|
|
|
|
; AVX1-NEXT: vinsertf128 $1, %xmm5, %ymm0, %ymm0
|
|
|
|
|
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
|
2019-06-07 21:17:46 +08:00
|
|
|
; AVX1-NEXT: vpxor %xmm4, %xmm2, %xmm8
|
|
|
|
|
; AVX1-NEXT: vxorps %ymm10, %ymm3, %ymm6
|
|
|
|
|
; AVX1-NEXT: vextractf128 $1, %ymm6, %xmm7
|
|
|
|
|
; AVX1-NEXT: vpxor %xmm4, %xmm7, %xmm5
|
|
|
|
|
; AVX1-NEXT: vpcmpgtq %xmm8, %xmm5, %xmm5
|
|
|
|
|
; AVX1-NEXT: vblendvpd %xmm5, %xmm2, %xmm7, %xmm2
|
|
|
|
|
; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm5
|
|
|
|
|
; AVX1-NEXT: vpaddq %xmm5, %xmm2, %xmm2
|
|
|
|
|
; AVX1-NEXT: vpxor %xmm4, %xmm1, %xmm5
|
|
|
|
|
; AVX1-NEXT: vxorps %xmm4, %xmm6, %xmm4
|
|
|
|
|
; AVX1-NEXT: vpcmpgtq %xmm5, %xmm4, %xmm4
|
|
|
|
|
; AVX1-NEXT: vblendvpd %xmm4, %xmm1, %xmm6, %xmm1
|
2019-01-29 03:19:09 +08:00
|
|
|
; AVX1-NEXT: vpaddq %xmm3, %xmm1, %xmm1
|
2019-01-17 04:53:23 +08:00
|
|
|
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm1, %ymm1
|
|
|
|
|
; AVX1-NEXT: retq
|
|
|
|
|
;
|
|
|
|
|
; AVX2-LABEL: v8i64:
|
|
|
|
|
; AVX2: # %bb.0:
|
2019-01-29 03:19:09 +08:00
|
|
|
; AVX2-NEXT: vpbroadcastq {{.*#+}} ymm4 = [9223372036854775808,9223372036854775808,9223372036854775808,9223372036854775808]
|
|
|
|
|
; AVX2-NEXT: vpxor %ymm4, %ymm0, %ymm5
|
|
|
|
|
; AVX2-NEXT: vpbroadcastq {{.*#+}} ymm6 = [9223372036854775807,9223372036854775807,9223372036854775807,9223372036854775807]
|
|
|
|
|
; AVX2-NEXT: vpxor %ymm6, %ymm2, %ymm7
|
|
|
|
|
; AVX2-NEXT: vpcmpgtq %ymm5, %ymm7, %ymm5
|
|
|
|
|
; AVX2-NEXT: vpcmpeqd %ymm7, %ymm7, %ymm7
|
|
|
|
|
; AVX2-NEXT: vpxor %ymm7, %ymm2, %ymm8
|
|
|
|
|
; AVX2-NEXT: vblendvpd %ymm5, %ymm0, %ymm8, %ymm0
|
|
|
|
|
; AVX2-NEXT: vpaddq %ymm2, %ymm0, %ymm0
|
|
|
|
|
; AVX2-NEXT: vpxor %ymm4, %ymm1, %ymm2
|
|
|
|
|
; AVX2-NEXT: vpxor %ymm6, %ymm3, %ymm4
|
|
|
|
|
; AVX2-NEXT: vpcmpgtq %ymm2, %ymm4, %ymm2
|
|
|
|
|
; AVX2-NEXT: vpxor %ymm7, %ymm3, %ymm4
|
|
|
|
|
; AVX2-NEXT: vblendvpd %ymm2, %ymm1, %ymm4, %ymm1
|
|
|
|
|
; AVX2-NEXT: vpaddq %ymm3, %ymm1, %ymm1
|
2019-01-17 04:53:23 +08:00
|
|
|
; AVX2-NEXT: retq
|
|
|
|
|
;
|
|
|
|
|
; AVX512-LABEL: v8i64:
|
|
|
|
|
; AVX512: # %bb.0:
|
2019-01-29 03:19:09 +08:00
|
|
|
; AVX512-NEXT: vmovdqa64 %zmm1, %zmm2
|
|
|
|
|
; AVX512-NEXT: vpternlogq $15, %zmm1, %zmm1, %zmm2
|
|
|
|
|
; AVX512-NEXT: vpminuq %zmm2, %zmm0, %zmm0
|
|
|
|
|
; AVX512-NEXT: vpaddq %zmm1, %zmm0, %zmm0
|
2019-01-17 04:53:23 +08:00
|
|
|
; AVX512-NEXT: retq
|
|
|
|
|
%z = call <8 x i64> @llvm.uadd.sat.v8i64(<8 x i64> %x, <8 x i64> %y)
|
|
|
|
|
ret <8 x i64> %z
|
2018-12-18 21:22:53 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define <2 x i128> @v2i128(<2 x i128> %x, <2 x i128> %y) nounwind {
|
|
|
|
|
; SSE-LABEL: v2i128:
|
|
|
|
|
; SSE: # %bb.0:
|
|
|
|
|
; SSE-NEXT: movq %rdi, %rax
|
|
|
|
|
; SSE-NEXT: addq %r9, %rsi
|
|
|
|
|
; SSE-NEXT: adcq {{[0-9]+}}(%rsp), %rdx
|
|
|
|
|
; SSE-NEXT: movq $-1, %rdi
|
|
|
|
|
; SSE-NEXT: cmovbq %rdi, %rsi
|
|
|
|
|
; SSE-NEXT: cmovbq %rdi, %rdx
|
|
|
|
|
; SSE-NEXT: addq {{[0-9]+}}(%rsp), %rcx
|
|
|
|
|
; SSE-NEXT: adcq {{[0-9]+}}(%rsp), %r8
|
|
|
|
|
; SSE-NEXT: cmovbq %rdi, %r8
|
|
|
|
|
; SSE-NEXT: cmovbq %rdi, %rcx
|
|
|
|
|
; SSE-NEXT: movq %r8, 24(%rax)
|
|
|
|
|
; SSE-NEXT: movq %rcx, 16(%rax)
|
|
|
|
|
; SSE-NEXT: movq %rdx, 8(%rax)
|
|
|
|
|
; SSE-NEXT: movq %rsi, (%rax)
|
|
|
|
|
; SSE-NEXT: retq
|
|
|
|
|
;
|
|
|
|
|
; AVX-LABEL: v2i128:
|
|
|
|
|
; AVX: # %bb.0:
|
|
|
|
|
; AVX-NEXT: movq %rdi, %rax
|
|
|
|
|
; AVX-NEXT: addq %r9, %rsi
|
|
|
|
|
; AVX-NEXT: adcq {{[0-9]+}}(%rsp), %rdx
|
|
|
|
|
; AVX-NEXT: movq $-1, %rdi
|
|
|
|
|
; AVX-NEXT: cmovbq %rdi, %rsi
|
|
|
|
|
; AVX-NEXT: cmovbq %rdi, %rdx
|
|
|
|
|
; AVX-NEXT: addq {{[0-9]+}}(%rsp), %rcx
|
|
|
|
|
; AVX-NEXT: adcq {{[0-9]+}}(%rsp), %r8
|
|
|
|
|
; AVX-NEXT: cmovbq %rdi, %r8
|
|
|
|
|
; AVX-NEXT: cmovbq %rdi, %rcx
|
|
|
|
|
; AVX-NEXT: movq %r8, 24(%rax)
|
|
|
|
|
; AVX-NEXT: movq %rcx, 16(%rax)
|
|
|
|
|
; AVX-NEXT: movq %rdx, 8(%rax)
|
|
|
|
|
; AVX-NEXT: movq %rsi, (%rax)
|
|
|
|
|
; AVX-NEXT: retq
|
|
|
|
|
%z = call <2 x i128> @llvm.uadd.sat.v2i128(<2 x i128> %x, <2 x i128> %y)
|
|
|
|
|
ret <2 x i128> %z
|
|
|
|
|
}
|