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llvm-project/llvm/test/CodeGen/X86/sse42-intrinsics-fast-isel-...

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[X86][SSE42] Added fast-isel tests to sync with clang/test/CodeGen/sse42-builtins.c llvm-svn: 269929
2016-05-18 22:28:54 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
[X86][SSE] Cleanup SSE4A/SSE41/SSE42 intrinsics tests Ensure we cover 32/64-bit targets for SSE/AVX/AVX512 cases as necessary Added some missing encoding checks to SSE4A tests llvm-svn: 333828
2018-06-03 01:33:26 +08:00
; RUN: llc < %s -fast-isel -mtriple=x86_64-unknown-unknown -mattr=+sse4.2 | FileCheck %s --check-prefixes=CHECK,SSE
; RUN: llc < %s -fast-isel -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=CHECK,AVX,AVX1
[X86][SSE4] Tweak rL333828 sse41/sse42 cleanup to recover SKX/EVEX2VEX testing Just testing for avx512f was missing the tests for EVEX TO VEX Compression encoding etc. llvm-svn: 333830
2018-06-03 02:01:09 +08:00
; RUN: llc < %s -fast-isel -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512bw,+avx512dq,+avx512vl | FileCheck %s --check-prefixes=CHECK,AVX,AVX512
[X86][SSE42] Added fast-isel tests to sync with clang/test/CodeGen/sse42-builtins.c llvm-svn: 269929
2016-05-18 22:28:54 +08:00
; NOTE: This should use IR equivalent to what is generated by clang/test/CodeGen/sse42-builtins.c
define i64 @test_mm_crc64_u8(i64 %a0, i8 %a1) nounwind{
[X86][SSE] Cleanup SSE4A/SSE41/SSE42 intrinsics tests Ensure we cover 32/64-bit targets for SSE/AVX/AVX512 cases as necessary Added some missing encoding checks to SSE4A tests llvm-svn: 333828
2018-06-03 01:33:26 +08:00
; CHECK-LABEL: test_mm_crc64_u8:
; CHECK: # %bb.0:
; CHECK-NEXT: crc32b %sil, %edi
; CHECK-NEXT: movl %edi, %eax
; CHECK-NEXT: retq
[X86][SSE42] Added fast-isel tests to sync with clang/test/CodeGen/sse42-builtins.c llvm-svn: 269929
2016-05-18 22:28:54 +08:00
%res = call i64 @llvm.x86.sse42.crc32.64.8(i64 %a0, i8 %a1)
ret i64 %res
}
declare i64 @llvm.x86.sse42.crc32.64.8(i64, i8) nounwind readnone
define i64 @test_mm_crc64_u64(i64 %a0, i64 %a1) nounwind{
[X86][SSE] Cleanup SSE4A/SSE41/SSE42 intrinsics tests Ensure we cover 32/64-bit targets for SSE/AVX/AVX512 cases as necessary Added some missing encoding checks to SSE4A tests llvm-svn: 333828
2018-06-03 01:33:26 +08:00
; CHECK-LABEL: test_mm_crc64_u64:
; CHECK: # %bb.0:
; CHECK-NEXT: movq %rdi, %rax
[X86] Handle COPYs of physregs better (regalloc hints) Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
2018-09-20 02:59:08 +08:00
; CHECK-NEXT: crc32q %rsi, %rax
[X86][SSE] Cleanup SSE4A/SSE41/SSE42 intrinsics tests Ensure we cover 32/64-bit targets for SSE/AVX/AVX512 cases as necessary Added some missing encoding checks to SSE4A tests llvm-svn: 333828
2018-06-03 01:33:26 +08:00
; CHECK-NEXT: retq
[X86][SSE42] Added fast-isel tests to sync with clang/test/CodeGen/sse42-builtins.c llvm-svn: 269929
2016-05-18 22:28:54 +08:00
%res = call i64 @llvm.x86.sse42.crc32.64.64(i64 %a0, i64 %a1)
ret i64 %res
}
declare i64 @llvm.x86.sse42.crc32.64.64(i64, i64) nounwind readnone