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llvm-project/llvm/test/CodeGen/X86/dynamic-regmask.ll

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Fix line endings. NFCI. llvm-svn: 322940
2018-01-19 20:09:17 +08:00
; RUN: llc -mtriple=x86_64-pc-win32 -stop-after machine-sink %s -o %t.mir
; RUN: FileCheck %s < %t.mir
; RUN: llc %t.mir -mtriple=x86_64-pc-win32 -run-pass machine-sink
; Check that callee saved registers are printed in a format that can then be parsed.
declare x86_regcallcc i32 @callee(i32 %a0, i32 %b0, i32 %c0, i32 %d0, i32 %e0)
define i32 @caller(i32 %a0) nounwind {
%b1 = call x86_regcallcc i32 @callee(i32 %a0, i32 %a0, i32 %a0, i32 %a0, i32 %a0)
%b2 = add i32 %b1, %a0
ret i32 %b2
}
; CHECK: name: caller
[X86] Add phony registers for high halves of regs with low halves Add registers still missing after r328016 (D43353): - for bits 15-8 of SI, DI, BP, SP (*H), and R8-R15 (*BH), - for bits 31-16 of R8-R15 (*WH). Thanks to Craig Topper for pointing it out. llvm-svn: 336134
2018-07-03 03:05:09 +08:00
; CHECK: CALL64pcrel32 @callee, CustomRegMask($bh,$bl,$bp,$bph,$bpl,$bx,$ebp,$ebx,$esp,$hbp,$hbx,$hsp,$rbp,$rbx,$rsp,$sp,$sph,$spl,$r10,$r11,$r12,$r13,$r14,$r15,$xmm8,$xmm9,$xmm10,$xmm11,$xmm12,$xmm13,$xmm14,$xmm15,$r10b,$r11b,$r12b,$r13b,$r14b,$r15b,$r10bh,$r11bh,$r12bh,$r13bh,$r14bh,$r15bh,$r10d,$r11d,$r12d,$r13d,$r14d,$r15d,$r10w,$r11w,$r12w,$r13w,$r14w,$r15w,$r10wh,$r11wh,$r12wh,$r13wh,$r14wh,$r15wh), implicit $rsp, implicit $ssp, implicit $eax, implicit $ecx, implicit $edx, implicit $edi, implicit $esi, implicit-def $rsp, implicit-def $ssp, implicit-def $eax
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-02-01 06:04:26 +08:00
; CHECK: RET 0, $eax
Fix line endings. NFCI. llvm-svn: 322940
2018-01-19 20:09:17 +08:00
define x86_regcallcc {i32, i32, i32} @test_callee(i32 %a0, i32 %b0, i32 %c0, i32 %d0, i32 %e0) nounwind {
%b1 = mul i32 7, %e0
%b2 = udiv i32 5, %e0
%b3 = mul i32 7, %d0
%b4 = insertvalue {i32, i32, i32} undef, i32 %b1, 0
%b5 = insertvalue {i32, i32, i32} %b4, i32 %b2, 1
%b6 = insertvalue {i32, i32, i32} %b5, i32 %b3, 2
ret {i32, i32, i32} %b6
}
; CHECK: name: test_callee
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-02-01 06:04:26 +08:00
; CHECK: calleeSavedRegisters: [ '$rbx', '$rbp', '$rsp', '$r10', '$r11', '$r12',
; CHECK: '$r13', '$r14', '$r15', '$xmm8', '$xmm9', '$xmm10',
; CHECK: '$xmm11', '$xmm12', '$xmm13', '$xmm14', '$xmm15' ]
; CHECK: RET 0, $eax, $ecx, $edx