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llvm-project/llvm/test/MC/RISCV/rv64-relaxation.s

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[RISCV] Implement MC relaxations for compressed instructions. Summary: This patch implements relaxation for RISCV in the MC layer. The following relaxations are currently handled: 1) Relax C_BEQZ to BEQ and C_BNEZ to BNEZ in RISCV. 2) Relax and C_J $imm to JAL x0, $imm and CJAL to JAL ra, $imm. Reviewers: asb, llvm-commits, efriedma Reviewed By: asb Subscribers: shiva0217 Differential Revision: https://reviews.llvm.org/D43055 llvm-svn: 326626
2018-03-03 06:04:12 +08:00
# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+c < %s \
[test] llvm/test/: change llvm-objdump single-dash long options to double-dash options As announced here: http://lists.llvm.org/pipermail/llvm-dev/2019-April/131786.html Grouped option syntax (POSIX Utility Conventions) does not play well with -long-option A subsequent change will reject -long-option.
2020-03-16 07:17:52 +08:00
# RUN: | llvm-objdump -d -M no-aliases - | FileCheck --check-prefix=INSTR %s
[RISCV] Add WasForced parameter to MCAsmBackend::fixupNeedsRelaxationAdvanced For RISCV branch instructions, we need to preserve relocation types when linker relaxation enabled, so then linker could modify offset when the branch offsets changed. We preserve relocation types by define shouldForceRelocation. IsResolved return by evaluateFixup will always false when shouldForceRelocation return true. It will make RISCV MC Branch Relaxation always relax 16-bit branches to 32-bit form, even if the symbol actually could be resolved. To avoid 16-bit branches always relax to 32-bit form when linker relaxation enabled, we add a new parameter WasForced to indicate that the symbol actually couldn't be resolved and not forced by shouldForceRelocation return true. RISCVAsmBackend::fixupNeedsRelaxationAdvanced could relax branches with unresolved symbols by (!IsResolved && !WasForced). RISCV MC Branch Relaxation is needed because RISCV could perform 32-bit to 16-bit transformation in MC layer. Differential Revision: https://reviews.llvm.org/D46350 llvm-svn: 332696
2018-05-18 14:42:21 +08:00
# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+c,+relax < %s \
[test] llvm/test/: change llvm-objdump single-dash long options to double-dash options As announced here: http://lists.llvm.org/pipermail/llvm-dev/2019-April/131786.html Grouped option syntax (POSIX Utility Conventions) does not play well with -long-option A subsequent change will reject -long-option.
2020-03-16 07:17:52 +08:00
# RUN: | llvm-objdump -d -M no-aliases - | FileCheck --check-prefix=RELAX-INSTR %s
[RISCV] Add WasForced parameter to MCAsmBackend::fixupNeedsRelaxationAdvanced For RISCV branch instructions, we need to preserve relocation types when linker relaxation enabled, so then linker could modify offset when the branch offsets changed. We preserve relocation types by define shouldForceRelocation. IsResolved return by evaluateFixup will always false when shouldForceRelocation return true. It will make RISCV MC Branch Relaxation always relax 16-bit branches to 32-bit form, even if the symbol actually could be resolved. To avoid 16-bit branches always relax to 32-bit form when linker relaxation enabled, we add a new parameter WasForced to indicate that the symbol actually couldn't be resolved and not forced by shouldForceRelocation return true. RISCVAsmBackend::fixupNeedsRelaxationAdvanced could relax branches with unresolved symbols by (!IsResolved && !WasForced). RISCV MC Branch Relaxation is needed because RISCV could perform 32-bit to 16-bit transformation in MC layer. Differential Revision: https://reviews.llvm.org/D46350 llvm-svn: 332696
2018-05-18 14:42:21 +08:00
# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+c,+relax < %s \
# RUN: | llvm-readobj -r | FileCheck -check-prefix=RELAX-RELOC %s
[RISCV] Implement MC relaxations for compressed instructions. Summary: This patch implements relaxation for RISCV in the MC layer. The following relaxations are currently handled: 1) Relax C_BEQZ to BEQ and C_BNEZ to BNEZ in RISCV. 2) Relax and C_J $imm to JAL x0, $imm and CJAL to JAL ra, $imm. Reviewers: asb, llvm-commits, efriedma Reviewed By: asb Subscribers: shiva0217 Differential Revision: https://reviews.llvm.org/D43055 llvm-svn: 326626
2018-03-03 06:04:12 +08:00
FAR_JUMP_NEGATIVE:
c.nop
.space 2000
FAR_BRANCH_NEGATIVE:
c.nop
.space 256
NEAR_NEGATIVE:
c.nop
start:
c.bnez a0, NEAR
#INSTR: c.bnez a0, 56
[RISCV] Add WasForced parameter to MCAsmBackend::fixupNeedsRelaxationAdvanced For RISCV branch instructions, we need to preserve relocation types when linker relaxation enabled, so then linker could modify offset when the branch offsets changed. We preserve relocation types by define shouldForceRelocation. IsResolved return by evaluateFixup will always false when shouldForceRelocation return true. It will make RISCV MC Branch Relaxation always relax 16-bit branches to 32-bit form, even if the symbol actually could be resolved. To avoid 16-bit branches always relax to 32-bit form when linker relaxation enabled, we add a new parameter WasForced to indicate that the symbol actually couldn't be resolved and not forced by shouldForceRelocation return true. RISCVAsmBackend::fixupNeedsRelaxationAdvanced could relax branches with unresolved symbols by (!IsResolved && !WasForced). RISCV MC Branch Relaxation is needed because RISCV could perform 32-bit to 16-bit transformation in MC layer. Differential Revision: https://reviews.llvm.org/D46350 llvm-svn: 332696
2018-05-18 14:42:21 +08:00
#RELAX-INSTR: c.bnez a0, 0
#RELAX-RELOC: R_RISCV_RVC_BRANCH
[RISCV] Implement MC relaxations for compressed instructions. Summary: This patch implements relaxation for RISCV in the MC layer. The following relaxations are currently handled: 1) Relax C_BEQZ to BEQ and C_BNEZ to BNEZ in RISCV. 2) Relax and C_J $imm to JAL x0, $imm and CJAL to JAL ra, $imm. Reviewers: asb, llvm-commits, efriedma Reviewed By: asb Subscribers: shiva0217 Differential Revision: https://reviews.llvm.org/D43055 llvm-svn: 326626
2018-03-03 06:04:12 +08:00
c.bnez a0, NEAR_NEGATIVE
#INSTR: c.bnez a0, -4
[RISCV] Add WasForced parameter to MCAsmBackend::fixupNeedsRelaxationAdvanced For RISCV branch instructions, we need to preserve relocation types when linker relaxation enabled, so then linker could modify offset when the branch offsets changed. We preserve relocation types by define shouldForceRelocation. IsResolved return by evaluateFixup will always false when shouldForceRelocation return true. It will make RISCV MC Branch Relaxation always relax 16-bit branches to 32-bit form, even if the symbol actually could be resolved. To avoid 16-bit branches always relax to 32-bit form when linker relaxation enabled, we add a new parameter WasForced to indicate that the symbol actually couldn't be resolved and not forced by shouldForceRelocation return true. RISCVAsmBackend::fixupNeedsRelaxationAdvanced could relax branches with unresolved symbols by (!IsResolved && !WasForced). RISCV MC Branch Relaxation is needed because RISCV could perform 32-bit to 16-bit transformation in MC layer. Differential Revision: https://reviews.llvm.org/D46350 llvm-svn: 332696
2018-05-18 14:42:21 +08:00
#RELAX-INSTR: c.bnez a0, 0
#RELAX-RELOC: R_RISCV_RVC_BRANCH
[RISCV] Implement MC relaxations for compressed instructions. Summary: This patch implements relaxation for RISCV in the MC layer. The following relaxations are currently handled: 1) Relax C_BEQZ to BEQ and C_BNEZ to BNEZ in RISCV. 2) Relax and C_J $imm to JAL x0, $imm and CJAL to JAL ra, $imm. Reviewers: asb, llvm-commits, efriedma Reviewed By: asb Subscribers: shiva0217 Differential Revision: https://reviews.llvm.org/D43055 llvm-svn: 326626
2018-03-03 06:04:12 +08:00
c.bnez a0, FAR_BRANCH
[RISCV] Tablegen-driven Instruction Compression. Summary: This patch implements a tablegen-driven Instruction Compression mechanism for generating RISCV compressed instructions (C Extension) from the expanded instruction form. This tablegen backend processes CompressPat declarations in a td file and generates all the compile-time and runtime checks required to validate the declarations, validate the input operands and generate correct instructions. The checks include validating register operands, immediate operands, fixed register operands and fixed immediate operands. Example: class CompressPat<dag input, dag output> { dag Input = input; dag Output = output; list<Predicate> Predicates = []; } let Predicates = [HasStdExtC] in { def : CompressPat<(ADD GPRNoX0:$rs1, GPRNoX0:$rs1, GPRNoX0:$rs2), (C_ADD GPRNoX0:$rs1, GPRNoX0:$rs2)>; } The result is an auto-generated header file 'RISCVGenCompressEmitter.inc' which exports two functions for compressing/uncompressing MCInst instructions, plus some helper functions: bool compressInst(MCInst& OutInst, const MCInst &MI, const MCSubtargetInfo &STI, MCContext &Context); bool uncompressInst(MCInst& OutInst, const MCInst &MI, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI); The clients that include this auto-generated header file and invoke these functions can compress an instruction before emitting it, in the target-specific ASM or ELF streamer, or can uncompress an instruction before printing it, when the expanded instruction format aliases is favored. The following clients were added to implement compression\uncompression for RISCV: 1) RISCVAsmParser::MatchAndEmitInstruction: Inserted a call to compressInst() to compresses instructions parsed by llvm-mc coming from an ASM input. 2) RISCVAsmPrinter::EmitInstruction: Inserted a call to compressInst() to compress instructions that were lowered from Machine Instructions (MachineInstr). 3) RVInstPrinter::printInst: Inserted a call to uncompressInst() to print the expanded version of the instruction instead of the compressed one (e.g, add s0, s0, a5 instead of c.add s0, a5) when -riscv-no-aliases is not passed. This patch squashes D45119, D42780 and D41932. It was reviewed in smaller patches by asb, efriedma, apazos and mgrang. Reviewers: asb, efriedma, apazos, llvm-commits, sabuasal Reviewed By: sabuasal Subscribers: mgorny, eraman, asb, rbar, johnrusso, simoncook, jordy.potman.lists, apazos, niosHD, kito-cheng, shiva0217, zzheng Differential Revision: https://reviews.llvm.org/D45385 llvm-svn: 329455
2018-04-07 05:07:05 +08:00
#INSTR-NEXT: bne a0, zero, 310
[RISCV] Add WasForced parameter to MCAsmBackend::fixupNeedsRelaxationAdvanced For RISCV branch instructions, we need to preserve relocation types when linker relaxation enabled, so then linker could modify offset when the branch offsets changed. We preserve relocation types by define shouldForceRelocation. IsResolved return by evaluateFixup will always false when shouldForceRelocation return true. It will make RISCV MC Branch Relaxation always relax 16-bit branches to 32-bit form, even if the symbol actually could be resolved. To avoid 16-bit branches always relax to 32-bit form when linker relaxation enabled, we add a new parameter WasForced to indicate that the symbol actually couldn't be resolved and not forced by shouldForceRelocation return true. RISCVAsmBackend::fixupNeedsRelaxationAdvanced could relax branches with unresolved symbols by (!IsResolved && !WasForced). RISCV MC Branch Relaxation is needed because RISCV could perform 32-bit to 16-bit transformation in MC layer. Differential Revision: https://reviews.llvm.org/D46350 llvm-svn: 332696
2018-05-18 14:42:21 +08:00
#RELAX-INSTR-NEXT: bne a0, zero, 0
#RELAX-RELOC: R_RISCV_BRANCH
[RISCV] Implement MC relaxations for compressed instructions. Summary: This patch implements relaxation for RISCV in the MC layer. The following relaxations are currently handled: 1) Relax C_BEQZ to BEQ and C_BNEZ to BNEZ in RISCV. 2) Relax and C_J $imm to JAL x0, $imm and CJAL to JAL ra, $imm. Reviewers: asb, llvm-commits, efriedma Reviewed By: asb Subscribers: shiva0217 Differential Revision: https://reviews.llvm.org/D43055 llvm-svn: 326626
2018-03-03 06:04:12 +08:00
c.bnez a0, FAR_BRANCH_NEGATIVE
[RISCV] Tablegen-driven Instruction Compression. Summary: This patch implements a tablegen-driven Instruction Compression mechanism for generating RISCV compressed instructions (C Extension) from the expanded instruction form. This tablegen backend processes CompressPat declarations in a td file and generates all the compile-time and runtime checks required to validate the declarations, validate the input operands and generate correct instructions. The checks include validating register operands, immediate operands, fixed register operands and fixed immediate operands. Example: class CompressPat<dag input, dag output> { dag Input = input; dag Output = output; list<Predicate> Predicates = []; } let Predicates = [HasStdExtC] in { def : CompressPat<(ADD GPRNoX0:$rs1, GPRNoX0:$rs1, GPRNoX0:$rs2), (C_ADD GPRNoX0:$rs1, GPRNoX0:$rs2)>; } The result is an auto-generated header file 'RISCVGenCompressEmitter.inc' which exports two functions for compressing/uncompressing MCInst instructions, plus some helper functions: bool compressInst(MCInst& OutInst, const MCInst &MI, const MCSubtargetInfo &STI, MCContext &Context); bool uncompressInst(MCInst& OutInst, const MCInst &MI, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI); The clients that include this auto-generated header file and invoke these functions can compress an instruction before emitting it, in the target-specific ASM or ELF streamer, or can uncompress an instruction before printing it, when the expanded instruction format aliases is favored. The following clients were added to implement compression\uncompression for RISCV: 1) RISCVAsmParser::MatchAndEmitInstruction: Inserted a call to compressInst() to compresses instructions parsed by llvm-mc coming from an ASM input. 2) RISCVAsmPrinter::EmitInstruction: Inserted a call to compressInst() to compress instructions that were lowered from Machine Instructions (MachineInstr). 3) RVInstPrinter::printInst: Inserted a call to uncompressInst() to print the expanded version of the instruction instead of the compressed one (e.g, add s0, s0, a5 instead of c.add s0, a5) when -riscv-no-aliases is not passed. This patch squashes D45119, D42780 and D41932. It was reviewed in smaller patches by asb, efriedma, apazos and mgrang. Reviewers: asb, efriedma, apazos, llvm-commits, sabuasal Reviewed By: sabuasal Subscribers: mgorny, eraman, asb, rbar, johnrusso, simoncook, jordy.potman.lists, apazos, niosHD, kito-cheng, shiva0217, zzheng Differential Revision: https://reviews.llvm.org/D45385 llvm-svn: 329455
2018-04-07 05:07:05 +08:00
#INSTR-NEXT: bne a0, zero, -268
[RISCV] Add WasForced parameter to MCAsmBackend::fixupNeedsRelaxationAdvanced For RISCV branch instructions, we need to preserve relocation types when linker relaxation enabled, so then linker could modify offset when the branch offsets changed. We preserve relocation types by define shouldForceRelocation. IsResolved return by evaluateFixup will always false when shouldForceRelocation return true. It will make RISCV MC Branch Relaxation always relax 16-bit branches to 32-bit form, even if the symbol actually could be resolved. To avoid 16-bit branches always relax to 32-bit form when linker relaxation enabled, we add a new parameter WasForced to indicate that the symbol actually couldn't be resolved and not forced by shouldForceRelocation return true. RISCVAsmBackend::fixupNeedsRelaxationAdvanced could relax branches with unresolved symbols by (!IsResolved && !WasForced). RISCV MC Branch Relaxation is needed because RISCV could perform 32-bit to 16-bit transformation in MC layer. Differential Revision: https://reviews.llvm.org/D46350 llvm-svn: 332696
2018-05-18 14:42:21 +08:00
#RELAX-INSTR-NEXT: bne a0, zero, 0
#RELAX-RELOC: R_RISCV_BRANCH
[RISCV] Implement MC relaxations for compressed instructions. Summary: This patch implements relaxation for RISCV in the MC layer. The following relaxations are currently handled: 1) Relax C_BEQZ to BEQ and C_BNEZ to BNEZ in RISCV. 2) Relax and C_J $imm to JAL x0, $imm and CJAL to JAL ra, $imm. Reviewers: asb, llvm-commits, efriedma Reviewed By: asb Subscribers: shiva0217 Differential Revision: https://reviews.llvm.org/D43055 llvm-svn: 326626
2018-03-03 06:04:12 +08:00
c.bnez a0, FAR_JUMP
[RISCV] Tablegen-driven Instruction Compression. Summary: This patch implements a tablegen-driven Instruction Compression mechanism for generating RISCV compressed instructions (C Extension) from the expanded instruction form. This tablegen backend processes CompressPat declarations in a td file and generates all the compile-time and runtime checks required to validate the declarations, validate the input operands and generate correct instructions. The checks include validating register operands, immediate operands, fixed register operands and fixed immediate operands. Example: class CompressPat<dag input, dag output> { dag Input = input; dag Output = output; list<Predicate> Predicates = []; } let Predicates = [HasStdExtC] in { def : CompressPat<(ADD GPRNoX0:$rs1, GPRNoX0:$rs1, GPRNoX0:$rs2), (C_ADD GPRNoX0:$rs1, GPRNoX0:$rs2)>; } The result is an auto-generated header file 'RISCVGenCompressEmitter.inc' which exports two functions for compressing/uncompressing MCInst instructions, plus some helper functions: bool compressInst(MCInst& OutInst, const MCInst &MI, const MCSubtargetInfo &STI, MCContext &Context); bool uncompressInst(MCInst& OutInst, const MCInst &MI, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI); The clients that include this auto-generated header file and invoke these functions can compress an instruction before emitting it, in the target-specific ASM or ELF streamer, or can uncompress an instruction before printing it, when the expanded instruction format aliases is favored. The following clients were added to implement compression\uncompression for RISCV: 1) RISCVAsmParser::MatchAndEmitInstruction: Inserted a call to compressInst() to compresses instructions parsed by llvm-mc coming from an ASM input. 2) RISCVAsmPrinter::EmitInstruction: Inserted a call to compressInst() to compress instructions that were lowered from Machine Instructions (MachineInstr). 3) RVInstPrinter::printInst: Inserted a call to uncompressInst() to print the expanded version of the instruction instead of the compressed one (e.g, add s0, s0, a5 instead of c.add s0, a5) when -riscv-no-aliases is not passed. This patch squashes D45119, D42780 and D41932. It was reviewed in smaller patches by asb, efriedma, apazos and mgrang. Reviewers: asb, efriedma, apazos, llvm-commits, sabuasal Reviewed By: sabuasal Subscribers: mgorny, eraman, asb, rbar, johnrusso, simoncook, jordy.potman.lists, apazos, niosHD, kito-cheng, shiva0217, zzheng Differential Revision: https://reviews.llvm.org/D45385 llvm-svn: 329455
2018-04-07 05:07:05 +08:00
#INSTR-NEXT: bne a0, zero, 2304
[RISCV] Add WasForced parameter to MCAsmBackend::fixupNeedsRelaxationAdvanced For RISCV branch instructions, we need to preserve relocation types when linker relaxation enabled, so then linker could modify offset when the branch offsets changed. We preserve relocation types by define shouldForceRelocation. IsResolved return by evaluateFixup will always false when shouldForceRelocation return true. It will make RISCV MC Branch Relaxation always relax 16-bit branches to 32-bit form, even if the symbol actually could be resolved. To avoid 16-bit branches always relax to 32-bit form when linker relaxation enabled, we add a new parameter WasForced to indicate that the symbol actually couldn't be resolved and not forced by shouldForceRelocation return true. RISCVAsmBackend::fixupNeedsRelaxationAdvanced could relax branches with unresolved symbols by (!IsResolved && !WasForced). RISCV MC Branch Relaxation is needed because RISCV could perform 32-bit to 16-bit transformation in MC layer. Differential Revision: https://reviews.llvm.org/D46350 llvm-svn: 332696
2018-05-18 14:42:21 +08:00
#RELAX-INSTR-NEXT: bne a0, zero, 0
#RELAX-RELOC: R_RISCV_BRANCH
[RISCV] Implement MC relaxations for compressed instructions. Summary: This patch implements relaxation for RISCV in the MC layer. The following relaxations are currently handled: 1) Relax C_BEQZ to BEQ and C_BNEZ to BNEZ in RISCV. 2) Relax and C_J $imm to JAL x0, $imm and CJAL to JAL ra, $imm. Reviewers: asb, llvm-commits, efriedma Reviewed By: asb Subscribers: shiva0217 Differential Revision: https://reviews.llvm.org/D43055 llvm-svn: 326626
2018-03-03 06:04:12 +08:00
c.bnez a0, FAR_JUMP_NEGATIVE
[RISCV] Tablegen-driven Instruction Compression. Summary: This patch implements a tablegen-driven Instruction Compression mechanism for generating RISCV compressed instructions (C Extension) from the expanded instruction form. This tablegen backend processes CompressPat declarations in a td file and generates all the compile-time and runtime checks required to validate the declarations, validate the input operands and generate correct instructions. The checks include validating register operands, immediate operands, fixed register operands and fixed immediate operands. Example: class CompressPat<dag input, dag output> { dag Input = input; dag Output = output; list<Predicate> Predicates = []; } let Predicates = [HasStdExtC] in { def : CompressPat<(ADD GPRNoX0:$rs1, GPRNoX0:$rs1, GPRNoX0:$rs2), (C_ADD GPRNoX0:$rs1, GPRNoX0:$rs2)>; } The result is an auto-generated header file 'RISCVGenCompressEmitter.inc' which exports two functions for compressing/uncompressing MCInst instructions, plus some helper functions: bool compressInst(MCInst& OutInst, const MCInst &MI, const MCSubtargetInfo &STI, MCContext &Context); bool uncompressInst(MCInst& OutInst, const MCInst &MI, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI); The clients that include this auto-generated header file and invoke these functions can compress an instruction before emitting it, in the target-specific ASM or ELF streamer, or can uncompress an instruction before printing it, when the expanded instruction format aliases is favored. The following clients were added to implement compression\uncompression for RISCV: 1) RISCVAsmParser::MatchAndEmitInstruction: Inserted a call to compressInst() to compresses instructions parsed by llvm-mc coming from an ASM input. 2) RISCVAsmPrinter::EmitInstruction: Inserted a call to compressInst() to compress instructions that were lowered from Machine Instructions (MachineInstr). 3) RVInstPrinter::printInst: Inserted a call to uncompressInst() to print the expanded version of the instruction instead of the compressed one (e.g, add s0, s0, a5 instead of c.add s0, a5) when -riscv-no-aliases is not passed. This patch squashes D45119, D42780 and D41932. It was reviewed in smaller patches by asb, efriedma, apazos and mgrang. Reviewers: asb, efriedma, apazos, llvm-commits, sabuasal Reviewed By: sabuasal Subscribers: mgorny, eraman, asb, rbar, johnrusso, simoncook, jordy.potman.lists, apazos, niosHD, kito-cheng, shiva0217, zzheng Differential Revision: https://reviews.llvm.org/D45385 llvm-svn: 329455
2018-04-07 05:07:05 +08:00
#INSTR-NEXT: bne a0, zero, -2278
[RISCV] Add WasForced parameter to MCAsmBackend::fixupNeedsRelaxationAdvanced For RISCV branch instructions, we need to preserve relocation types when linker relaxation enabled, so then linker could modify offset when the branch offsets changed. We preserve relocation types by define shouldForceRelocation. IsResolved return by evaluateFixup will always false when shouldForceRelocation return true. It will make RISCV MC Branch Relaxation always relax 16-bit branches to 32-bit form, even if the symbol actually could be resolved. To avoid 16-bit branches always relax to 32-bit form when linker relaxation enabled, we add a new parameter WasForced to indicate that the symbol actually couldn't be resolved and not forced by shouldForceRelocation return true. RISCVAsmBackend::fixupNeedsRelaxationAdvanced could relax branches with unresolved symbols by (!IsResolved && !WasForced). RISCV MC Branch Relaxation is needed because RISCV could perform 32-bit to 16-bit transformation in MC layer. Differential Revision: https://reviews.llvm.org/D46350 llvm-svn: 332696
2018-05-18 14:42:21 +08:00
#RELAX-INSTR-NEXT: bne a0, zero, 0
#RELAX-RELOC: R_RISCV_BRANCH
[RISCV] Implement MC relaxations for compressed instructions. Summary: This patch implements relaxation for RISCV in the MC layer. The following relaxations are currently handled: 1) Relax C_BEQZ to BEQ and C_BNEZ to BNEZ in RISCV. 2) Relax and C_J $imm to JAL x0, $imm and CJAL to JAL ra, $imm. Reviewers: asb, llvm-commits, efriedma Reviewed By: asb Subscribers: shiva0217 Differential Revision: https://reviews.llvm.org/D43055 llvm-svn: 326626
2018-03-03 06:04:12 +08:00
c.beqz a0, NEAR
#INSTR-NEXT: c.beqz a0, 36
[RISCV] Add WasForced parameter to MCAsmBackend::fixupNeedsRelaxationAdvanced For RISCV branch instructions, we need to preserve relocation types when linker relaxation enabled, so then linker could modify offset when the branch offsets changed. We preserve relocation types by define shouldForceRelocation. IsResolved return by evaluateFixup will always false when shouldForceRelocation return true. It will make RISCV MC Branch Relaxation always relax 16-bit branches to 32-bit form, even if the symbol actually could be resolved. To avoid 16-bit branches always relax to 32-bit form when linker relaxation enabled, we add a new parameter WasForced to indicate that the symbol actually couldn't be resolved and not forced by shouldForceRelocation return true. RISCVAsmBackend::fixupNeedsRelaxationAdvanced could relax branches with unresolved symbols by (!IsResolved && !WasForced). RISCV MC Branch Relaxation is needed because RISCV could perform 32-bit to 16-bit transformation in MC layer. Differential Revision: https://reviews.llvm.org/D46350 llvm-svn: 332696
2018-05-18 14:42:21 +08:00
#RELAX-INSTR-NEXT: c.beqz a0, 0
#RELAX-RELOC: R_RISCV_RVC_BRANCH
[RISCV] Implement MC relaxations for compressed instructions. Summary: This patch implements relaxation for RISCV in the MC layer. The following relaxations are currently handled: 1) Relax C_BEQZ to BEQ and C_BNEZ to BNEZ in RISCV. 2) Relax and C_J $imm to JAL x0, $imm and CJAL to JAL ra, $imm. Reviewers: asb, llvm-commits, efriedma Reviewed By: asb Subscribers: shiva0217 Differential Revision: https://reviews.llvm.org/D43055 llvm-svn: 326626
2018-03-03 06:04:12 +08:00
c.beqz a0, NEAR_NEGATIVE
#INSTR-NEXT: c.beqz a0, -24
[RISCV] Add WasForced parameter to MCAsmBackend::fixupNeedsRelaxationAdvanced For RISCV branch instructions, we need to preserve relocation types when linker relaxation enabled, so then linker could modify offset when the branch offsets changed. We preserve relocation types by define shouldForceRelocation. IsResolved return by evaluateFixup will always false when shouldForceRelocation return true. It will make RISCV MC Branch Relaxation always relax 16-bit branches to 32-bit form, even if the symbol actually could be resolved. To avoid 16-bit branches always relax to 32-bit form when linker relaxation enabled, we add a new parameter WasForced to indicate that the symbol actually couldn't be resolved and not forced by shouldForceRelocation return true. RISCVAsmBackend::fixupNeedsRelaxationAdvanced could relax branches with unresolved symbols by (!IsResolved && !WasForced). RISCV MC Branch Relaxation is needed because RISCV could perform 32-bit to 16-bit transformation in MC layer. Differential Revision: https://reviews.llvm.org/D46350 llvm-svn: 332696
2018-05-18 14:42:21 +08:00
#RELAX-INSTR-NEXT: c.beqz a0, 0
#RELAX-RELOC: R_RISCV_RVC_BRANCH
[RISCV] Implement MC relaxations for compressed instructions. Summary: This patch implements relaxation for RISCV in the MC layer. The following relaxations are currently handled: 1) Relax C_BEQZ to BEQ and C_BNEZ to BNEZ in RISCV. 2) Relax and C_J $imm to JAL x0, $imm and CJAL to JAL ra, $imm. Reviewers: asb, llvm-commits, efriedma Reviewed By: asb Subscribers: shiva0217 Differential Revision: https://reviews.llvm.org/D43055 llvm-svn: 326626
2018-03-03 06:04:12 +08:00
c.beqz a0, FAR_BRANCH
[RISCV] Tablegen-driven Instruction Compression. Summary: This patch implements a tablegen-driven Instruction Compression mechanism for generating RISCV compressed instructions (C Extension) from the expanded instruction form. This tablegen backend processes CompressPat declarations in a td file and generates all the compile-time and runtime checks required to validate the declarations, validate the input operands and generate correct instructions. The checks include validating register operands, immediate operands, fixed register operands and fixed immediate operands. Example: class CompressPat<dag input, dag output> { dag Input = input; dag Output = output; list<Predicate> Predicates = []; } let Predicates = [HasStdExtC] in { def : CompressPat<(ADD GPRNoX0:$rs1, GPRNoX0:$rs1, GPRNoX0:$rs2), (C_ADD GPRNoX0:$rs1, GPRNoX0:$rs2)>; } The result is an auto-generated header file 'RISCVGenCompressEmitter.inc' which exports two functions for compressing/uncompressing MCInst instructions, plus some helper functions: bool compressInst(MCInst& OutInst, const MCInst &MI, const MCSubtargetInfo &STI, MCContext &Context); bool uncompressInst(MCInst& OutInst, const MCInst &MI, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI); The clients that include this auto-generated header file and invoke these functions can compress an instruction before emitting it, in the target-specific ASM or ELF streamer, or can uncompress an instruction before printing it, when the expanded instruction format aliases is favored. The following clients were added to implement compression\uncompression for RISCV: 1) RISCVAsmParser::MatchAndEmitInstruction: Inserted a call to compressInst() to compresses instructions parsed by llvm-mc coming from an ASM input. 2) RISCVAsmPrinter::EmitInstruction: Inserted a call to compressInst() to compress instructions that were lowered from Machine Instructions (MachineInstr). 3) RVInstPrinter::printInst: Inserted a call to uncompressInst() to print the expanded version of the instruction instead of the compressed one (e.g, add s0, s0, a5 instead of c.add s0, a5) when -riscv-no-aliases is not passed. This patch squashes D45119, D42780 and D41932. It was reviewed in smaller patches by asb, efriedma, apazos and mgrang. Reviewers: asb, efriedma, apazos, llvm-commits, sabuasal Reviewed By: sabuasal Subscribers: mgorny, eraman, asb, rbar, johnrusso, simoncook, jordy.potman.lists, apazos, niosHD, kito-cheng, shiva0217, zzheng Differential Revision: https://reviews.llvm.org/D45385 llvm-svn: 329455
2018-04-07 05:07:05 +08:00
#INSTR-NEXT: beq a0, zero, 290
[RISCV] Add WasForced parameter to MCAsmBackend::fixupNeedsRelaxationAdvanced For RISCV branch instructions, we need to preserve relocation types when linker relaxation enabled, so then linker could modify offset when the branch offsets changed. We preserve relocation types by define shouldForceRelocation. IsResolved return by evaluateFixup will always false when shouldForceRelocation return true. It will make RISCV MC Branch Relaxation always relax 16-bit branches to 32-bit form, even if the symbol actually could be resolved. To avoid 16-bit branches always relax to 32-bit form when linker relaxation enabled, we add a new parameter WasForced to indicate that the symbol actually couldn't be resolved and not forced by shouldForceRelocation return true. RISCVAsmBackend::fixupNeedsRelaxationAdvanced could relax branches with unresolved symbols by (!IsResolved && !WasForced). RISCV MC Branch Relaxation is needed because RISCV could perform 32-bit to 16-bit transformation in MC layer. Differential Revision: https://reviews.llvm.org/D46350 llvm-svn: 332696
2018-05-18 14:42:21 +08:00
#RELAX-INSTR-NEXT: beq a0, zero, 0
#RELAX-RELOC: R_RISCV_BRANCH
[RISCV] Implement MC relaxations for compressed instructions. Summary: This patch implements relaxation for RISCV in the MC layer. The following relaxations are currently handled: 1) Relax C_BEQZ to BEQ and C_BNEZ to BNEZ in RISCV. 2) Relax and C_J $imm to JAL x0, $imm and CJAL to JAL ra, $imm. Reviewers: asb, llvm-commits, efriedma Reviewed By: asb Subscribers: shiva0217 Differential Revision: https://reviews.llvm.org/D43055 llvm-svn: 326626
2018-03-03 06:04:12 +08:00
c.beqz a0, FAR_BRANCH_NEGATIVE
[RISCV] Tablegen-driven Instruction Compression. Summary: This patch implements a tablegen-driven Instruction Compression mechanism for generating RISCV compressed instructions (C Extension) from the expanded instruction form. This tablegen backend processes CompressPat declarations in a td file and generates all the compile-time and runtime checks required to validate the declarations, validate the input operands and generate correct instructions. The checks include validating register operands, immediate operands, fixed register operands and fixed immediate operands. Example: class CompressPat<dag input, dag output> { dag Input = input; dag Output = output; list<Predicate> Predicates = []; } let Predicates = [HasStdExtC] in { def : CompressPat<(ADD GPRNoX0:$rs1, GPRNoX0:$rs1, GPRNoX0:$rs2), (C_ADD GPRNoX0:$rs1, GPRNoX0:$rs2)>; } The result is an auto-generated header file 'RISCVGenCompressEmitter.inc' which exports two functions for compressing/uncompressing MCInst instructions, plus some helper functions: bool compressInst(MCInst& OutInst, const MCInst &MI, const MCSubtargetInfo &STI, MCContext &Context); bool uncompressInst(MCInst& OutInst, const MCInst &MI, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI); The clients that include this auto-generated header file and invoke these functions can compress an instruction before emitting it, in the target-specific ASM or ELF streamer, or can uncompress an instruction before printing it, when the expanded instruction format aliases is favored. The following clients were added to implement compression\uncompression for RISCV: 1) RISCVAsmParser::MatchAndEmitInstruction: Inserted a call to compressInst() to compresses instructions parsed by llvm-mc coming from an ASM input. 2) RISCVAsmPrinter::EmitInstruction: Inserted a call to compressInst() to compress instructions that were lowered from Machine Instructions (MachineInstr). 3) RVInstPrinter::printInst: Inserted a call to uncompressInst() to print the expanded version of the instruction instead of the compressed one (e.g, add s0, s0, a5 instead of c.add s0, a5) when -riscv-no-aliases is not passed. This patch squashes D45119, D42780 and D41932. It was reviewed in smaller patches by asb, efriedma, apazos and mgrang. Reviewers: asb, efriedma, apazos, llvm-commits, sabuasal Reviewed By: sabuasal Subscribers: mgorny, eraman, asb, rbar, johnrusso, simoncook, jordy.potman.lists, apazos, niosHD, kito-cheng, shiva0217, zzheng Differential Revision: https://reviews.llvm.org/D45385 llvm-svn: 329455
2018-04-07 05:07:05 +08:00
#INSTR-NEXT: beq a0, zero, -288
[RISCV] Add WasForced parameter to MCAsmBackend::fixupNeedsRelaxationAdvanced For RISCV branch instructions, we need to preserve relocation types when linker relaxation enabled, so then linker could modify offset when the branch offsets changed. We preserve relocation types by define shouldForceRelocation. IsResolved return by evaluateFixup will always false when shouldForceRelocation return true. It will make RISCV MC Branch Relaxation always relax 16-bit branches to 32-bit form, even if the symbol actually could be resolved. To avoid 16-bit branches always relax to 32-bit form when linker relaxation enabled, we add a new parameter WasForced to indicate that the symbol actually couldn't be resolved and not forced by shouldForceRelocation return true. RISCVAsmBackend::fixupNeedsRelaxationAdvanced could relax branches with unresolved symbols by (!IsResolved && !WasForced). RISCV MC Branch Relaxation is needed because RISCV could perform 32-bit to 16-bit transformation in MC layer. Differential Revision: https://reviews.llvm.org/D46350 llvm-svn: 332696
2018-05-18 14:42:21 +08:00
#RELAX-INSTR-NEXT: beq a0, zero, 0
#RELAX-RELOC: R_RISCV_BRANCH
[RISCV] Implement MC relaxations for compressed instructions. Summary: This patch implements relaxation for RISCV in the MC layer. The following relaxations are currently handled: 1) Relax C_BEQZ to BEQ and C_BNEZ to BNEZ in RISCV. 2) Relax and C_J $imm to JAL x0, $imm and CJAL to JAL ra, $imm. Reviewers: asb, llvm-commits, efriedma Reviewed By: asb Subscribers: shiva0217 Differential Revision: https://reviews.llvm.org/D43055 llvm-svn: 326626
2018-03-03 06:04:12 +08:00
c.beqz a0, FAR_JUMP
[RISCV] Tablegen-driven Instruction Compression. Summary: This patch implements a tablegen-driven Instruction Compression mechanism for generating RISCV compressed instructions (C Extension) from the expanded instruction form. This tablegen backend processes CompressPat declarations in a td file and generates all the compile-time and runtime checks required to validate the declarations, validate the input operands and generate correct instructions. The checks include validating register operands, immediate operands, fixed register operands and fixed immediate operands. Example: class CompressPat<dag input, dag output> { dag Input = input; dag Output = output; list<Predicate> Predicates = []; } let Predicates = [HasStdExtC] in { def : CompressPat<(ADD GPRNoX0:$rs1, GPRNoX0:$rs1, GPRNoX0:$rs2), (C_ADD GPRNoX0:$rs1, GPRNoX0:$rs2)>; } The result is an auto-generated header file 'RISCVGenCompressEmitter.inc' which exports two functions for compressing/uncompressing MCInst instructions, plus some helper functions: bool compressInst(MCInst& OutInst, const MCInst &MI, const MCSubtargetInfo &STI, MCContext &Context); bool uncompressInst(MCInst& OutInst, const MCInst &MI, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI); The clients that include this auto-generated header file and invoke these functions can compress an instruction before emitting it, in the target-specific ASM or ELF streamer, or can uncompress an instruction before printing it, when the expanded instruction format aliases is favored. The following clients were added to implement compression\uncompression for RISCV: 1) RISCVAsmParser::MatchAndEmitInstruction: Inserted a call to compressInst() to compresses instructions parsed by llvm-mc coming from an ASM input. 2) RISCVAsmPrinter::EmitInstruction: Inserted a call to compressInst() to compress instructions that were lowered from Machine Instructions (MachineInstr). 3) RVInstPrinter::printInst: Inserted a call to uncompressInst() to print the expanded version of the instruction instead of the compressed one (e.g, add s0, s0, a5 instead of c.add s0, a5) when -riscv-no-aliases is not passed. This patch squashes D45119, D42780 and D41932. It was reviewed in smaller patches by asb, efriedma, apazos and mgrang. Reviewers: asb, efriedma, apazos, llvm-commits, sabuasal Reviewed By: sabuasal Subscribers: mgorny, eraman, asb, rbar, johnrusso, simoncook, jordy.potman.lists, apazos, niosHD, kito-cheng, shiva0217, zzheng Differential Revision: https://reviews.llvm.org/D45385 llvm-svn: 329455
2018-04-07 05:07:05 +08:00
#INSTR-NEXT: beq a0, zero, 2284
[RISCV] Add WasForced parameter to MCAsmBackend::fixupNeedsRelaxationAdvanced For RISCV branch instructions, we need to preserve relocation types when linker relaxation enabled, so then linker could modify offset when the branch offsets changed. We preserve relocation types by define shouldForceRelocation. IsResolved return by evaluateFixup will always false when shouldForceRelocation return true. It will make RISCV MC Branch Relaxation always relax 16-bit branches to 32-bit form, even if the symbol actually could be resolved. To avoid 16-bit branches always relax to 32-bit form when linker relaxation enabled, we add a new parameter WasForced to indicate that the symbol actually couldn't be resolved and not forced by shouldForceRelocation return true. RISCVAsmBackend::fixupNeedsRelaxationAdvanced could relax branches with unresolved symbols by (!IsResolved && !WasForced). RISCV MC Branch Relaxation is needed because RISCV could perform 32-bit to 16-bit transformation in MC layer. Differential Revision: https://reviews.llvm.org/D46350 llvm-svn: 332696
2018-05-18 14:42:21 +08:00
#RELAX-INSTR-NEXT: beq a0, zero, 0
#RELAX-RELOC: R_RISCV_BRANCH
[RISCV] Implement MC relaxations for compressed instructions. Summary: This patch implements relaxation for RISCV in the MC layer. The following relaxations are currently handled: 1) Relax C_BEQZ to BEQ and C_BNEZ to BNEZ in RISCV. 2) Relax and C_J $imm to JAL x0, $imm and CJAL to JAL ra, $imm. Reviewers: asb, llvm-commits, efriedma Reviewed By: asb Subscribers: shiva0217 Differential Revision: https://reviews.llvm.org/D43055 llvm-svn: 326626
2018-03-03 06:04:12 +08:00
c.beqz a0, FAR_JUMP_NEGATIVE
[RISCV] Tablegen-driven Instruction Compression. Summary: This patch implements a tablegen-driven Instruction Compression mechanism for generating RISCV compressed instructions (C Extension) from the expanded instruction form. This tablegen backend processes CompressPat declarations in a td file and generates all the compile-time and runtime checks required to validate the declarations, validate the input operands and generate correct instructions. The checks include validating register operands, immediate operands, fixed register operands and fixed immediate operands. Example: class CompressPat<dag input, dag output> { dag Input = input; dag Output = output; list<Predicate> Predicates = []; } let Predicates = [HasStdExtC] in { def : CompressPat<(ADD GPRNoX0:$rs1, GPRNoX0:$rs1, GPRNoX0:$rs2), (C_ADD GPRNoX0:$rs1, GPRNoX0:$rs2)>; } The result is an auto-generated header file 'RISCVGenCompressEmitter.inc' which exports two functions for compressing/uncompressing MCInst instructions, plus some helper functions: bool compressInst(MCInst& OutInst, const MCInst &MI, const MCSubtargetInfo &STI, MCContext &Context); bool uncompressInst(MCInst& OutInst, const MCInst &MI, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI); The clients that include this auto-generated header file and invoke these functions can compress an instruction before emitting it, in the target-specific ASM or ELF streamer, or can uncompress an instruction before printing it, when the expanded instruction format aliases is favored. The following clients were added to implement compression\uncompression for RISCV: 1) RISCVAsmParser::MatchAndEmitInstruction: Inserted a call to compressInst() to compresses instructions parsed by llvm-mc coming from an ASM input. 2) RISCVAsmPrinter::EmitInstruction: Inserted a call to compressInst() to compress instructions that were lowered from Machine Instructions (MachineInstr). 3) RVInstPrinter::printInst: Inserted a call to uncompressInst() to print the expanded version of the instruction instead of the compressed one (e.g, add s0, s0, a5 instead of c.add s0, a5) when -riscv-no-aliases is not passed. This patch squashes D45119, D42780 and D41932. It was reviewed in smaller patches by asb, efriedma, apazos and mgrang. Reviewers: asb, efriedma, apazos, llvm-commits, sabuasal Reviewed By: sabuasal Subscribers: mgorny, eraman, asb, rbar, johnrusso, simoncook, jordy.potman.lists, apazos, niosHD, kito-cheng, shiva0217, zzheng Differential Revision: https://reviews.llvm.org/D45385 llvm-svn: 329455
2018-04-07 05:07:05 +08:00
#INSTR-NEXT: beq a0, zero, -2298
[RISCV] Add WasForced parameter to MCAsmBackend::fixupNeedsRelaxationAdvanced For RISCV branch instructions, we need to preserve relocation types when linker relaxation enabled, so then linker could modify offset when the branch offsets changed. We preserve relocation types by define shouldForceRelocation. IsResolved return by evaluateFixup will always false when shouldForceRelocation return true. It will make RISCV MC Branch Relaxation always relax 16-bit branches to 32-bit form, even if the symbol actually could be resolved. To avoid 16-bit branches always relax to 32-bit form when linker relaxation enabled, we add a new parameter WasForced to indicate that the symbol actually couldn't be resolved and not forced by shouldForceRelocation return true. RISCVAsmBackend::fixupNeedsRelaxationAdvanced could relax branches with unresolved symbols by (!IsResolved && !WasForced). RISCV MC Branch Relaxation is needed because RISCV could perform 32-bit to 16-bit transformation in MC layer. Differential Revision: https://reviews.llvm.org/D46350 llvm-svn: 332696
2018-05-18 14:42:21 +08:00
#RELAX-INSTR-NEXT: beq a0, zero, 0
#RELAX-RELOC: R_RISCV_BRANCH
[RISCV] Implement MC relaxations for compressed instructions. Summary: This patch implements relaxation for RISCV in the MC layer. The following relaxations are currently handled: 1) Relax C_BEQZ to BEQ and C_BNEZ to BNEZ in RISCV. 2) Relax and C_J $imm to JAL x0, $imm and CJAL to JAL ra, $imm. Reviewers: asb, llvm-commits, efriedma Reviewed By: asb Subscribers: shiva0217 Differential Revision: https://reviews.llvm.org/D43055 llvm-svn: 326626
2018-03-03 06:04:12 +08:00
c.j NEAR
#INSTR-NEXT: c.j 16
[RISCV] Add WasForced parameter to MCAsmBackend::fixupNeedsRelaxationAdvanced For RISCV branch instructions, we need to preserve relocation types when linker relaxation enabled, so then linker could modify offset when the branch offsets changed. We preserve relocation types by define shouldForceRelocation. IsResolved return by evaluateFixup will always false when shouldForceRelocation return true. It will make RISCV MC Branch Relaxation always relax 16-bit branches to 32-bit form, even if the symbol actually could be resolved. To avoid 16-bit branches always relax to 32-bit form when linker relaxation enabled, we add a new parameter WasForced to indicate that the symbol actually couldn't be resolved and not forced by shouldForceRelocation return true. RISCVAsmBackend::fixupNeedsRelaxationAdvanced could relax branches with unresolved symbols by (!IsResolved && !WasForced). RISCV MC Branch Relaxation is needed because RISCV could perform 32-bit to 16-bit transformation in MC layer. Differential Revision: https://reviews.llvm.org/D46350 llvm-svn: 332696
2018-05-18 14:42:21 +08:00
#RELAX-INSTR-NEXT: c.j 0
#RELAX-RELOC: R_RISCV_RVC_JUMP
[RISCV] Implement MC relaxations for compressed instructions. Summary: This patch implements relaxation for RISCV in the MC layer. The following relaxations are currently handled: 1) Relax C_BEQZ to BEQ and C_BNEZ to BNEZ in RISCV. 2) Relax and C_J $imm to JAL x0, $imm and CJAL to JAL ra, $imm. Reviewers: asb, llvm-commits, efriedma Reviewed By: asb Subscribers: shiva0217 Differential Revision: https://reviews.llvm.org/D43055 llvm-svn: 326626
2018-03-03 06:04:12 +08:00
c.j NEAR_NEGATIVE
#INSTR-NEXT: c.j -44
[RISCV] Add WasForced parameter to MCAsmBackend::fixupNeedsRelaxationAdvanced For RISCV branch instructions, we need to preserve relocation types when linker relaxation enabled, so then linker could modify offset when the branch offsets changed. We preserve relocation types by define shouldForceRelocation. IsResolved return by evaluateFixup will always false when shouldForceRelocation return true. It will make RISCV MC Branch Relaxation always relax 16-bit branches to 32-bit form, even if the symbol actually could be resolved. To avoid 16-bit branches always relax to 32-bit form when linker relaxation enabled, we add a new parameter WasForced to indicate that the symbol actually couldn't be resolved and not forced by shouldForceRelocation return true. RISCVAsmBackend::fixupNeedsRelaxationAdvanced could relax branches with unresolved symbols by (!IsResolved && !WasForced). RISCV MC Branch Relaxation is needed because RISCV could perform 32-bit to 16-bit transformation in MC layer. Differential Revision: https://reviews.llvm.org/D46350 llvm-svn: 332696
2018-05-18 14:42:21 +08:00
#RELAX-INSTR-NEXT: c.j 0
#RELAX-RELOC: R_RISCV_RVC_JUMP
[RISCV] Implement MC relaxations for compressed instructions. Summary: This patch implements relaxation for RISCV in the MC layer. The following relaxations are currently handled: 1) Relax C_BEQZ to BEQ and C_BNEZ to BNEZ in RISCV. 2) Relax and C_J $imm to JAL x0, $imm and CJAL to JAL ra, $imm. Reviewers: asb, llvm-commits, efriedma Reviewed By: asb Subscribers: shiva0217 Differential Revision: https://reviews.llvm.org/D43055 llvm-svn: 326626
2018-03-03 06:04:12 +08:00
c.j FAR_BRANCH
#INSTR-NEXT: c.j 270
[RISCV] Add WasForced parameter to MCAsmBackend::fixupNeedsRelaxationAdvanced For RISCV branch instructions, we need to preserve relocation types when linker relaxation enabled, so then linker could modify offset when the branch offsets changed. We preserve relocation types by define shouldForceRelocation. IsResolved return by evaluateFixup will always false when shouldForceRelocation return true. It will make RISCV MC Branch Relaxation always relax 16-bit branches to 32-bit form, even if the symbol actually could be resolved. To avoid 16-bit branches always relax to 32-bit form when linker relaxation enabled, we add a new parameter WasForced to indicate that the symbol actually couldn't be resolved and not forced by shouldForceRelocation return true. RISCVAsmBackend::fixupNeedsRelaxationAdvanced could relax branches with unresolved symbols by (!IsResolved && !WasForced). RISCV MC Branch Relaxation is needed because RISCV could perform 32-bit to 16-bit transformation in MC layer. Differential Revision: https://reviews.llvm.org/D46350 llvm-svn: 332696
2018-05-18 14:42:21 +08:00
#RELAX-INSTR-NEXT: c.j 0
#RELAX-RELOC: R_RISCV_RVC_JUMP
[RISCV] Implement MC relaxations for compressed instructions. Summary: This patch implements relaxation for RISCV in the MC layer. The following relaxations are currently handled: 1) Relax C_BEQZ to BEQ and C_BNEZ to BNEZ in RISCV. 2) Relax and C_J $imm to JAL x0, $imm and CJAL to JAL ra, $imm. Reviewers: asb, llvm-commits, efriedma Reviewed By: asb Subscribers: shiva0217 Differential Revision: https://reviews.llvm.org/D43055 llvm-svn: 326626
2018-03-03 06:04:12 +08:00
c.j FAR_BRANCH_NEGATIVE
#INSTR-NEXT: c.j -306
[RISCV] Add WasForced parameter to MCAsmBackend::fixupNeedsRelaxationAdvanced For RISCV branch instructions, we need to preserve relocation types when linker relaxation enabled, so then linker could modify offset when the branch offsets changed. We preserve relocation types by define shouldForceRelocation. IsResolved return by evaluateFixup will always false when shouldForceRelocation return true. It will make RISCV MC Branch Relaxation always relax 16-bit branches to 32-bit form, even if the symbol actually could be resolved. To avoid 16-bit branches always relax to 32-bit form when linker relaxation enabled, we add a new parameter WasForced to indicate that the symbol actually couldn't be resolved and not forced by shouldForceRelocation return true. RISCVAsmBackend::fixupNeedsRelaxationAdvanced could relax branches with unresolved symbols by (!IsResolved && !WasForced). RISCV MC Branch Relaxation is needed because RISCV could perform 32-bit to 16-bit transformation in MC layer. Differential Revision: https://reviews.llvm.org/D46350 llvm-svn: 332696
2018-05-18 14:42:21 +08:00
#RELAX-INSTR-NEXT: c.j 0
#RELAX-RELOC: R_RISCV_RVC_JUMP
[RISCV] Implement MC relaxations for compressed instructions. Summary: This patch implements relaxation for RISCV in the MC layer. The following relaxations are currently handled: 1) Relax C_BEQZ to BEQ and C_BNEZ to BNEZ in RISCV. 2) Relax and C_J $imm to JAL x0, $imm and CJAL to JAL ra, $imm. Reviewers: asb, llvm-commits, efriedma Reviewed By: asb Subscribers: shiva0217 Differential Revision: https://reviews.llvm.org/D43055 llvm-svn: 326626
2018-03-03 06:04:12 +08:00
c.j FAR_JUMP
[RISCV] Tablegen-driven Instruction Compression. Summary: This patch implements a tablegen-driven Instruction Compression mechanism for generating RISCV compressed instructions (C Extension) from the expanded instruction form. This tablegen backend processes CompressPat declarations in a td file and generates all the compile-time and runtime checks required to validate the declarations, validate the input operands and generate correct instructions. The checks include validating register operands, immediate operands, fixed register operands and fixed immediate operands. Example: class CompressPat<dag input, dag output> { dag Input = input; dag Output = output; list<Predicate> Predicates = []; } let Predicates = [HasStdExtC] in { def : CompressPat<(ADD GPRNoX0:$rs1, GPRNoX0:$rs1, GPRNoX0:$rs2), (C_ADD GPRNoX0:$rs1, GPRNoX0:$rs2)>; } The result is an auto-generated header file 'RISCVGenCompressEmitter.inc' which exports two functions for compressing/uncompressing MCInst instructions, plus some helper functions: bool compressInst(MCInst& OutInst, const MCInst &MI, const MCSubtargetInfo &STI, MCContext &Context); bool uncompressInst(MCInst& OutInst, const MCInst &MI, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI); The clients that include this auto-generated header file and invoke these functions can compress an instruction before emitting it, in the target-specific ASM or ELF streamer, or can uncompress an instruction before printing it, when the expanded instruction format aliases is favored. The following clients were added to implement compression\uncompression for RISCV: 1) RISCVAsmParser::MatchAndEmitInstruction: Inserted a call to compressInst() to compresses instructions parsed by llvm-mc coming from an ASM input. 2) RISCVAsmPrinter::EmitInstruction: Inserted a call to compressInst() to compress instructions that were lowered from Machine Instructions (MachineInstr). 3) RVInstPrinter::printInst: Inserted a call to uncompressInst() to print the expanded version of the instruction instead of the compressed one (e.g, add s0, s0, a5 instead of c.add s0, a5) when -riscv-no-aliases is not passed. This patch squashes D45119, D42780 and D41932. It was reviewed in smaller patches by asb, efriedma, apazos and mgrang. Reviewers: asb, efriedma, apazos, llvm-commits, sabuasal Reviewed By: sabuasal Subscribers: mgorny, eraman, asb, rbar, johnrusso, simoncook, jordy.potman.lists, apazos, niosHD, kito-cheng, shiva0217, zzheng Differential Revision: https://reviews.llvm.org/D45385 llvm-svn: 329455
2018-04-07 05:07:05 +08:00
#INSTR-NEXT: jal zero, 2268
[RISCV] Add WasForced parameter to MCAsmBackend::fixupNeedsRelaxationAdvanced For RISCV branch instructions, we need to preserve relocation types when linker relaxation enabled, so then linker could modify offset when the branch offsets changed. We preserve relocation types by define shouldForceRelocation. IsResolved return by evaluateFixup will always false when shouldForceRelocation return true. It will make RISCV MC Branch Relaxation always relax 16-bit branches to 32-bit form, even if the symbol actually could be resolved. To avoid 16-bit branches always relax to 32-bit form when linker relaxation enabled, we add a new parameter WasForced to indicate that the symbol actually couldn't be resolved and not forced by shouldForceRelocation return true. RISCVAsmBackend::fixupNeedsRelaxationAdvanced could relax branches with unresolved symbols by (!IsResolved && !WasForced). RISCV MC Branch Relaxation is needed because RISCV could perform 32-bit to 16-bit transformation in MC layer. Differential Revision: https://reviews.llvm.org/D46350 llvm-svn: 332696
2018-05-18 14:42:21 +08:00
#RELAX-INSTR-NEXT: jal zero, 0
#RELAX-RELOC: R_RISCV_JAL
[RISCV] Implement MC relaxations for compressed instructions. Summary: This patch implements relaxation for RISCV in the MC layer. The following relaxations are currently handled: 1) Relax C_BEQZ to BEQ and C_BNEZ to BNEZ in RISCV. 2) Relax and C_J $imm to JAL x0, $imm and CJAL to JAL ra, $imm. Reviewers: asb, llvm-commits, efriedma Reviewed By: asb Subscribers: shiva0217 Differential Revision: https://reviews.llvm.org/D43055 llvm-svn: 326626
2018-03-03 06:04:12 +08:00
c.j FAR_JUMP_NEGATIVE
[RISCV] Tablegen-driven Instruction Compression. Summary: This patch implements a tablegen-driven Instruction Compression mechanism for generating RISCV compressed instructions (C Extension) from the expanded instruction form. This tablegen backend processes CompressPat declarations in a td file and generates all the compile-time and runtime checks required to validate the declarations, validate the input operands and generate correct instructions. The checks include validating register operands, immediate operands, fixed register operands and fixed immediate operands. Example: class CompressPat<dag input, dag output> { dag Input = input; dag Output = output; list<Predicate> Predicates = []; } let Predicates = [HasStdExtC] in { def : CompressPat<(ADD GPRNoX0:$rs1, GPRNoX0:$rs1, GPRNoX0:$rs2), (C_ADD GPRNoX0:$rs1, GPRNoX0:$rs2)>; } The result is an auto-generated header file 'RISCVGenCompressEmitter.inc' which exports two functions for compressing/uncompressing MCInst instructions, plus some helper functions: bool compressInst(MCInst& OutInst, const MCInst &MI, const MCSubtargetInfo &STI, MCContext &Context); bool uncompressInst(MCInst& OutInst, const MCInst &MI, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI); The clients that include this auto-generated header file and invoke these functions can compress an instruction before emitting it, in the target-specific ASM or ELF streamer, or can uncompress an instruction before printing it, when the expanded instruction format aliases is favored. The following clients were added to implement compression\uncompression for RISCV: 1) RISCVAsmParser::MatchAndEmitInstruction: Inserted a call to compressInst() to compresses instructions parsed by llvm-mc coming from an ASM input. 2) RISCVAsmPrinter::EmitInstruction: Inserted a call to compressInst() to compress instructions that were lowered from Machine Instructions (MachineInstr). 3) RVInstPrinter::printInst: Inserted a call to uncompressInst() to print the expanded version of the instruction instead of the compressed one (e.g, add s0, s0, a5 instead of c.add s0, a5) when -riscv-no-aliases is not passed. This patch squashes D45119, D42780 and D41932. It was reviewed in smaller patches by asb, efriedma, apazos and mgrang. Reviewers: asb, efriedma, apazos, llvm-commits, sabuasal Reviewed By: sabuasal Subscribers: mgorny, eraman, asb, rbar, johnrusso, simoncook, jordy.potman.lists, apazos, niosHD, kito-cheng, shiva0217, zzheng Differential Revision: https://reviews.llvm.org/D45385 llvm-svn: 329455
2018-04-07 05:07:05 +08:00
#INSTR-NEXT: jal zero, -2314
[RISCV] Add WasForced parameter to MCAsmBackend::fixupNeedsRelaxationAdvanced For RISCV branch instructions, we need to preserve relocation types when linker relaxation enabled, so then linker could modify offset when the branch offsets changed. We preserve relocation types by define shouldForceRelocation. IsResolved return by evaluateFixup will always false when shouldForceRelocation return true. It will make RISCV MC Branch Relaxation always relax 16-bit branches to 32-bit form, even if the symbol actually could be resolved. To avoid 16-bit branches always relax to 32-bit form when linker relaxation enabled, we add a new parameter WasForced to indicate that the symbol actually couldn't be resolved and not forced by shouldForceRelocation return true. RISCVAsmBackend::fixupNeedsRelaxationAdvanced could relax branches with unresolved symbols by (!IsResolved && !WasForced). RISCV MC Branch Relaxation is needed because RISCV could perform 32-bit to 16-bit transformation in MC layer. Differential Revision: https://reviews.llvm.org/D46350 llvm-svn: 332696
2018-05-18 14:42:21 +08:00
#RELAX-INSTR-NEXT: jal zero, 0
#RELAX-RELOC: R_RISCV_JAL
[RISCV] Implement MC relaxations for compressed instructions. Summary: This patch implements relaxation for RISCV in the MC layer. The following relaxations are currently handled: 1) Relax C_BEQZ to BEQ and C_BNEZ to BNEZ in RISCV. 2) Relax and C_J $imm to JAL x0, $imm and CJAL to JAL ra, $imm. Reviewers: asb, llvm-commits, efriedma Reviewed By: asb Subscribers: shiva0217 Differential Revision: https://reviews.llvm.org/D43055 llvm-svn: 326626
2018-03-03 06:04:12 +08:00
NEAR:
c.nop
.space 256
FAR_BRANCH:
c.nop
.space 2000
FAR_JUMP:
c.nop