[AArch64][SVE2] Asm: add various bitwise shift instructions
Summary:
This patch adds support for the SVE2 saturating/rounding bitwise shift
left (predicated) group of instructions:
* SRSHL, URSHL, SRSHLR, URSHLR, SQSHL, UQSHL, SQRSHL, UQRSHL,
SQSHLR, UQSHLR, SQRSHLR, UQRSHLR
Immediate forms of the SQSHL and UQSHL instructions are also added to
the existing SVE bitwise shift by immediate (predicated) group, as well
as three new instructions SRSHR/URSHR/SQSHLU. The new instructions in
this group are encoded similarly and are implemented using the same
TableGen class with a minimal change (1 bit in encoding).
The specification can be found here:
https://developer.arm.com/docs/ddi0602/latest
Reviewed By: SjoerdMeijer
Differential Revision: https://reviews.llvm.org/D62140
llvm-svn: 361612
2019-05-24 17:17:23 +08:00
|
|
|
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
|
|
|
|
|
|
|
|
|
|
// --------------------------------------------------------------------------//
|
|
|
|
|
// Source and Destination Registers must match
|
|
|
|
|
|
|
|
|
|
sqrshl z0.b, p0/m, z1.b, z2.b
|
|
|
|
|
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
|
|
|
|
|
// CHECK-NEXT: sqrshl z0.b, p0/m, z1.b, z2.b
|
|
|
|
|
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
// --------------------------------------------------------------------------//
|
|
|
|
|
// Element sizes must match
|
|
|
|
|
|
|
|
|
|
sqrshl z0.b, p0/m, z0.d, z1.d
|
|
|
|
|
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
|
|
|
|
|
// CHECK-NEXT: sqrshl z0.b, p0/m, z0.d, z1.d
|
|
|
|
|
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
|
|
|
|
|
|
|
|
|
sqrshl z0.b, p0/m, z0.b, z1.h
|
|
|
|
|
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
|
|
|
|
|
// CHECK-NEXT: sqrshl z0.b, p0/m, z0.b, z1.h
|
|
|
|
|
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
// --------------------------------------------------------------------------//
|
|
|
|
|
// Invalid predicate
|
|
|
|
|
|
|
|
|
|
sqrshl z0.b, p0/z, z0.b, z1.b
|
|
|
|
|
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
|
|
|
|
|
// CHECK-NEXT: sqrshl z0.b, p0/z, z0.b, z1.b
|
|
|
|
|
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
|
|
|
|
|
|
|
|
|
sqrshl z0.b, p8/m, z0.b, z1.b
|
2019-06-07 16:37:00 +08:00
|
|
|
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
|
[AArch64][SVE2] Asm: add various bitwise shift instructions
Summary:
This patch adds support for the SVE2 saturating/rounding bitwise shift
left (predicated) group of instructions:
* SRSHL, URSHL, SRSHLR, URSHLR, SQSHL, UQSHL, SQRSHL, UQRSHL,
SQSHLR, UQSHLR, SQRSHLR, UQRSHLR
Immediate forms of the SQSHL and UQSHL instructions are also added to
the existing SVE bitwise shift by immediate (predicated) group, as well
as three new instructions SRSHR/URSHR/SQSHLU. The new instructions in
this group are encoded similarly and are implemented using the same
TableGen class with a minimal change (1 bit in encoding).
The specification can be found here:
https://developer.arm.com/docs/ddi0602/latest
Reviewed By: SjoerdMeijer
Differential Revision: https://reviews.llvm.org/D62140
llvm-svn: 361612
2019-05-24 17:17:23 +08:00
|
|
|
// CHECK-NEXT: sqrshl z0.b, p8/m, z0.b, z1.b
|
|
|
|
|
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
