2019-07-26 23:57:50 +08:00
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// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2-bitperm 2>&1 < %s| FileCheck %s
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[AArch64][SVE2] Asm: support SVE2 Misc Group
Summary:
Patch adds support for the following instructions:
SVE2 bitwise exclusive-or interleaved:
* EORBT, EORTB
SVE2 bitwise permute:
* BEXT, BDEP, BGRP
SVE2 bitwise shift left long:
* SSHLLB, SSHLLT, USHLLB, USHLLT
SVE2 integer add/subtract interleaved long:
* SADDLBT, SSUBLBT, SSUBLTB
BDEP, BEXT and BGRP are enabled with SVE2 feature +bitperm, all other
instructions in this group are enabled with +sve2.
Reviewed By: chill
Differential Revision: https://reviews.llvm.org/D62304
llvm-svn: 361795
2019-05-28 16:42:22 +08:00
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// ------------------------------------------------------------------------- //
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// Invalid element width
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bdep z0.b, z1.h, z2.s
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: bdep z0.b, z1.h, z2.s
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Negative tests for instructions that are incompatible with movprfx
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movprfx z0, z7
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bdep z0.d, z1.d, z7.d
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
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// CHECK-NEXT: bdep z0.d, z1.d, z7.d
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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movprfx z0.d, p0/z, z7.d
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bdep z0.d, z1.d, z7.d
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
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// CHECK-NEXT: bdep z0.d, z1.d, z7.d
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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