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llvm-project/llvm/test/CodeGen/X86/pr15267.ll

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Make utils/update_llc_test_checks.py note that the assertions are autogenerated. Also update existing test cases which appear to be generated by it and weren't modified (other than addition of the header) by rerunning it. llvm-svn: 253917
2015-11-24 05:33:58 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
Fix PR15267 - When extloading from a vector with non-byte-addressable element, e.g. <4 x i1>, the current logic breaks. Extend the current logic to fix the case where the element type is not byte-addressable by loading all bytes, bit-extracting/packing each element. llvm-svn: 175642
2013-02-21 02:04:21 +08:00
; RUN: llc < %s -mtriple=x86_64-pc-linux -mcpu=corei7-avx | FileCheck %s
define <4 x i3> @test1(<4 x i3>* %in) nounwind {
[X86] Refreshed sign extension tests. llvm-svn: 245358
2015-08-19 05:21:35 +08:00
; CHECK-LABEL: test1:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; CHECK: # %bb.0:
[X86] Refreshed sign extension tests. llvm-svn: 245358
2015-08-19 05:21:35 +08:00
; CHECK-NEXT: movzwl (%rdi), %eax
; CHECK-NEXT: movl %eax, %ecx
; CHECK-NEXT: shrl $3, %ecx
[X86][SSE] Vectorize a bit (AND/XOR/OR) op if a BUILD_VECTOR has the same op for all their scalar elements. If all a BUILD_VECTOR's source elements are the same bit (AND/XOR/OR) operation type and each has one constant operand, lower to a pair of BUILD_VECTOR and just apply the bit operation to the vectors. The constant operands will form a constant vector meaning that we still only have a single BUILD_VECTOR to lower and we will have replaced all the scalarized operations with a single SSE equivalent. Its not in our interest to start make a general purpose vectorizer from this, but I'm seeing enough of these scalar bit operations from the later legalization/scalarization stages to support them at least. Differential Revision: http://reviews.llvm.org/D18492 llvm-svn: 264666
2016-03-29 05:33:52 +08:00
; CHECK-NEXT: vmovd %eax, %xmm0
[X86] Refreshed sign extension tests. llvm-svn: 245358
2015-08-19 05:21:35 +08:00
; CHECK-NEXT: vpinsrd $1, %ecx, %xmm0, %xmm0
; CHECK-NEXT: movl %eax, %ecx
; CHECK-NEXT: shrl $6, %ecx
; CHECK-NEXT: vpinsrd $2, %ecx, %xmm0, %xmm0
; CHECK-NEXT: shrl $9, %eax
; CHECK-NEXT: vpinsrd $3, %eax, %xmm0, %xmm0
[X86][SSE] Vectorize a bit (AND/XOR/OR) op if a BUILD_VECTOR has the same op for all their scalar elements. If all a BUILD_VECTOR's source elements are the same bit (AND/XOR/OR) operation type and each has one constant operand, lower to a pair of BUILD_VECTOR and just apply the bit operation to the vectors. The constant operands will form a constant vector meaning that we still only have a single BUILD_VECTOR to lower and we will have replaced all the scalarized operations with a single SSE equivalent. Its not in our interest to start make a general purpose vectorizer from this, but I'm seeing enough of these scalar bit operations from the later legalization/scalarization stages to support them at least. Differential Revision: http://reviews.llvm.org/D18492 llvm-svn: 264666
2016-03-29 05:33:52 +08:00
; CHECK-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
[X86] Refreshed sign extension tests. llvm-svn: 245358
2015-08-19 05:21:35 +08:00
; CHECK-NEXT: retq
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%ret = load <4 x i3>, <4 x i3>* %in, align 1
Fix PR15267 - When extloading from a vector with non-byte-addressable element, e.g. <4 x i1>, the current logic breaks. Extend the current logic to fix the case where the element type is not byte-addressable by loading all bytes, bit-extracting/packing each element. llvm-svn: 175642
2013-02-21 02:04:21 +08:00
ret <4 x i3> %ret
}
define <4 x i1> @test2(<4 x i1>* %in) nounwind {
[X86] Refreshed sign extension tests. llvm-svn: 245358
2015-08-19 05:21:35 +08:00
; CHECK-LABEL: test2:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; CHECK: # %bb.0:
[X86] Refreshed sign extension tests. llvm-svn: 245358
2015-08-19 05:21:35 +08:00
; CHECK-NEXT: movzbl (%rdi), %eax
; CHECK-NEXT: movl %eax, %ecx
; CHECK-NEXT: shrl %ecx
[X86][SSE] Vectorize a bit (AND/XOR/OR) op if a BUILD_VECTOR has the same op for all their scalar elements. If all a BUILD_VECTOR's source elements are the same bit (AND/XOR/OR) operation type and each has one constant operand, lower to a pair of BUILD_VECTOR and just apply the bit operation to the vectors. The constant operands will form a constant vector meaning that we still only have a single BUILD_VECTOR to lower and we will have replaced all the scalarized operations with a single SSE equivalent. Its not in our interest to start make a general purpose vectorizer from this, but I'm seeing enough of these scalar bit operations from the later legalization/scalarization stages to support them at least. Differential Revision: http://reviews.llvm.org/D18492 llvm-svn: 264666
2016-03-29 05:33:52 +08:00
; CHECK-NEXT: vmovd %eax, %xmm0
[X86] Refreshed sign extension tests. llvm-svn: 245358
2015-08-19 05:21:35 +08:00
; CHECK-NEXT: vpinsrd $1, %ecx, %xmm0, %xmm0
; CHECK-NEXT: movl %eax, %ecx
; CHECK-NEXT: shrl $2, %ecx
; CHECK-NEXT: vpinsrd $2, %ecx, %xmm0, %xmm0
; CHECK-NEXT: shrl $3, %eax
; CHECK-NEXT: vpinsrd $3, %eax, %xmm0, %xmm0
[X86][SSE] Vectorize a bit (AND/XOR/OR) op if a BUILD_VECTOR has the same op for all their scalar elements. If all a BUILD_VECTOR's source elements are the same bit (AND/XOR/OR) operation type and each has one constant operand, lower to a pair of BUILD_VECTOR and just apply the bit operation to the vectors. The constant operands will form a constant vector meaning that we still only have a single BUILD_VECTOR to lower and we will have replaced all the scalarized operations with a single SSE equivalent. Its not in our interest to start make a general purpose vectorizer from this, but I'm seeing enough of these scalar bit operations from the later legalization/scalarization stages to support them at least. Differential Revision: http://reviews.llvm.org/D18492 llvm-svn: 264666
2016-03-29 05:33:52 +08:00
; CHECK-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
[X86] Refreshed sign extension tests. llvm-svn: 245358
2015-08-19 05:21:35 +08:00
; CHECK-NEXT: retq
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%ret = load <4 x i1>, <4 x i1>* %in, align 1
Fix PR15267 - When extloading from a vector with non-byte-addressable element, e.g. <4 x i1>, the current logic breaks. Extend the current logic to fix the case where the element type is not byte-addressable by loading all bytes, bit-extracting/packing each element. llvm-svn: 175642
2013-02-21 02:04:21 +08:00
ret <4 x i1> %ret
}
define <4 x i64> @test3(<4 x i1>* %in) nounwind {
[X86] Refreshed sign extension tests. llvm-svn: 245358
2015-08-19 05:21:35 +08:00
; CHECK-LABEL: test3:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; CHECK: # %bb.0:
[X86] Refreshed sign extension tests. llvm-svn: 245358
2015-08-19 05:21:35 +08:00
; CHECK-NEXT: movzbl (%rdi), %eax
; CHECK-NEXT: movq %rax, %rcx
; CHECK-NEXT: shlq $62, %rcx
; CHECK-NEXT: sarq $63, %rcx
; CHECK-NEXT: movq %rax, %rdx
; CHECK-NEXT: shlq $63, %rdx
; CHECK-NEXT: sarq $63, %rdx
; CHECK-NEXT: vmovd %edx, %xmm0
; CHECK-NEXT: vpinsrd $1, %ecx, %xmm0, %xmm0
; CHECK-NEXT: movq %rax, %rcx
; CHECK-NEXT: shlq $61, %rcx
; CHECK-NEXT: sarq $63, %rcx
; CHECK-NEXT: vpinsrd $2, %ecx, %xmm0, %xmm0
; CHECK-NEXT: shlq $60, %rax
; CHECK-NEXT: sarq $63, %rax
; CHECK-NEXT: vpinsrd $3, %eax, %xmm0, %xmm0
[DAGCombiner] Fold CONCAT_VECTORS of EXTRACT_SUBVECTOR (or undef) to VECTOR_SHUFFLE. Check to see if this is a CONCAT_VECTORS of a bunch of EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector inputs come from at most two distinct vectors the same size as the result, attempt to turn this into a legal shuffle. Differential Revision: http://reviews.llvm.org/D12125 llvm-svn: 245490
2015-08-20 04:09:50 +08:00
; CHECK-NEXT: vpmovsxdq %xmm0, %xmm1
; CHECK-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
[X86] Refreshed sign extension tests. llvm-svn: 245358
2015-08-19 05:21:35 +08:00
; CHECK-NEXT: vpmovsxdq %xmm0, %xmm0
[DAGCombiner] Fold CONCAT_VECTORS of EXTRACT_SUBVECTOR (or undef) to VECTOR_SHUFFLE. Check to see if this is a CONCAT_VECTORS of a bunch of EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector inputs come from at most two distinct vectors the same size as the result, attempt to turn this into a legal shuffle. Differential Revision: http://reviews.llvm.org/D12125 llvm-svn: 245490
2015-08-20 04:09:50 +08:00
; CHECK-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0
[X86] Refreshed sign extension tests. llvm-svn: 245358
2015-08-19 05:21:35 +08:00
; CHECK-NEXT: retq
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%wide.load35 = load <4 x i1>, <4 x i1>* %in, align 1
Fix PR15267 - When extloading from a vector with non-byte-addressable element, e.g. <4 x i1>, the current logic breaks. Extend the current logic to fix the case where the element type is not byte-addressable by loading all bytes, bit-extracting/packing each element. llvm-svn: 175642
2013-02-21 02:04:21 +08:00
%sext = sext <4 x i1> %wide.load35 to <4 x i64>
ret <4 x i64> %sext
}
Fixes a bug in vector load legalization that confused bits and bytes. Differential Revision: http://reviews.llvm.org/D7400 llvm-svn: 228168
2015-02-05 02:54:01 +08:00
define <16 x i4> @test4(<16 x i4>* %in) nounwind {
[X86] Refreshed sign extension tests. llvm-svn: 245358
2015-08-19 05:21:35 +08:00
; CHECK-LABEL: test4:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; CHECK: # %bb.0:
[X86] Refreshed sign extension tests. llvm-svn: 245358
2015-08-19 05:21:35 +08:00
; CHECK-NEXT: movq (%rdi), %rax
; CHECK-NEXT: movl %eax, %ecx
; CHECK-NEXT: shrl $4, %ecx
; CHECK-NEXT: andl $15, %ecx
; CHECK-NEXT: movl %eax, %edx
; CHECK-NEXT: andl $15, %edx
; CHECK-NEXT: vmovd %edx, %xmm0
; CHECK-NEXT: vpinsrb $1, %ecx, %xmm0, %xmm0
; CHECK-NEXT: movl %eax, %ecx
; CHECK-NEXT: shrl $8, %ecx
; CHECK-NEXT: andl $15, %ecx
; CHECK-NEXT: vpinsrb $2, %ecx, %xmm0, %xmm0
; CHECK-NEXT: movl %eax, %ecx
; CHECK-NEXT: shrl $12, %ecx
; CHECK-NEXT: andl $15, %ecx
; CHECK-NEXT: vpinsrb $3, %ecx, %xmm0, %xmm0
; CHECK-NEXT: movl %eax, %ecx
; CHECK-NEXT: shrl $16, %ecx
; CHECK-NEXT: andl $15, %ecx
; CHECK-NEXT: vpinsrb $4, %ecx, %xmm0, %xmm0
; CHECK-NEXT: movl %eax, %ecx
; CHECK-NEXT: shrl $20, %ecx
; CHECK-NEXT: andl $15, %ecx
; CHECK-NEXT: vpinsrb $5, %ecx, %xmm0, %xmm0
; CHECK-NEXT: movl %eax, %ecx
; CHECK-NEXT: shrl $24, %ecx
; CHECK-NEXT: andl $15, %ecx
; CHECK-NEXT: vpinsrb $6, %ecx, %xmm0, %xmm0
; CHECK-NEXT: movl %eax, %ecx
; CHECK-NEXT: shrl $28, %ecx
; CHECK-NEXT: vpinsrb $7, %ecx, %xmm0, %xmm0
; CHECK-NEXT: movq %rax, %rcx
; CHECK-NEXT: shrq $32, %rcx
; CHECK-NEXT: andl $15, %ecx
; CHECK-NEXT: vpinsrb $8, %ecx, %xmm0, %xmm0
; CHECK-NEXT: movq %rax, %rcx
; CHECK-NEXT: shrq $36, %rcx
; CHECK-NEXT: andl $15, %ecx
; CHECK-NEXT: vpinsrb $9, %ecx, %xmm0, %xmm0
; CHECK-NEXT: movq %rax, %rcx
; CHECK-NEXT: shrq $40, %rcx
; CHECK-NEXT: andl $15, %ecx
; CHECK-NEXT: vpinsrb $10, %ecx, %xmm0, %xmm0
; CHECK-NEXT: movq %rax, %rcx
; CHECK-NEXT: shrq $44, %rcx
; CHECK-NEXT: andl $15, %ecx
; CHECK-NEXT: vpinsrb $11, %ecx, %xmm0, %xmm0
; CHECK-NEXT: movq %rax, %rcx
; CHECK-NEXT: shrq $48, %rcx
; CHECK-NEXT: andl $15, %ecx
; CHECK-NEXT: vpinsrb $12, %ecx, %xmm0, %xmm0
; CHECK-NEXT: movq %rax, %rcx
; CHECK-NEXT: shrq $52, %rcx
; CHECK-NEXT: andl $15, %ecx
; CHECK-NEXT: vpinsrb $13, %ecx, %xmm0, %xmm0
; CHECK-NEXT: movq %rax, %rcx
; CHECK-NEXT: shrq $56, %rcx
; CHECK-NEXT: andl $15, %ecx
; CHECK-NEXT: vpinsrb $14, %ecx, %xmm0, %xmm0
; CHECK-NEXT: shrq $60, %rax
; CHECK-NEXT: vpinsrb $15, %eax, %xmm0, %xmm0
; CHECK-NEXT: retq
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%ret = load <16 x i4>, <16 x i4>* %in, align 1
Fixes a bug in vector load legalization that confused bits and bytes. Differential Revision: http://reviews.llvm.org/D7400 llvm-svn: 228168
2015-02-05 02:54:01 +08:00
ret <16 x i4> %ret
}