2017-08-30 06:32:07 +08:00
|
|
|
//===- ImplicitNullChecks.cpp - Fold null checks into memory accesses -----===//
|
2015-06-16 02:44:27 +08:00
|
|
|
//
|
2019-01-19 16:50:56 +08:00
|
|
|
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
|
|
|
|
// See https://llvm.org/LICENSE.txt for license information.
|
|
|
|
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
|
2015-06-16 02:44:27 +08:00
|
|
|
//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
//
|
|
|
|
// This pass turns explicit null checks of the form
|
|
|
|
//
|
|
|
|
// test %r10, %r10
|
|
|
|
// je throw_npe
|
|
|
|
// movl (%r10), %esi
|
|
|
|
// ...
|
|
|
|
//
|
|
|
|
// to
|
|
|
|
//
|
|
|
|
// faulting_load_op("movl (%r10), %esi", throw_npe)
|
|
|
|
// ...
|
|
|
|
//
|
|
|
|
// With the help of a runtime that understands the .fault_maps section,
|
|
|
|
// faulting_load_op branches to throw_npe if executing movl (%r10), %esi incurs
|
|
|
|
// a page fault.
|
2017-04-12 12:41:35 +08:00
|
|
|
// Store and LoadStore are also supported.
|
2015-06-16 02:44:27 +08:00
|
|
|
//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
2017-08-30 06:32:07 +08:00
|
|
|
#include "llvm/ADT/ArrayRef.h"
|
|
|
|
#include "llvm/ADT/None.h"
|
|
|
|
#include "llvm/ADT/Optional.h"
|
|
|
|
#include "llvm/ADT/STLExtras.h"
|
2015-06-16 02:44:27 +08:00
|
|
|
#include "llvm/ADT/SmallVector.h"
|
2015-07-07 07:32:10 +08:00
|
|
|
#include "llvm/ADT/Statistic.h"
|
2016-06-23 06:16:51 +08:00
|
|
|
#include "llvm/Analysis/AliasAnalysis.h"
|
2017-08-30 06:32:07 +08:00
|
|
|
#include "llvm/Analysis/MemoryLocation.h"
|
2017-02-08 03:19:49 +08:00
|
|
|
#include "llvm/CodeGen/FaultMaps.h"
|
2017-08-30 06:32:07 +08:00
|
|
|
#include "llvm/CodeGen/MachineBasicBlock.h"
|
2015-06-16 02:44:27 +08:00
|
|
|
#include "llvm/CodeGen/MachineFunction.h"
|
|
|
|
#include "llvm/CodeGen/MachineFunctionPass.h"
|
2017-08-30 06:32:07 +08:00
|
|
|
#include "llvm/CodeGen/MachineInstr.h"
|
2015-06-16 02:44:27 +08:00
|
|
|
#include "llvm/CodeGen/MachineInstrBuilder.h"
|
2017-06-06 19:49:48 +08:00
|
|
|
#include "llvm/CodeGen/MachineMemOperand.h"
|
|
|
|
#include "llvm/CodeGen/MachineOperand.h"
|
|
|
|
#include "llvm/CodeGen/MachineRegisterInfo.h"
|
2017-08-30 06:32:07 +08:00
|
|
|
#include "llvm/CodeGen/PseudoSourceValue.h"
|
2017-11-08 09:01:31 +08:00
|
|
|
#include "llvm/CodeGen/TargetInstrInfo.h"
|
2017-11-17 09:07:10 +08:00
|
|
|
#include "llvm/CodeGen/TargetOpcodes.h"
|
|
|
|
#include "llvm/CodeGen/TargetRegisterInfo.h"
|
|
|
|
#include "llvm/CodeGen/TargetSubtargetInfo.h"
|
2015-06-16 02:44:27 +08:00
|
|
|
#include "llvm/IR/BasicBlock.h"
|
2017-08-30 06:32:07 +08:00
|
|
|
#include "llvm/IR/DebugLoc.h"
|
2015-08-04 12:41:34 +08:00
|
|
|
#include "llvm/IR/LLVMContext.h"
|
Sink all InitializePasses.h includes
This file lists every pass in LLVM, and is included by Pass.h, which is
very popular. Every time we add, remove, or rename a pass in LLVM, it
caused lots of recompilation.
I found this fact by looking at this table, which is sorted by the
number of times a file was changed over the last 100,000 git commits
multiplied by the number of object files that depend on it in the
current checkout:
recompiles touches affected_files header
342380 95 3604 llvm/include/llvm/ADT/STLExtras.h
314730 234 1345 llvm/include/llvm/InitializePasses.h
307036 118 2602 llvm/include/llvm/ADT/APInt.h
213049 59 3611 llvm/include/llvm/Support/MathExtras.h
170422 47 3626 llvm/include/llvm/Support/Compiler.h
162225 45 3605 llvm/include/llvm/ADT/Optional.h
158319 63 2513 llvm/include/llvm/ADT/Triple.h
140322 39 3598 llvm/include/llvm/ADT/StringRef.h
137647 59 2333 llvm/include/llvm/Support/Error.h
131619 73 1803 llvm/include/llvm/Support/FileSystem.h
Before this change, touching InitializePasses.h would cause 1345 files
to recompile. After this change, touching it only causes 550 compiles in
an incremental rebuild.
Reviewers: bkramer, asbirlea, bollu, jdoerfert
Differential Revision: https://reviews.llvm.org/D70211
2019-11-14 05:15:01 +08:00
|
|
|
#include "llvm/InitializePasses.h"
|
2017-08-30 06:32:07 +08:00
|
|
|
#include "llvm/MC/MCInstrDesc.h"
|
|
|
|
#include "llvm/MC/MCRegisterInfo.h"
|
|
|
|
#include "llvm/Pass.h"
|
2015-06-16 02:44:27 +08:00
|
|
|
#include "llvm/Support/CommandLine.h"
|
2017-08-30 06:32:07 +08:00
|
|
|
#include <cassert>
|
|
|
|
#include <cstdint>
|
|
|
|
#include <iterator>
|
2015-06-16 02:44:27 +08:00
|
|
|
|
|
|
|
using namespace llvm;
|
|
|
|
|
2016-03-10 00:00:35 +08:00
|
|
|
static cl::opt<int> PageSize("imp-null-check-page-size",
|
|
|
|
cl::desc("The page size of the target in bytes"),
|
2017-12-01 08:53:10 +08:00
|
|
|
cl::init(4096), cl::Hidden);
|
2015-06-16 02:44:27 +08:00
|
|
|
|
2016-12-23 08:41:21 +08:00
|
|
|
static cl::opt<unsigned> MaxInstsToConsider(
|
|
|
|
"imp-null-max-insts-to-consider",
|
|
|
|
cl::desc("The max number of instructions to consider hoisting loads over "
|
|
|
|
"(the algorithm is quadratic over this number)"),
|
2017-12-01 08:53:10 +08:00
|
|
|
cl::Hidden, cl::init(8));
|
2016-12-23 08:41:21 +08:00
|
|
|
|
2015-07-07 07:32:10 +08:00
|
|
|
#define DEBUG_TYPE "implicit-null-checks"
|
|
|
|
|
|
|
|
STATISTIC(NumImplicitNullChecks,
|
|
|
|
"Number of explicit null checks made implicit");
|
|
|
|
|
2015-06-16 02:44:27 +08:00
|
|
|
namespace {
|
|
|
|
|
|
|
|
class ImplicitNullChecks : public MachineFunctionPass {
|
2016-12-23 08:41:21 +08:00
|
|
|
/// Return true if \c computeDependence can process \p MI.
|
|
|
|
static bool canHandle(const MachineInstr *MI);
|
|
|
|
|
|
|
|
/// Helper function for \c computeDependence. Return true if \p A
|
|
|
|
/// and \p B do not have any dependences between them, and can be
|
|
|
|
/// re-ordered without changing program semantics.
|
|
|
|
bool canReorder(const MachineInstr *A, const MachineInstr *B);
|
|
|
|
|
|
|
|
/// A data type for representing the result computed by \c
|
|
|
|
/// computeDependence. States whether it is okay to reorder the
|
|
|
|
/// instruction passed to \c computeDependence with at most one
|
2018-09-08 10:04:20 +08:00
|
|
|
/// dependency.
|
2016-12-23 08:41:21 +08:00
|
|
|
struct DependenceResult {
|
|
|
|
/// Can we actually re-order \p MI with \p Insts (see \c
|
|
|
|
/// computeDependence).
|
|
|
|
bool CanReorder;
|
|
|
|
|
|
|
|
/// If non-None, then an instruction in \p Insts that also must be
|
|
|
|
/// hoisted.
|
|
|
|
Optional<ArrayRef<MachineInstr *>::iterator> PotentialDependence;
|
|
|
|
|
|
|
|
/*implicit*/ DependenceResult(
|
|
|
|
bool CanReorder,
|
|
|
|
Optional<ArrayRef<MachineInstr *>::iterator> PotentialDependence)
|
|
|
|
: CanReorder(CanReorder), PotentialDependence(PotentialDependence) {
|
|
|
|
assert((!PotentialDependence || CanReorder) &&
|
|
|
|
"!CanReorder && PotentialDependence.hasValue() not allowed!");
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
|
|
|
/// Compute a result for the following question: can \p MI be
|
|
|
|
/// re-ordered from after \p Insts to before it.
|
|
|
|
///
|
|
|
|
/// \c canHandle should return true for all instructions in \p
|
|
|
|
/// Insts.
|
|
|
|
DependenceResult computeDependence(const MachineInstr *MI,
|
2018-07-17 02:51:40 +08:00
|
|
|
ArrayRef<MachineInstr *> Block);
|
2016-12-23 08:41:21 +08:00
|
|
|
|
2015-06-16 02:44:27 +08:00
|
|
|
/// Represents one null check that can be made implicit.
|
2016-06-21 10:10:18 +08:00
|
|
|
class NullCheck {
|
2015-06-16 02:44:27 +08:00
|
|
|
// The memory operation the null check can be folded into.
|
|
|
|
MachineInstr *MemOperation;
|
|
|
|
|
|
|
|
// The instruction actually doing the null check (Ptr != 0).
|
|
|
|
MachineInstr *CheckOperation;
|
|
|
|
|
|
|
|
// The block the check resides in.
|
|
|
|
MachineBasicBlock *CheckBlock;
|
|
|
|
|
2015-06-19 09:53:21 +08:00
|
|
|
// The block branched to if the pointer is non-null.
|
2015-06-16 02:44:27 +08:00
|
|
|
MachineBasicBlock *NotNullSucc;
|
|
|
|
|
2015-06-19 09:53:21 +08:00
|
|
|
// The block branched to if the pointer is null.
|
2015-06-16 02:44:27 +08:00
|
|
|
MachineBasicBlock *NullSucc;
|
|
|
|
|
2018-01-26 16:15:29 +08:00
|
|
|
// If this is non-null, then MemOperation has a dependency on this
|
2016-06-23 06:16:51 +08:00
|
|
|
// instruction; and it needs to be hoisted to execute before MemOperation.
|
|
|
|
MachineInstr *OnlyDependency;
|
|
|
|
|
2016-06-21 10:10:18 +08:00
|
|
|
public:
|
2015-06-16 02:44:27 +08:00
|
|
|
explicit NullCheck(MachineInstr *memOperation, MachineInstr *checkOperation,
|
|
|
|
MachineBasicBlock *checkBlock,
|
|
|
|
MachineBasicBlock *notNullSucc,
|
2016-06-23 06:16:51 +08:00
|
|
|
MachineBasicBlock *nullSucc,
|
|
|
|
MachineInstr *onlyDependency)
|
2015-06-16 02:44:27 +08:00
|
|
|
: MemOperation(memOperation), CheckOperation(checkOperation),
|
2016-06-23 06:16:51 +08:00
|
|
|
CheckBlock(checkBlock), NotNullSucc(notNullSucc), NullSucc(nullSucc),
|
|
|
|
OnlyDependency(onlyDependency) {}
|
2016-06-21 10:10:18 +08:00
|
|
|
|
|
|
|
MachineInstr *getMemOperation() const { return MemOperation; }
|
|
|
|
|
|
|
|
MachineInstr *getCheckOperation() const { return CheckOperation; }
|
|
|
|
|
|
|
|
MachineBasicBlock *getCheckBlock() const { return CheckBlock; }
|
|
|
|
|
|
|
|
MachineBasicBlock *getNotNullSucc() const { return NotNullSucc; }
|
|
|
|
|
|
|
|
MachineBasicBlock *getNullSucc() const { return NullSucc; }
|
2016-06-23 06:16:51 +08:00
|
|
|
|
|
|
|
MachineInstr *getOnlyDependency() const { return OnlyDependency; }
|
2015-06-16 02:44:27 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
const TargetInstrInfo *TII = nullptr;
|
|
|
|
const TargetRegisterInfo *TRI = nullptr;
|
2016-06-23 06:16:51 +08:00
|
|
|
AliasAnalysis *AA = nullptr;
|
2017-02-28 15:04:49 +08:00
|
|
|
MachineFrameInfo *MFI = nullptr;
|
2015-06-16 02:44:27 +08:00
|
|
|
|
|
|
|
bool analyzeBlockForNullChecks(MachineBasicBlock &MBB,
|
|
|
|
SmallVectorImpl<NullCheck> &NullCheckList);
|
2017-02-08 03:19:49 +08:00
|
|
|
MachineInstr *insertFaultingInstr(MachineInstr *MI, MachineBasicBlock *MBB,
|
|
|
|
MachineBasicBlock *HandlerMBB);
|
2015-06-16 02:44:27 +08:00
|
|
|
void rewriteNullChecks(ArrayRef<NullCheck> NullCheckList);
|
|
|
|
|
2017-02-28 15:04:49 +08:00
|
|
|
enum AliasResult {
|
|
|
|
AR_NoAlias,
|
|
|
|
AR_MayAlias,
|
|
|
|
AR_WillAliasEverything
|
|
|
|
};
|
2017-08-30 06:32:07 +08:00
|
|
|
|
2017-02-28 15:04:49 +08:00
|
|
|
/// Returns AR_NoAlias if \p MI memory operation does not alias with
|
|
|
|
/// \p PrevMI, AR_MayAlias if they may alias and AR_WillAliasEverything if
|
|
|
|
/// they may alias and any further memory operation may alias with \p PrevMI.
|
2019-04-19 17:08:38 +08:00
|
|
|
AliasResult areMemoryOpsAliased(const MachineInstr &MI,
|
|
|
|
const MachineInstr *PrevMI) const;
|
2017-02-28 15:04:49 +08:00
|
|
|
|
|
|
|
enum SuitabilityResult {
|
|
|
|
SR_Suitable,
|
|
|
|
SR_Unsuitable,
|
|
|
|
SR_Impossible
|
|
|
|
};
|
2017-08-30 06:32:07 +08:00
|
|
|
|
2017-02-01 10:49:25 +08:00
|
|
|
/// Return SR_Suitable if \p MI a memory operation that can be used to
|
|
|
|
/// implicitly null check the value in \p PointerReg, SR_Unsuitable if
|
|
|
|
/// \p MI cannot be used to null check and SR_Impossible if there is
|
|
|
|
/// no sense to continue lookup due to any other instruction will not be able
|
|
|
|
/// to be used. \p PrevInsts is the set of instruction seen since
|
2017-02-28 15:04:49 +08:00
|
|
|
/// the explicit null check on \p PointerReg.
|
2019-04-19 17:08:38 +08:00
|
|
|
SuitabilityResult isSuitableMemoryOp(const MachineInstr &MI,
|
|
|
|
unsigned PointerReg,
|
2017-02-28 15:04:49 +08:00
|
|
|
ArrayRef<MachineInstr *> PrevInsts);
|
2016-12-23 08:41:24 +08:00
|
|
|
|
2018-01-17 20:29:38 +08:00
|
|
|
/// Return true if \p FaultingMI can be hoisted from after the
|
2016-12-23 08:41:24 +08:00
|
|
|
/// instructions in \p InstsSeenSoFar to before them. Set \p Dependence to a
|
|
|
|
/// non-null value if we also need to (and legally can) hoist a depedency.
|
2017-02-08 03:19:49 +08:00
|
|
|
bool canHoistInst(MachineInstr *FaultingMI, unsigned PointerReg,
|
|
|
|
ArrayRef<MachineInstr *> InstsSeenSoFar,
|
|
|
|
MachineBasicBlock *NullSucc, MachineInstr *&Dependence);
|
2016-12-23 08:41:24 +08:00
|
|
|
|
2015-06-16 02:44:27 +08:00
|
|
|
public:
|
|
|
|
static char ID;
|
|
|
|
|
|
|
|
ImplicitNullChecks() : MachineFunctionPass(ID) {
|
|
|
|
initializeImplicitNullChecksPass(*PassRegistry::getPassRegistry());
|
|
|
|
}
|
|
|
|
|
|
|
|
bool runOnMachineFunction(MachineFunction &MF) override;
|
2017-08-30 06:32:07 +08:00
|
|
|
|
2016-06-23 06:16:51 +08:00
|
|
|
void getAnalysisUsage(AnalysisUsage &AU) const override {
|
|
|
|
AU.addRequired<AAResultsWrapperPass>();
|
|
|
|
MachineFunctionPass::getAnalysisUsage(AU);
|
|
|
|
}
|
2016-03-29 01:05:30 +08:00
|
|
|
|
|
|
|
MachineFunctionProperties getRequiredProperties() const override {
|
|
|
|
return MachineFunctionProperties().set(
|
2016-08-25 09:27:13 +08:00
|
|
|
MachineFunctionProperties::Property::NoVRegs);
|
2016-03-29 01:05:30 +08:00
|
|
|
}
|
2015-06-16 02:44:27 +08:00
|
|
|
};
|
2015-11-13 04:51:44 +08:00
|
|
|
|
2017-08-30 06:32:07 +08:00
|
|
|
} // end anonymous namespace
|
2015-11-13 04:51:44 +08:00
|
|
|
|
2016-12-23 08:41:21 +08:00
|
|
|
bool ImplicitNullChecks::canHandle(const MachineInstr *MI) {
|
2019-06-06 06:33:10 +08:00
|
|
|
if (MI->isCall() || MI->mayRaiseFPException() ||
|
|
|
|
MI->hasUnmodeledSideEffects())
|
2016-12-23 08:41:21 +08:00
|
|
|
return false;
|
|
|
|
auto IsRegMask = [](const MachineOperand &MO) { return MO.isRegMask(); };
|
|
|
|
(void)IsRegMask;
|
2015-11-13 04:51:44 +08:00
|
|
|
|
2016-12-23 08:41:21 +08:00
|
|
|
assert(!llvm::any_of(MI->operands(), IsRegMask) &&
|
|
|
|
"Calls were filtered out above!");
|
2015-11-13 04:51:44 +08:00
|
|
|
|
2019-03-13 11:25:20 +08:00
|
|
|
auto IsUnordered = [](MachineMemOperand *MMO) { return MMO->isUnordered(); };
|
|
|
|
return llvm::all_of(MI->memoperands(), IsUnordered);
|
2015-11-13 04:51:44 +08:00
|
|
|
}
|
|
|
|
|
2016-12-23 08:41:21 +08:00
|
|
|
ImplicitNullChecks::DependenceResult
|
|
|
|
ImplicitNullChecks::computeDependence(const MachineInstr *MI,
|
|
|
|
ArrayRef<MachineInstr *> Block) {
|
|
|
|
assert(llvm::all_of(Block, canHandle) && "Check this first!");
|
2017-08-30 06:32:07 +08:00
|
|
|
assert(!is_contained(Block, MI) && "Block must be exclusive of MI!");
|
2015-11-13 04:51:44 +08:00
|
|
|
|
2016-12-23 08:41:21 +08:00
|
|
|
Optional<ArrayRef<MachineInstr *>::iterator> Dep;
|
2015-11-13 04:51:44 +08:00
|
|
|
|
2016-12-23 08:41:21 +08:00
|
|
|
for (auto I = Block.begin(), E = Block.end(); I != E; ++I) {
|
|
|
|
if (canReorder(*I, MI))
|
|
|
|
continue;
|
2015-11-13 04:51:44 +08:00
|
|
|
|
2016-12-23 08:41:21 +08:00
|
|
|
if (Dep == None) {
|
|
|
|
// Found one possible dependency, keep track of it.
|
|
|
|
Dep = I;
|
|
|
|
} else {
|
|
|
|
// We found two dependencies, so bail out.
|
|
|
|
return {false, None};
|
2015-11-13 04:51:44 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-12-23 08:41:21 +08:00
|
|
|
return {true, Dep};
|
2015-11-13 04:51:44 +08:00
|
|
|
}
|
|
|
|
|
2016-12-23 08:41:21 +08:00
|
|
|
bool ImplicitNullChecks::canReorder(const MachineInstr *A,
|
|
|
|
const MachineInstr *B) {
|
|
|
|
assert(canHandle(A) && canHandle(B) && "Precondition!");
|
2016-06-23 06:16:51 +08:00
|
|
|
|
2016-12-23 08:41:21 +08:00
|
|
|
// canHandle makes sure that we _can_ correctly analyze the dependencies
|
|
|
|
// between A and B here -- for instance, we should not be dealing with heap
|
|
|
|
// load-store dependencies here.
|
2016-06-23 06:16:51 +08:00
|
|
|
|
2016-12-23 08:41:21 +08:00
|
|
|
for (auto MOA : A->operands()) {
|
|
|
|
if (!(MOA.isReg() && MOA.getReg()))
|
|
|
|
continue;
|
2016-06-23 06:16:51 +08:00
|
|
|
|
Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM
Summary:
This clang-tidy check is looking for unsigned integer variables whose initializer
starts with an implicit cast from llvm::Register and changes the type of the
variable to llvm::Register (dropping the llvm:: where possible).
Partial reverts in:
X86FrameLowering.cpp - Some functions return unsigned and arguably should be MCRegister
X86FixupLEAs.cpp - Some functions return unsigned and arguably should be MCRegister
X86FrameLowering.cpp - Some functions return unsigned and arguably should be MCRegister
HexagonBitSimplify.cpp - Function takes BitTracker::RegisterRef which appears to be unsigned&
MachineVerifier.cpp - Ambiguous operator==() given MCRegister and const Register
PPCFastISel.cpp - No Register::operator-=()
PeepholeOptimizer.cpp - TargetInstrInfo::optimizeLoadInstr() takes an unsigned&
MachineTraceMetrics.cpp - MachineTraceMetrics lacks a suitable constructor
Manual fixups in:
ARMFastISel.cpp - ARMEmitLoad() now takes a Register& instead of unsigned&
HexagonSplitDouble.cpp - Ternary operator was ambiguous between unsigned/Register
HexagonConstExtenders.cpp - Has a local class named Register, used llvm::Register instead of Register.
PPCFastISel.cpp - PPCEmitLoad() now takes a Register& instead of unsigned&
Depends on D65919
Reviewers: arsenm, bogner, craig.topper, RKSimon
Reviewed By: arsenm
Subscribers: RKSimon, craig.topper, lenary, aemerson, wuzish, jholewinski, MatzeB, qcolombet, dschuff, jyknight, dylanmckay, sdardis, nemanjai, jvesely, wdng, nhaehnle, sbc100, jgravelle-google, kristof.beyls, hiraditya, aheejin, kbarton, fedor.sergeev, javed.absar, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, tpr, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, Jim, s.egerton, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D65962
llvm-svn: 369041
2019-08-16 03:22:08 +08:00
|
|
|
Register RegA = MOA.getReg();
|
2016-12-23 08:41:21 +08:00
|
|
|
for (auto MOB : B->operands()) {
|
|
|
|
if (!(MOB.isReg() && MOB.getReg()))
|
|
|
|
continue;
|
2016-06-23 06:16:51 +08:00
|
|
|
|
Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM
Summary:
This clang-tidy check is looking for unsigned integer variables whose initializer
starts with an implicit cast from llvm::Register and changes the type of the
variable to llvm::Register (dropping the llvm:: where possible).
Partial reverts in:
X86FrameLowering.cpp - Some functions return unsigned and arguably should be MCRegister
X86FixupLEAs.cpp - Some functions return unsigned and arguably should be MCRegister
X86FrameLowering.cpp - Some functions return unsigned and arguably should be MCRegister
HexagonBitSimplify.cpp - Function takes BitTracker::RegisterRef which appears to be unsigned&
MachineVerifier.cpp - Ambiguous operator==() given MCRegister and const Register
PPCFastISel.cpp - No Register::operator-=()
PeepholeOptimizer.cpp - TargetInstrInfo::optimizeLoadInstr() takes an unsigned&
MachineTraceMetrics.cpp - MachineTraceMetrics lacks a suitable constructor
Manual fixups in:
ARMFastISel.cpp - ARMEmitLoad() now takes a Register& instead of unsigned&
HexagonSplitDouble.cpp - Ternary operator was ambiguous between unsigned/Register
HexagonConstExtenders.cpp - Has a local class named Register, used llvm::Register instead of Register.
PPCFastISel.cpp - PPCEmitLoad() now takes a Register& instead of unsigned&
Depends on D65919
Reviewers: arsenm, bogner, craig.topper, RKSimon
Reviewed By: arsenm
Subscribers: RKSimon, craig.topper, lenary, aemerson, wuzish, jholewinski, MatzeB, qcolombet, dschuff, jyknight, dylanmckay, sdardis, nemanjai, jvesely, wdng, nhaehnle, sbc100, jgravelle-google, kristof.beyls, hiraditya, aheejin, kbarton, fedor.sergeev, javed.absar, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, tpr, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, Jim, s.egerton, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D65962
llvm-svn: 369041
2019-08-16 03:22:08 +08:00
|
|
|
Register RegB = MOB.getReg();
|
2015-11-13 04:51:44 +08:00
|
|
|
|
2017-02-02 00:04:21 +08:00
|
|
|
if (TRI->regsOverlap(RegA, RegB) && (MOA.isDef() || MOB.isDef()))
|
2016-12-23 08:41:21 +08:00
|
|
|
return false;
|
2015-11-13 04:51:44 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
2015-06-23 17:49:53 +08:00
|
|
|
}
|
2015-06-16 02:44:27 +08:00
|
|
|
|
|
|
|
bool ImplicitNullChecks::runOnMachineFunction(MachineFunction &MF) {
|
|
|
|
TII = MF.getSubtarget().getInstrInfo();
|
|
|
|
TRI = MF.getRegInfo().getTargetRegisterInfo();
|
2017-02-28 15:04:49 +08:00
|
|
|
MFI = &MF.getFrameInfo();
|
2016-06-23 06:16:51 +08:00
|
|
|
AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
|
2015-06-16 02:44:27 +08:00
|
|
|
|
|
|
|
SmallVector<NullCheck, 16> NullCheckList;
|
|
|
|
|
|
|
|
for (auto &MBB : MF)
|
|
|
|
analyzeBlockForNullChecks(MBB, NullCheckList);
|
|
|
|
|
|
|
|
if (!NullCheckList.empty())
|
|
|
|
rewriteNullChecks(NullCheckList);
|
|
|
|
|
|
|
|
return !NullCheckList.empty();
|
|
|
|
}
|
|
|
|
|
2016-06-23 06:16:51 +08:00
|
|
|
// Return true if any register aliasing \p Reg is live-in into \p MBB.
|
|
|
|
static bool AnyAliasLiveIn(const TargetRegisterInfo *TRI,
|
|
|
|
MachineBasicBlock *MBB, unsigned Reg) {
|
|
|
|
for (MCRegAliasIterator AR(Reg, TRI, /*IncludeSelf*/ true); AR.isValid();
|
|
|
|
++AR)
|
|
|
|
if (MBB->isLiveIn(*AR))
|
|
|
|
return true;
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2017-02-28 15:04:49 +08:00
|
|
|
ImplicitNullChecks::AliasResult
|
2019-04-19 17:08:38 +08:00
|
|
|
ImplicitNullChecks::areMemoryOpsAliased(const MachineInstr &MI,
|
|
|
|
const MachineInstr *PrevMI) const {
|
2017-02-28 15:04:49 +08:00
|
|
|
// If it is not memory access, skip the check.
|
|
|
|
if (!(PrevMI->mayStore() || PrevMI->mayLoad()))
|
|
|
|
return AR_NoAlias;
|
|
|
|
// Load-Load may alias
|
|
|
|
if (!(MI.mayStore() || PrevMI->mayStore()))
|
|
|
|
return AR_NoAlias;
|
|
|
|
// We lost info, conservatively alias. If it was store then no sense to
|
|
|
|
// continue because we won't be able to check against it further.
|
|
|
|
if (MI.memoperands_empty())
|
|
|
|
return MI.mayStore() ? AR_WillAliasEverything : AR_MayAlias;
|
|
|
|
if (PrevMI->memoperands_empty())
|
|
|
|
return PrevMI->mayStore() ? AR_WillAliasEverything : AR_MayAlias;
|
|
|
|
|
|
|
|
for (MachineMemOperand *MMO1 : MI.memoperands()) {
|
|
|
|
// MMO1 should have a value due it comes from operation we'd like to use
|
|
|
|
// as implicit null check.
|
|
|
|
assert(MMO1->getValue() && "MMO1 should have a Value!");
|
|
|
|
for (MachineMemOperand *MMO2 : PrevMI->memoperands()) {
|
|
|
|
if (const PseudoSourceValue *PSV = MMO2->getPseudoValue()) {
|
|
|
|
if (PSV->mayAlias(MFI))
|
|
|
|
return AR_MayAlias;
|
|
|
|
continue;
|
|
|
|
}
|
2018-10-11 05:28:44 +08:00
|
|
|
llvm::AliasResult AAResult =
|
|
|
|
AA->alias(MemoryLocation(MMO1->getValue(), LocationSize::unknown(),
|
|
|
|
MMO1->getAAInfo()),
|
|
|
|
MemoryLocation(MMO2->getValue(), LocationSize::unknown(),
|
|
|
|
MMO2->getAAInfo()));
|
2017-02-28 15:04:49 +08:00
|
|
|
if (AAResult != NoAlias)
|
|
|
|
return AR_MayAlias;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return AR_NoAlias;
|
|
|
|
}
|
|
|
|
|
2017-02-01 10:49:25 +08:00
|
|
|
ImplicitNullChecks::SuitabilityResult
|
2019-04-19 17:08:38 +08:00
|
|
|
ImplicitNullChecks::isSuitableMemoryOp(const MachineInstr &MI,
|
|
|
|
unsigned PointerReg,
|
2017-02-28 15:04:49 +08:00
|
|
|
ArrayRef<MachineInstr *> PrevInsts) {
|
2016-12-23 08:41:24 +08:00
|
|
|
int64_t Offset;
|
2019-04-19 17:08:38 +08:00
|
|
|
const MachineOperand *BaseOp;
|
2016-12-23 08:41:24 +08:00
|
|
|
|
2018-11-28 20:00:20 +08:00
|
|
|
if (!TII->getMemOperandWithOffset(MI, BaseOp, Offset, TRI) ||
|
|
|
|
!BaseOp->isReg() || BaseOp->getReg() != PointerReg)
|
2017-02-28 15:04:49 +08:00
|
|
|
return SR_Unsuitable;
|
2016-12-23 08:41:24 +08:00
|
|
|
|
2017-02-08 03:19:49 +08:00
|
|
|
// We want the mem access to be issued at a sane offset from PointerReg,
|
|
|
|
// so that if PointerReg is null then the access reliably page faults.
|
2019-12-19 19:19:36 +08:00
|
|
|
if (!(MI.mayLoadOrStore() && !MI.isPredicable() &&
|
2017-10-17 19:47:36 +08:00
|
|
|
-PageSize < Offset && Offset < PageSize))
|
2017-02-28 15:04:49 +08:00
|
|
|
return SR_Unsuitable;
|
2016-12-23 08:41:24 +08:00
|
|
|
|
2017-06-21 14:38:23 +08:00
|
|
|
// Finally, check whether the current memory access aliases with previous one.
|
|
|
|
for (auto *PrevMI : PrevInsts) {
|
|
|
|
AliasResult AR = areMemoryOpsAliased(MI, PrevMI);
|
|
|
|
if (AR == AR_WillAliasEverything)
|
|
|
|
return SR_Impossible;
|
|
|
|
if (AR == AR_MayAlias)
|
|
|
|
return SR_Unsuitable;
|
|
|
|
}
|
|
|
|
return SR_Suitable;
|
2016-12-23 08:41:24 +08:00
|
|
|
}
|
|
|
|
|
2017-02-08 03:19:49 +08:00
|
|
|
bool ImplicitNullChecks::canHoistInst(MachineInstr *FaultingMI,
|
|
|
|
unsigned PointerReg,
|
|
|
|
ArrayRef<MachineInstr *> InstsSeenSoFar,
|
|
|
|
MachineBasicBlock *NullSucc,
|
|
|
|
MachineInstr *&Dependence) {
|
2016-12-23 08:41:24 +08:00
|
|
|
auto DepResult = computeDependence(FaultingMI, InstsSeenSoFar);
|
|
|
|
if (!DepResult.CanReorder)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
if (!DepResult.PotentialDependence) {
|
|
|
|
Dependence = nullptr;
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
auto DependenceItr = *DepResult.PotentialDependence;
|
|
|
|
auto *DependenceMI = *DependenceItr;
|
|
|
|
|
|
|
|
// We don't want to reason about speculating loads. Note -- at this point
|
|
|
|
// we should have already filtered out all of the other non-speculatable
|
|
|
|
// things, like calls and stores.
|
2017-08-09 13:17:02 +08:00
|
|
|
// We also do not want to hoist stores because it might change the memory
|
|
|
|
// while the FaultingMI may result in faulting.
|
2016-12-23 08:41:24 +08:00
|
|
|
assert(canHandle(DependenceMI) && "Should never have reached here!");
|
2017-08-09 13:17:02 +08:00
|
|
|
if (DependenceMI->mayLoadOrStore())
|
2016-12-23 08:41:24 +08:00
|
|
|
return false;
|
|
|
|
|
|
|
|
for (auto &DependenceMO : DependenceMI->operands()) {
|
|
|
|
if (!(DependenceMO.isReg() && DependenceMO.getReg()))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
// Make sure that we won't clobber any live ins to the sibling block by
|
|
|
|
// hoisting Dependency. For instance, we can't hoist INST to before the
|
|
|
|
// null check (even if it safe, and does not violate any dependencies in
|
|
|
|
// the non_null_block) if %rdx is live in to _null_block.
|
|
|
|
//
|
|
|
|
// test %rcx, %rcx
|
|
|
|
// je _null_block
|
|
|
|
// _non_null_block:
|
2017-12-07 18:40:31 +08:00
|
|
|
// %rdx = INST
|
2016-12-23 08:41:24 +08:00
|
|
|
// ...
|
|
|
|
//
|
|
|
|
// This restriction does not apply to the faulting load inst because in
|
|
|
|
// case the pointer loaded from is in the null page, the load will not
|
|
|
|
// semantically execute, and affect machine state. That is, if the load
|
|
|
|
// was loading into %rax and it faults, the value of %rax should stay the
|
|
|
|
// same as it would have been had the load not have executed and we'd have
|
|
|
|
// branched to NullSucc directly.
|
|
|
|
if (AnyAliasLiveIn(TRI, NullSucc, DependenceMO.getReg()))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// The Dependency can't be re-defining the base register -- then we won't
|
|
|
|
// get the memory operation on the address we want. This is already
|
|
|
|
// checked in \c IsSuitableMemoryOp.
|
2017-02-02 00:04:21 +08:00
|
|
|
assert(!(DependenceMO.isDef() &&
|
|
|
|
TRI->regsOverlap(DependenceMO.getReg(), PointerReg)) &&
|
2016-12-23 08:41:24 +08:00
|
|
|
"Should have been checked before!");
|
|
|
|
}
|
|
|
|
|
|
|
|
auto DepDepResult =
|
|
|
|
computeDependence(DependenceMI, {InstsSeenSoFar.begin(), DependenceItr});
|
|
|
|
|
|
|
|
if (!DepDepResult.CanReorder || DepDepResult.PotentialDependence)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
Dependence = DependenceMI;
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2015-06-16 02:44:27 +08:00
|
|
|
/// Analyze MBB to check if its terminating branch can be turned into an
|
|
|
|
/// implicit null check. If yes, append a description of the said null check to
|
|
|
|
/// NullCheckList and return true, else return false.
|
|
|
|
bool ImplicitNullChecks::analyzeBlockForNullChecks(
|
|
|
|
MachineBasicBlock &MBB, SmallVectorImpl<NullCheck> &NullCheckList) {
|
2017-08-30 06:32:07 +08:00
|
|
|
using MachineBranchPredicate = TargetInstrInfo::MachineBranchPredicate;
|
2015-06-16 02:44:27 +08:00
|
|
|
|
2015-11-13 04:51:49 +08:00
|
|
|
MDNode *BranchMD = nullptr;
|
|
|
|
if (auto *BB = MBB.getBasicBlock())
|
|
|
|
BranchMD = BB->getTerminator()->getMetadata(LLVMContext::MD_make_implicit);
|
|
|
|
|
2015-07-01 05:22:32 +08:00
|
|
|
if (!BranchMD)
|
|
|
|
return false;
|
|
|
|
|
2015-06-16 02:44:27 +08:00
|
|
|
MachineBranchPredicate MBP;
|
|
|
|
|
2016-07-15 22:41:04 +08:00
|
|
|
if (TII->analyzeBranchPredicate(MBB, MBP, true))
|
2015-06-16 02:44:27 +08:00
|
|
|
return false;
|
|
|
|
|
|
|
|
// Is the predicate comparing an integer to zero?
|
|
|
|
if (!(MBP.LHS.isReg() && MBP.RHS.isImm() && MBP.RHS.getImm() == 0 &&
|
|
|
|
(MBP.Predicate == MachineBranchPredicate::PRED_NE ||
|
|
|
|
MBP.Predicate == MachineBranchPredicate::PRED_EQ)))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// If we cannot erase the test instruction itself, then making the null check
|
|
|
|
// implicit does not buy us much.
|
|
|
|
if (!MBP.SingleUseCondition)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
MachineBasicBlock *NotNullSucc, *NullSucc;
|
|
|
|
|
|
|
|
if (MBP.Predicate == MachineBranchPredicate::PRED_NE) {
|
|
|
|
NotNullSucc = MBP.TrueDest;
|
|
|
|
NullSucc = MBP.FalseDest;
|
|
|
|
} else {
|
|
|
|
NotNullSucc = MBP.FalseDest;
|
|
|
|
NullSucc = MBP.TrueDest;
|
|
|
|
}
|
|
|
|
|
|
|
|
// We handle the simplest case for now. We can potentially do better by using
|
|
|
|
// the machine dominator tree.
|
|
|
|
if (NotNullSucc->pred_size() != 1)
|
|
|
|
return false;
|
|
|
|
|
[ImplicitNullChecks] Check for rewrite of register used in 'test' instruction
The following code pattern:
mov %rax, %rcx
test %rax, %rax
%rax = ....
je throw_npe
mov(%rcx), %r9
mov(%rax), %r10
gets transformed into the following incorrect code after implicit null check pass:
mov %rax, %rcx
%rax = ....
faulting_load_op("movl (%rax), %r10", throw_npe)
mov(%rcx), %r9
For implicit null check pass, if the register that is checked for null value (ie, the register used in the 'test' instruction) is written into before the condition jump, we should avoid doing the optimization.
Patch by Surya Kumari Jangala!
Differential Revision: https://reviews.llvm.org/D48627
Reviewed By: skatkov
llvm-svn: 336241
2018-07-04 16:01:26 +08:00
|
|
|
// To prevent the invalid transformation of the following code:
|
|
|
|
//
|
|
|
|
// mov %rax, %rcx
|
|
|
|
// test %rax, %rax
|
|
|
|
// %rax = ...
|
|
|
|
// je throw_npe
|
|
|
|
// mov(%rcx), %r9
|
|
|
|
// mov(%rax), %r10
|
|
|
|
//
|
|
|
|
// into:
|
|
|
|
//
|
|
|
|
// mov %rax, %rcx
|
|
|
|
// %rax = ....
|
|
|
|
// faulting_load_op("movl (%rax), %r10", throw_npe)
|
|
|
|
// mov(%rcx), %r9
|
|
|
|
//
|
|
|
|
// we must ensure that there are no instructions between the 'test' and
|
|
|
|
// conditional jump that modify %rax.
|
Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM
Summary:
This clang-tidy check is looking for unsigned integer variables whose initializer
starts with an implicit cast from llvm::Register and changes the type of the
variable to llvm::Register (dropping the llvm:: where possible).
Partial reverts in:
X86FrameLowering.cpp - Some functions return unsigned and arguably should be MCRegister
X86FixupLEAs.cpp - Some functions return unsigned and arguably should be MCRegister
X86FrameLowering.cpp - Some functions return unsigned and arguably should be MCRegister
HexagonBitSimplify.cpp - Function takes BitTracker::RegisterRef which appears to be unsigned&
MachineVerifier.cpp - Ambiguous operator==() given MCRegister and const Register
PPCFastISel.cpp - No Register::operator-=()
PeepholeOptimizer.cpp - TargetInstrInfo::optimizeLoadInstr() takes an unsigned&
MachineTraceMetrics.cpp - MachineTraceMetrics lacks a suitable constructor
Manual fixups in:
ARMFastISel.cpp - ARMEmitLoad() now takes a Register& instead of unsigned&
HexagonSplitDouble.cpp - Ternary operator was ambiguous between unsigned/Register
HexagonConstExtenders.cpp - Has a local class named Register, used llvm::Register instead of Register.
PPCFastISel.cpp - PPCEmitLoad() now takes a Register& instead of unsigned&
Depends on D65919
Reviewers: arsenm, bogner, craig.topper, RKSimon
Reviewed By: arsenm
Subscribers: RKSimon, craig.topper, lenary, aemerson, wuzish, jholewinski, MatzeB, qcolombet, dschuff, jyknight, dylanmckay, sdardis, nemanjai, jvesely, wdng, nhaehnle, sbc100, jgravelle-google, kristof.beyls, hiraditya, aheejin, kbarton, fedor.sergeev, javed.absar, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, tpr, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, Jim, s.egerton, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D65962
llvm-svn: 369041
2019-08-16 03:22:08 +08:00
|
|
|
const Register PointerReg = MBP.LHS.getReg();
|
[ImplicitNullChecks] Check for rewrite of register used in 'test' instruction
The following code pattern:
mov %rax, %rcx
test %rax, %rax
%rax = ....
je throw_npe
mov(%rcx), %r9
mov(%rax), %r10
gets transformed into the following incorrect code after implicit null check pass:
mov %rax, %rcx
%rax = ....
faulting_load_op("movl (%rax), %r10", throw_npe)
mov(%rcx), %r9
For implicit null check pass, if the register that is checked for null value (ie, the register used in the 'test' instruction) is written into before the condition jump, we should avoid doing the optimization.
Patch by Surya Kumari Jangala!
Differential Revision: https://reviews.llvm.org/D48627
Reviewed By: skatkov
llvm-svn: 336241
2018-07-04 16:01:26 +08:00
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|
|
|
|
|
assert(MBP.ConditionDef->getParent() == &MBB && "Should be in basic block");
|
|
|
|
|
|
|
|
for (auto I = MBB.rbegin(); MBP.ConditionDef != &*I; ++I)
|
|
|
|
if (I->modifiesRegister(PointerReg, TRI))
|
|
|
|
return false;
|
|
|
|
|
2015-06-16 02:44:27 +08:00
|
|
|
// Starting with a code fragment like:
|
|
|
|
//
|
2017-11-29 01:15:09 +08:00
|
|
|
// test %rax, %rax
|
2015-06-16 02:44:27 +08:00
|
|
|
// jne LblNotNull
|
|
|
|
//
|
|
|
|
// LblNull:
|
|
|
|
// callq throw_NullPointerException
|
|
|
|
//
|
|
|
|
// LblNotNull:
|
2015-07-10 04:13:25 +08:00
|
|
|
// Inst0
|
|
|
|
// Inst1
|
|
|
|
// ...
|
2017-11-29 01:15:09 +08:00
|
|
|
// Def = Load (%rax + <offset>)
|
2015-06-16 02:44:27 +08:00
|
|
|
// ...
|
|
|
|
//
|
|
|
|
//
|
|
|
|
// we want to end up with
|
|
|
|
//
|
2017-11-29 01:15:09 +08:00
|
|
|
// Def = FaultingLoad (%rax + <offset>), LblNull
|
2015-06-16 02:44:27 +08:00
|
|
|
// jmp LblNotNull ;; explicit or fallthrough
|
|
|
|
//
|
|
|
|
// LblNotNull:
|
2015-07-10 04:13:25 +08:00
|
|
|
// Inst0
|
|
|
|
// Inst1
|
2015-06-16 02:44:27 +08:00
|
|
|
// ...
|
|
|
|
//
|
|
|
|
// LblNull:
|
|
|
|
// callq throw_NullPointerException
|
|
|
|
//
|
2015-11-13 16:14:00 +08:00
|
|
|
//
|
|
|
|
// To see why this is legal, consider the two possibilities:
|
|
|
|
//
|
2017-11-29 01:15:09 +08:00
|
|
|
// 1. %rax is null: since we constrain <offset> to be less than PageSize, the
|
2015-11-13 16:14:00 +08:00
|
|
|
// load instruction dereferences the null page, causing a segmentation
|
|
|
|
// fault.
|
|
|
|
//
|
2017-11-29 01:15:09 +08:00
|
|
|
// 2. %rax is not null: in this case we know that the load cannot fault, as
|
2015-11-13 16:14:00 +08:00
|
|
|
// otherwise the load would've faulted in the original program too and the
|
|
|
|
// original program would've been undefined.
|
|
|
|
//
|
|
|
|
// This reasoning cannot be extended to justify hoisting through arbitrary
|
|
|
|
// control flow. For instance, in the example below (in pseudo-C)
|
|
|
|
//
|
|
|
|
// if (ptr == null) { throw_npe(); unreachable; }
|
|
|
|
// if (some_cond) { return 42; }
|
|
|
|
// v = ptr->field; // LD
|
|
|
|
// ...
|
|
|
|
//
|
|
|
|
// we cannot (without code duplication) use the load marked "LD" to null check
|
|
|
|
// ptr -- clause (2) above does not apply in this case. In the above program
|
|
|
|
// the safety of ptr->field can be dependent on some_cond; and, for instance,
|
|
|
|
// ptr could be some non-null invalid reference that never gets loaded from
|
|
|
|
// because some_cond is always true.
|
2015-06-16 02:44:27 +08:00
|
|
|
|
2016-12-23 08:41:21 +08:00
|
|
|
SmallVector<MachineInstr *, 8> InstsSeenSoFar;
|
2015-07-10 04:13:25 +08:00
|
|
|
|
2016-12-23 08:41:21 +08:00
|
|
|
for (auto &MI : *NotNullSucc) {
|
|
|
|
if (!canHandle(&MI) || InstsSeenSoFar.size() >= MaxInstsToConsider)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
MachineInstr *Dependence;
|
2017-02-28 15:04:49 +08:00
|
|
|
SuitabilityResult SR = isSuitableMemoryOp(MI, PointerReg, InstsSeenSoFar);
|
2017-02-01 10:49:25 +08:00
|
|
|
if (SR == SR_Impossible)
|
|
|
|
return false;
|
2017-02-08 03:19:49 +08:00
|
|
|
if (SR == SR_Suitable &&
|
|
|
|
canHoistInst(&MI, PointerReg, InstsSeenSoFar, NullSucc, Dependence)) {
|
2016-12-23 08:41:21 +08:00
|
|
|
NullCheckList.emplace_back(&MI, MBP.ConditionDef, &MBB, NotNullSucc,
|
|
|
|
NullSucc, Dependence);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2017-06-21 14:38:23 +08:00
|
|
|
// If MI re-defines the PointerReg then we cannot move further.
|
2017-08-30 06:32:07 +08:00
|
|
|
if (llvm::any_of(MI.operands(), [&](MachineOperand &MO) {
|
2017-06-21 14:38:23 +08:00
|
|
|
return MO.isReg() && MO.getReg() && MO.isDef() &&
|
|
|
|
TRI->regsOverlap(MO.getReg(), PointerReg);
|
|
|
|
}))
|
|
|
|
return false;
|
2016-12-23 08:41:21 +08:00
|
|
|
InstsSeenSoFar.push_back(&MI);
|
2015-07-10 04:13:25 +08:00
|
|
|
}
|
|
|
|
|
2015-06-16 02:44:27 +08:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2017-02-08 03:19:49 +08:00
|
|
|
/// Wrap a machine instruction, MI, into a FAULTING machine instruction.
|
|
|
|
/// The FAULTING instruction does the same load/store as MI
|
|
|
|
/// (defining the same register), and branches to HandlerMBB if the mem access
|
|
|
|
/// faults. The FAULTING instruction is inserted at the end of MBB.
|
|
|
|
MachineInstr *ImplicitNullChecks::insertFaultingInstr(
|
|
|
|
MachineInstr *MI, MachineBasicBlock *MBB, MachineBasicBlock *HandlerMBB) {
|
2015-07-21 04:31:39 +08:00
|
|
|
const unsigned NoRegister = 0; // Guaranteed to be the NoRegister value for
|
|
|
|
// all targets.
|
|
|
|
|
2015-06-16 02:44:27 +08:00
|
|
|
DebugLoc DL;
|
2017-02-08 03:19:49 +08:00
|
|
|
unsigned NumDefs = MI->getDesc().getNumDefs();
|
2015-07-21 04:31:39 +08:00
|
|
|
assert(NumDefs <= 1 && "other cases unhandled!");
|
2015-06-16 02:44:27 +08:00
|
|
|
|
2015-07-21 04:31:39 +08:00
|
|
|
unsigned DefReg = NoRegister;
|
|
|
|
if (NumDefs != 0) {
|
2018-05-17 07:39:27 +08:00
|
|
|
DefReg = MI->getOperand(0).getReg();
|
2018-05-17 07:20:42 +08:00
|
|
|
assert(NumDefs == 1 && "expected exactly one def!");
|
2015-07-21 04:31:39 +08:00
|
|
|
}
|
2015-06-16 02:44:27 +08:00
|
|
|
|
2017-02-08 03:19:49 +08:00
|
|
|
FaultMaps::FaultKind FK;
|
|
|
|
if (MI->mayLoad())
|
|
|
|
FK =
|
|
|
|
MI->mayStore() ? FaultMaps::FaultingLoadStore : FaultMaps::FaultingLoad;
|
|
|
|
else
|
|
|
|
FK = FaultMaps::FaultingStore;
|
|
|
|
|
|
|
|
auto MIB = BuildMI(MBB, DL, TII->get(TargetOpcode::FAULTING_OP), DefReg)
|
|
|
|
.addImm(FK)
|
2016-05-03 06:58:54 +08:00
|
|
|
.addMBB(HandlerMBB)
|
2017-02-08 03:19:49 +08:00
|
|
|
.addImm(MI->getOpcode());
|
2015-06-16 02:44:27 +08:00
|
|
|
|
2017-06-01 06:23:08 +08:00
|
|
|
for (auto &MO : MI->uses()) {
|
|
|
|
if (MO.isReg()) {
|
|
|
|
MachineOperand NewMO = MO;
|
|
|
|
if (MO.isUse()) {
|
|
|
|
NewMO.setIsKill(false);
|
|
|
|
} else {
|
|
|
|
assert(MO.isDef() && "Expected def or use");
|
|
|
|
NewMO.setIsDead(false);
|
|
|
|
}
|
|
|
|
MIB.add(NewMO);
|
|
|
|
} else {
|
|
|
|
MIB.add(MO);
|
|
|
|
}
|
|
|
|
}
|
2015-06-16 02:44:27 +08:00
|
|
|
|
2018-08-17 05:30:05 +08:00
|
|
|
MIB.setMemRefs(MI->memoperands());
|
2015-06-16 02:44:27 +08:00
|
|
|
|
|
|
|
return MIB;
|
|
|
|
}
|
|
|
|
|
|
|
|
/// Rewrite the null checks in NullCheckList into implicit null checks.
|
|
|
|
void ImplicitNullChecks::rewriteNullChecks(
|
|
|
|
ArrayRef<ImplicitNullChecks::NullCheck> NullCheckList) {
|
|
|
|
DebugLoc DL;
|
|
|
|
|
|
|
|
for (auto &NC : NullCheckList) {
|
|
|
|
// Remove the conditional branch dependent on the null check.
|
2016-09-15 04:43:16 +08:00
|
|
|
unsigned BranchesRemoved = TII->removeBranch(*NC.getCheckBlock());
|
2015-06-16 02:44:27 +08:00
|
|
|
(void)BranchesRemoved;
|
|
|
|
assert(BranchesRemoved > 0 && "expected at least one branch!");
|
|
|
|
|
2016-06-23 06:16:51 +08:00
|
|
|
if (auto *DepMI = NC.getOnlyDependency()) {
|
|
|
|
DepMI->removeFromParent();
|
|
|
|
NC.getCheckBlock()->insert(NC.getCheckBlock()->end(), DepMI);
|
|
|
|
}
|
|
|
|
|
2017-02-08 03:19:49 +08:00
|
|
|
// Insert a faulting instruction where the conditional branch was
|
|
|
|
// originally. We check earlier ensures that this bit of code motion
|
|
|
|
// is legal. We do not touch the successors list for any basic block
|
|
|
|
// since we haven't changed control flow, we've just made it implicit.
|
|
|
|
MachineInstr *FaultingInstr = insertFaultingInstr(
|
2016-06-21 10:10:18 +08:00
|
|
|
NC.getMemOperation(), NC.getCheckBlock(), NC.getNullSucc());
|
2016-05-04 02:09:06 +08:00
|
|
|
// Now the values defined by MemOperation, if any, are live-in of
|
|
|
|
// the block of MemOperation.
|
2017-02-08 03:19:49 +08:00
|
|
|
// The original operation may define implicit-defs alongside
|
|
|
|
// the value.
|
2016-06-21 10:10:18 +08:00
|
|
|
MachineBasicBlock *MBB = NC.getMemOperation()->getParent();
|
2017-02-08 03:19:49 +08:00
|
|
|
for (const MachineOperand &MO : FaultingInstr->operands()) {
|
2016-05-04 02:09:06 +08:00
|
|
|
if (!MO.isReg() || !MO.isDef())
|
|
|
|
continue;
|
Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM
Summary:
This clang-tidy check is looking for unsigned integer variables whose initializer
starts with an implicit cast from llvm::Register and changes the type of the
variable to llvm::Register (dropping the llvm:: where possible).
Partial reverts in:
X86FrameLowering.cpp - Some functions return unsigned and arguably should be MCRegister
X86FixupLEAs.cpp - Some functions return unsigned and arguably should be MCRegister
X86FrameLowering.cpp - Some functions return unsigned and arguably should be MCRegister
HexagonBitSimplify.cpp - Function takes BitTracker::RegisterRef which appears to be unsigned&
MachineVerifier.cpp - Ambiguous operator==() given MCRegister and const Register
PPCFastISel.cpp - No Register::operator-=()
PeepholeOptimizer.cpp - TargetInstrInfo::optimizeLoadInstr() takes an unsigned&
MachineTraceMetrics.cpp - MachineTraceMetrics lacks a suitable constructor
Manual fixups in:
ARMFastISel.cpp - ARMEmitLoad() now takes a Register& instead of unsigned&
HexagonSplitDouble.cpp - Ternary operator was ambiguous between unsigned/Register
HexagonConstExtenders.cpp - Has a local class named Register, used llvm::Register instead of Register.
PPCFastISel.cpp - PPCEmitLoad() now takes a Register& instead of unsigned&
Depends on D65919
Reviewers: arsenm, bogner, craig.topper, RKSimon
Reviewed By: arsenm
Subscribers: RKSimon, craig.topper, lenary, aemerson, wuzish, jholewinski, MatzeB, qcolombet, dschuff, jyknight, dylanmckay, sdardis, nemanjai, jvesely, wdng, nhaehnle, sbc100, jgravelle-google, kristof.beyls, hiraditya, aheejin, kbarton, fedor.sergeev, javed.absar, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, tpr, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, Jim, s.egerton, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D65962
llvm-svn: 369041
2019-08-16 03:22:08 +08:00
|
|
|
Register Reg = MO.getReg();
|
2016-05-04 02:09:06 +08:00
|
|
|
if (!Reg || MBB->isLiveIn(Reg))
|
|
|
|
continue;
|
|
|
|
MBB->addLiveIn(Reg);
|
2016-04-28 07:26:40 +08:00
|
|
|
}
|
2016-06-23 06:16:51 +08:00
|
|
|
|
|
|
|
if (auto *DepMI = NC.getOnlyDependency()) {
|
|
|
|
for (auto &MO : DepMI->operands()) {
|
2019-11-19 20:15:12 +08:00
|
|
|
if (!MO.isReg() || !MO.getReg() || !MO.isDef() || MO.isDead())
|
2016-06-23 06:16:51 +08:00
|
|
|
continue;
|
|
|
|
if (!NC.getNotNullSucc()->isLiveIn(MO.getReg()))
|
|
|
|
NC.getNotNullSucc()->addLiveIn(MO.getReg());
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-06-21 10:10:18 +08:00
|
|
|
NC.getMemOperation()->eraseFromParent();
|
|
|
|
NC.getCheckOperation()->eraseFromParent();
|
2015-06-16 02:44:27 +08:00
|
|
|
|
|
|
|
// Insert an *unconditional* branch to not-null successor.
|
2016-09-15 01:24:15 +08:00
|
|
|
TII->insertBranch(*NC.getCheckBlock(), NC.getNotNullSucc(), nullptr,
|
2016-06-21 10:10:18 +08:00
|
|
|
/*Cond=*/None, DL);
|
2015-06-16 02:44:27 +08:00
|
|
|
|
2015-07-07 07:32:10 +08:00
|
|
|
NumImplicitNullChecks++;
|
2015-06-16 02:44:27 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
char ImplicitNullChecks::ID = 0;
|
2017-08-30 06:32:07 +08:00
|
|
|
|
2015-06-16 02:44:27 +08:00
|
|
|
char &llvm::ImplicitNullChecksID = ImplicitNullChecks::ID;
|
2017-08-30 06:32:07 +08:00
|
|
|
|
2017-05-26 05:26:32 +08:00
|
|
|
INITIALIZE_PASS_BEGIN(ImplicitNullChecks, DEBUG_TYPE,
|
2015-06-16 02:44:27 +08:00
|
|
|
"Implicit null checks", false, false)
|
2016-06-23 06:16:51 +08:00
|
|
|
INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)
|
2017-05-26 05:26:32 +08:00
|
|
|
INITIALIZE_PASS_END(ImplicitNullChecks, DEBUG_TYPE,
|
2015-06-16 02:44:27 +08:00
|
|
|
"Implicit null checks", false, false)
|