2017-09-29 06:27:25 +08:00
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=avx2 | FileCheck %s --check-prefix=X32_AVX256
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx2 | FileCheck %s --check-prefix=X64_AVX256
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; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=avx512f | FileCheck %s --check-prefix=X32_AVX512
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx512f | FileCheck %s --check-prefix=X64_AVX512
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define <8 x float> @insert_subvector_256(i16 %x0, i16 %x1, <8 x float> %v) nounwind {
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; X32_AVX256-LABEL: insert_subvector_256:
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; X32_AVX256: # BB#0:
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; X32_AVX256-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero
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; X32_AVX256-NEXT: vpinsrw $1, {{[0-9]+}}(%esp), %xmm1, %xmm1
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[DAGCombiner] convert insertelement of bitcasted vector into shuffle
Eg:
insert v4i32 V, (v2i16 X), 2 --> shuffle v8i16 V', X', {0,1,2,3,8,9,6,7}
This is a generalization of the IR fold in D38316 to handle insertion into a non-undef vector.
We may want to abandon that one if we can't find value in squashing the more specific pattern sooner.
We're using the existing legal shuffle target hook to avoid AVX512 horror with vXi1 shuffles.
There may be room for improvement in the shuffle lowering here, but that would be follow-up work.
Differential Revision: https://reviews.llvm.org/D38388
llvm-svn: 315460
2017-10-11 22:12:16 +08:00
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; X32_AVX256-NEXT: vpbroadcastd %xmm1, %xmm1
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; X32_AVX256-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2,3,4,5,6,7]
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2017-09-29 06:27:25 +08:00
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; X32_AVX256-NEXT: retl
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;
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; X64_AVX256-LABEL: insert_subvector_256:
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; X64_AVX256: # BB#0:
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; X64_AVX256-NEXT: vmovd %edi, %xmm1
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; X64_AVX256-NEXT: vpinsrw $1, %esi, %xmm1, %xmm1
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[DAGCombiner] convert insertelement of bitcasted vector into shuffle
Eg:
insert v4i32 V, (v2i16 X), 2 --> shuffle v8i16 V', X', {0,1,2,3,8,9,6,7}
This is a generalization of the IR fold in D38316 to handle insertion into a non-undef vector.
We may want to abandon that one if we can't find value in squashing the more specific pattern sooner.
We're using the existing legal shuffle target hook to avoid AVX512 horror with vXi1 shuffles.
There may be room for improvement in the shuffle lowering here, but that would be follow-up work.
Differential Revision: https://reviews.llvm.org/D38388
llvm-svn: 315460
2017-10-11 22:12:16 +08:00
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; X64_AVX256-NEXT: vpbroadcastd %xmm1, %xmm1
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; X64_AVX256-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2,3,4,5,6,7]
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2017-09-29 06:27:25 +08:00
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; X64_AVX256-NEXT: retq
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;
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; X32_AVX512-LABEL: insert_subvector_256:
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; X32_AVX512: # BB#0:
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; X32_AVX512-NEXT: vmovd {{.*#+}} xmm1 = mem[0],zero,zero,zero
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; X32_AVX512-NEXT: vpinsrw $1, {{[0-9]+}}(%esp), %xmm1, %xmm1
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[DAGCombiner] convert insertelement of bitcasted vector into shuffle
Eg:
insert v4i32 V, (v2i16 X), 2 --> shuffle v8i16 V', X', {0,1,2,3,8,9,6,7}
This is a generalization of the IR fold in D38316 to handle insertion into a non-undef vector.
We may want to abandon that one if we can't find value in squashing the more specific pattern sooner.
We're using the existing legal shuffle target hook to avoid AVX512 horror with vXi1 shuffles.
There may be room for improvement in the shuffle lowering here, but that would be follow-up work.
Differential Revision: https://reviews.llvm.org/D38388
llvm-svn: 315460
2017-10-11 22:12:16 +08:00
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; X32_AVX512-NEXT: vpbroadcastd %xmm1, %xmm1
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; X32_AVX512-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2,3,4,5,6,7]
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2017-09-29 06:27:25 +08:00
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; X32_AVX512-NEXT: retl
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;
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; X64_AVX512-LABEL: insert_subvector_256:
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; X64_AVX512: # BB#0:
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; X64_AVX512-NEXT: vmovd %edi, %xmm1
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; X64_AVX512-NEXT: vpinsrw $1, %esi, %xmm1, %xmm1
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[DAGCombiner] convert insertelement of bitcasted vector into shuffle
Eg:
insert v4i32 V, (v2i16 X), 2 --> shuffle v8i16 V', X', {0,1,2,3,8,9,6,7}
This is a generalization of the IR fold in D38316 to handle insertion into a non-undef vector.
We may want to abandon that one if we can't find value in squashing the more specific pattern sooner.
We're using the existing legal shuffle target hook to avoid AVX512 horror with vXi1 shuffles.
There may be room for improvement in the shuffle lowering here, but that would be follow-up work.
Differential Revision: https://reviews.llvm.org/D38388
llvm-svn: 315460
2017-10-11 22:12:16 +08:00
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; X64_AVX512-NEXT: vpbroadcastd %xmm1, %xmm1
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; X64_AVX512-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0],ymm1[1],ymm0[2,3,4,5,6,7]
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2017-09-29 06:27:25 +08:00
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; X64_AVX512-NEXT: retq
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%ins1 = insertelement <2 x i16> undef, i16 %x0, i32 0
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%ins2 = insertelement <2 x i16> %ins1, i16 %x1, i32 1
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%bc = bitcast <2 x i16> %ins2 to float
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%ins3 = insertelement <8 x float> %v, float %bc, i32 1
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ret <8 x float> %ins3
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}
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define <8 x i64> @insert_subvector_512(i32 %x0, i32 %x1, <8 x i64> %v) nounwind {
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; X32_AVX256-LABEL: insert_subvector_512:
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; X32_AVX256: # BB#0:
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; X32_AVX256-NEXT: pushl %ebp
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; X32_AVX256-NEXT: movl %esp, %ebp
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; X32_AVX256-NEXT: andl $-8, %esp
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; X32_AVX256-NEXT: subl $8, %esp
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; X32_AVX256-NEXT: vmovsd {{.*#+}} xmm2 = mem[0],zero
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; X32_AVX256-NEXT: vmovlps %xmm2, (%esp)
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; X32_AVX256-NEXT: vextracti128 $1, %ymm0, %xmm2
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; X32_AVX256-NEXT: vpinsrd $0, (%esp), %xmm2, %xmm2
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; X32_AVX256-NEXT: vpinsrd $1, {{[0-9]+}}(%esp), %xmm2, %xmm2
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; X32_AVX256-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm0
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; X32_AVX256-NEXT: movl %ebp, %esp
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; X32_AVX256-NEXT: popl %ebp
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; X32_AVX256-NEXT: retl
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;
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; X64_AVX256-LABEL: insert_subvector_512:
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; X64_AVX256: # BB#0:
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; X64_AVX256-NEXT: vmovd %edi, %xmm2
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; X64_AVX256-NEXT: vpinsrd $1, %esi, %xmm2, %xmm2
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; X64_AVX256-NEXT: vmovq %xmm2, %rax
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; X64_AVX256-NEXT: vextracti128 $1, %ymm0, %xmm2
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; X64_AVX256-NEXT: vpinsrq $0, %rax, %xmm2, %xmm2
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; X64_AVX256-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm0
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; X64_AVX256-NEXT: retq
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;
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; X32_AVX512-LABEL: insert_subvector_512:
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; X32_AVX512: # BB#0:
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[DAGCombiner] convert insertelement of bitcasted vector into shuffle
Eg:
insert v4i32 V, (v2i16 X), 2 --> shuffle v8i16 V', X', {0,1,2,3,8,9,6,7}
This is a generalization of the IR fold in D38316 to handle insertion into a non-undef vector.
We may want to abandon that one if we can't find value in squashing the more specific pattern sooner.
We're using the existing legal shuffle target hook to avoid AVX512 horror with vXi1 shuffles.
There may be room for improvement in the shuffle lowering here, but that would be follow-up work.
Differential Revision: https://reviews.llvm.org/D38388
llvm-svn: 315460
2017-10-11 22:12:16 +08:00
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; X32_AVX512-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero
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; X32_AVX512-NEXT: vmovdqa64 {{.*#+}} zmm2 = [0,0,1,0,8,0,3,0,4,0,5,0,6,0,7,0]
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; X32_AVX512-NEXT: vpermt2q %zmm1, %zmm2, %zmm0
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2017-09-29 06:27:25 +08:00
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; X32_AVX512-NEXT: retl
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;
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; X64_AVX512-LABEL: insert_subvector_512:
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; X64_AVX512: # BB#0:
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; X64_AVX512-NEXT: vmovd %edi, %xmm1
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; X64_AVX512-NEXT: vpinsrd $1, %esi, %xmm1, %xmm1
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[DAGCombiner] convert insertelement of bitcasted vector into shuffle
Eg:
insert v4i32 V, (v2i16 X), 2 --> shuffle v8i16 V', X', {0,1,2,3,8,9,6,7}
This is a generalization of the IR fold in D38316 to handle insertion into a non-undef vector.
We may want to abandon that one if we can't find value in squashing the more specific pattern sooner.
We're using the existing legal shuffle target hook to avoid AVX512 horror with vXi1 shuffles.
There may be room for improvement in the shuffle lowering here, but that would be follow-up work.
Differential Revision: https://reviews.llvm.org/D38388
llvm-svn: 315460
2017-10-11 22:12:16 +08:00
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; X64_AVX512-NEXT: vmovdqa64 {{.*#+}} zmm2 = [0,1,8,3,4,5,6,7]
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; X64_AVX512-NEXT: vpermt2q %zmm1, %zmm2, %zmm0
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2017-09-29 06:27:25 +08:00
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; X64_AVX512-NEXT: retq
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%ins1 = insertelement <2 x i32> undef, i32 %x0, i32 0
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%ins2 = insertelement <2 x i32> %ins1, i32 %x1, i32 1
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%bc = bitcast <2 x i32> %ins2 to i64
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%ins3 = insertelement <8 x i64> %v, i64 %bc, i32 2
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ret <8 x i64> %ins3
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}
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; PR34716 - https://bugs.llvm.org/show_bug.cgi?id=34716
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; Special case: if we're inserting into an undef vector, we can optimize more.
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define <8 x i64> @insert_subvector_into_undef(i32 %x0, i32 %x1) nounwind {
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; X32_AVX256-LABEL: insert_subvector_into_undef:
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; X32_AVX256: # BB#0:
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; X32_AVX256-NEXT: pushl %ebp
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; X32_AVX256-NEXT: movl %esp, %ebp
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; X32_AVX256-NEXT: andl $-8, %esp
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; X32_AVX256-NEXT: subl $8, %esp
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; X32_AVX256-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
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; X32_AVX256-NEXT: vmovlps %xmm0, (%esp)
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; X32_AVX256-NEXT: movl (%esp), %eax
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; X32_AVX256-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X32_AVX256-NEXT: vmovd %eax, %xmm0
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; X32_AVX256-NEXT: vpinsrd $1, %ecx, %xmm0, %xmm0
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; X32_AVX256-NEXT: vpinsrd $2, %eax, %xmm0, %xmm0
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; X32_AVX256-NEXT: vpinsrd $3, %ecx, %xmm0, %xmm0
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; X32_AVX256-NEXT: vinserti128 $1, %xmm0, %ymm0, %ymm0
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; X32_AVX256-NEXT: vmovdqa %ymm0, %ymm1
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; X32_AVX256-NEXT: movl %ebp, %esp
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; X32_AVX256-NEXT: popl %ebp
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; X32_AVX256-NEXT: retl
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;
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; X64_AVX256-LABEL: insert_subvector_into_undef:
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; X64_AVX256: # BB#0:
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; X64_AVX256-NEXT: vmovd %edi, %xmm0
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; X64_AVX256-NEXT: vpinsrd $1, %esi, %xmm0, %xmm0
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; X64_AVX256-NEXT: vpbroadcastq %xmm0, %ymm0
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; X64_AVX256-NEXT: vmovdqa %ymm0, %ymm1
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; X64_AVX256-NEXT: retq
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;
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; X32_AVX512-LABEL: insert_subvector_into_undef:
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; X32_AVX512: # BB#0:
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; X32_AVX512-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
|
[DAGCombiner] convert insertelement of bitcasted vector into shuffle
Eg:
insert v4i32 V, (v2i16 X), 2 --> shuffle v8i16 V', X', {0,1,2,3,8,9,6,7}
This is a generalization of the IR fold in D38316 to handle insertion into a non-undef vector.
We may want to abandon that one if we can't find value in squashing the more specific pattern sooner.
We're using the existing legal shuffle target hook to avoid AVX512 horror with vXi1 shuffles.
There may be room for improvement in the shuffle lowering here, but that would be follow-up work.
Differential Revision: https://reviews.llvm.org/D38388
llvm-svn: 315460
2017-10-11 22:12:16 +08:00
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; X32_AVX512-NEXT: vbroadcastsd %xmm0, %zmm0
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2017-09-29 06:27:25 +08:00
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; X32_AVX512-NEXT: retl
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;
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; X64_AVX512-LABEL: insert_subvector_into_undef:
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; X64_AVX512: # BB#0:
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; X64_AVX512-NEXT: vmovd %edi, %xmm0
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; X64_AVX512-NEXT: vpinsrd $1, %esi, %xmm0, %xmm0
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; X64_AVX512-NEXT: vpbroadcastq %xmm0, %zmm0
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; X64_AVX512-NEXT: retq
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%ins1 = insertelement <2 x i32> undef, i32 %x0, i32 0
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%ins2 = insertelement <2 x i32> %ins1, i32 %x1, i32 1
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%bc = bitcast <2 x i32> %ins2 to i64
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%ins3 = insertelement <8 x i64> undef, i64 %bc, i32 0
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%splat = shufflevector <8 x i64> %ins3, <8 x i64> undef, <8 x i32> zeroinitializer
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ret <8 x i64> %splat
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}
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