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llvm-project/llvm/test/CodeGen/PowerPC/2008-10-28-f128-i32.ll

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Eliminate more uses of llvm-as and llvm-dis. llvm-svn: 81293
2009-09-09 08:09:15 +08:00
; RUN: llc < %s -march=ppc32 -o - | not grep fixunstfsi
Fix darwin ppc llvm-gcc build breakage: intercept ppcf128 to i32 conversion and expand it into a code sequence like in LegalizeDAG. This needs custom ppc lowering of FP_ROUND_INREG, so turn that on and make it work with LegalizeTypes. Probably PPC should simply custom lower the original conversion. llvm-svn: 58329
2008-10-28 23:00:32 +08:00
define i64 @__fixunstfdi(ppc_fp128 %a) nounwind readnone {
entry:
%0 = fcmp olt ppc_fp128 %a, 0xM00000000000000000000000000000000 ; <i1> [#uses=1]
br i1 %0, label %bb5, label %bb1
bb1: ; preds = %entry
Split the Add, Sub, and Mul instruction opcodes into separate integer and floating-point opcodes, introducing FAdd, FSub, and FMul. For now, the AsmParser, BitcodeReader, and IRBuilder all preserve backwards compatability, and the Core LLVM APIs preserve backwards compatibility for IR producers. Most front-ends won't need to change immediately. This implements the first step of the plan outlined here: http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt llvm-svn: 72897
2009-06-05 06:49:04 +08:00
%1 = fmul ppc_fp128 %a, 0xM3DF00000000000000000000000000000 ; <ppc_fp128> [#uses=1]
Fix darwin ppc llvm-gcc build breakage: intercept ppcf128 to i32 conversion and expand it into a code sequence like in LegalizeDAG. This needs custom ppc lowering of FP_ROUND_INREG, so turn that on and make it work with LegalizeTypes. Probably PPC should simply custom lower the original conversion. llvm-svn: 58329
2008-10-28 23:00:32 +08:00
%2 = fptoui ppc_fp128 %1 to i32 ; <i32> [#uses=1]
%3 = zext i32 %2 to i64 ; <i64> [#uses=1]
%4 = shl i64 %3, 32 ; <i64> [#uses=3]
%5 = uitofp i64 %4 to ppc_fp128 ; <ppc_fp128> [#uses=1]
Split the Add, Sub, and Mul instruction opcodes into separate integer and floating-point opcodes, introducing FAdd, FSub, and FMul. For now, the AsmParser, BitcodeReader, and IRBuilder all preserve backwards compatability, and the Core LLVM APIs preserve backwards compatibility for IR producers. Most front-ends won't need to change immediately. This implements the first step of the plan outlined here: http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt llvm-svn: 72897
2009-06-05 06:49:04 +08:00
%6 = fsub ppc_fp128 %a, %5 ; <ppc_fp128> [#uses=3]
Fix darwin ppc llvm-gcc build breakage: intercept ppcf128 to i32 conversion and expand it into a code sequence like in LegalizeDAG. This needs custom ppc lowering of FP_ROUND_INREG, so turn that on and make it work with LegalizeTypes. Probably PPC should simply custom lower the original conversion. llvm-svn: 58329
2008-10-28 23:00:32 +08:00
%7 = fcmp olt ppc_fp128 %6, 0xM00000000000000000000000000000000 ; <i1> [#uses=1]
br i1 %7, label %bb2, label %bb3
bb2: ; preds = %bb1
Split the Add, Sub, and Mul instruction opcodes into separate integer and floating-point opcodes, introducing FAdd, FSub, and FMul. For now, the AsmParser, BitcodeReader, and IRBuilder all preserve backwards compatability, and the Core LLVM APIs preserve backwards compatibility for IR producers. Most front-ends won't need to change immediately. This implements the first step of the plan outlined here: http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt llvm-svn: 72897
2009-06-05 06:49:04 +08:00
%8 = fsub ppc_fp128 0xM80000000000000000000000000000000, %6 ; <ppc_fp128> [#uses=1]
Fix darwin ppc llvm-gcc build breakage: intercept ppcf128 to i32 conversion and expand it into a code sequence like in LegalizeDAG. This needs custom ppc lowering of FP_ROUND_INREG, so turn that on and make it work with LegalizeTypes. Probably PPC should simply custom lower the original conversion. llvm-svn: 58329
2008-10-28 23:00:32 +08:00
%9 = fptoui ppc_fp128 %8 to i32 ; <i32> [#uses=1]
%10 = zext i32 %9 to i64 ; <i64> [#uses=1]
%11 = sub i64 %4, %10 ; <i64> [#uses=1]
ret i64 %11
bb3: ; preds = %bb1
%12 = fptoui ppc_fp128 %6 to i32 ; <i32> [#uses=1]
%13 = zext i32 %12 to i64 ; <i64> [#uses=1]
%14 = or i64 %13, %4 ; <i64> [#uses=1]
ret i64 %14
bb5: ; preds = %entry
ret i64 0
}