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llvm-project/llvm/lib/Target/Hexagon/HexagonInstrInfo.h

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[Hexagon] Use constant extenders to fix up hardware loops Use a loop instruction with a constant extender for a hardware loop instruction that is too far away from the start of the loop. This is cheaper than changing the SA register value. Differential Revision: http://reviews.llvm.org/D9262 llvm-svn: 235882
2015-04-27 22:16:43 +08:00
Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. llvm-svn: 150878
2012-02-18 20:03:15 +08:00
//===- HexagonInstrInfo.h - Hexagon Instruction Information -----*- C++ -*-===//
Hexagon backend support llvm-svn: 146412
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//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file contains the Hexagon implementation of the TargetInstrInfo class.
//
//===----------------------------------------------------------------------===//
Canonicalize header guards into a common format. Add header guards to files that were missing guards. Remove #endif comments as they don't seem common in LLVM (we can easily add them back if we decide they're useful) Changes made by clang-tidy with minor tweaks. llvm-svn: 215558
2014-08-14 00:26:38 +08:00
#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONINSTRINFO_H
#define LLVM_LIB_TARGET_HEXAGON_HEXAGONINSTRINFO_H
Hexagon backend support llvm-svn: 146412
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Reorder includes in Target backends to following coding standards. Remove some superfluous forward declarations. llvm-svn: 152997
2012-03-18 02:46:09 +08:00
#include "HexagonRegisterInfo.h"
Use TSFlag bit to describe instruction properties. Creating the isPredicated TSFlag enables the code to use the property defined in the instruction format instead of using a large switch statement. llvm-svn: 150078
2012-02-09 02:25:47 +08:00
#include "MCTargetDesc/HexagonBaseInfo.h"
Hexagon: Honor __builtin_expect by using branch probabilities. * lib/Target/Hexagon/HexagonInstrInfo.cpp (GetDotNewPredOp): Given a jump opcode return the right pred.new jump opcode with a taken vs not-taken hint based on branch probabilities provided by the target independent module. * lib/Target/Hexagon/HexagonVLIWPacketizer.cpp: Use the above function. * lib/Target/Hexagon/HexagonNewValueJump.cpp(getNewvalueJumpOpcode): Enhance existing function use branch probabilities like HexagonInstrInfo::GetDotNewPredOp but for New Value (GPR) Jumps. llvm-svn: 180923
2013-05-02 23:39:30 +08:00
#include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
Re-sort all of the includes with ./utils/sort_includes.py so that subsequent changes are easier to review. About to fix some layering issues, and wanted to separate out the necessary churn. Also comment and sink the include of "Windows.h" in three .inc files to match the usage in Memory.inc. llvm-svn: 198685
2014-01-07 19:48:04 +08:00
#include "llvm/Target/TargetFrameLowering.h"
#include "llvm/Target/TargetInstrInfo.h"
Hexagon backend support llvm-svn: 146412
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#define GET_INSTRINFO_HEADER
#include "HexagonGenInstrInfo.inc"
namespace llvm {
Replace ValueTypes.h with MachineValueType.h if possible. Utilize the previous move of MVT to a separate header for all trivial cases (that don't need any further restructuring). Reviewed By: Tim Northover llvm-svn: 204003
2014-03-15 17:11:41 +08:00
struct EVT;
Remove some unnecessary forward declarations and put a couple more where they're supposed to reside. llvm-svn: 232014
2015-03-12 14:07:16 +08:00
class HexagonSubtarget;
Hexagon backend support llvm-svn: 146412
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class HexagonInstrInfo : public HexagonGenInstrInfo {
[weak vtables] Remove a bunch of weak vtables This patch removes most of the trivial cases of weak vtables by pinning them to a single object file. The memory leaks in this version have been fixed. Thanks Alexey for pointing them out. Differential Revision: http://llvm-reviews.chandlerc.com/D2068 Reviewed by Andy llvm-svn: 195064
2013-11-19 08:57:56 +08:00
virtual void anchor();
Hexagon backend support llvm-svn: 146412
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const HexagonRegisterInfo RI;
Don't cache the instruction and register info from the TargetMachine, because the internals of TargetMachine could change. llvm-svn: 183490
2013-06-07 14:19:56 +08:00
const HexagonSubtarget &Subtarget;
Hexagon: Use multiclass for Jump instructions. llvm-svn: 180885
2013-05-02 05:37:34 +08:00
Hexagon backend support llvm-svn: 146412
2011-12-13 05:14:40 +08:00
public:
[Hexagon] Update AnalyzeBranch, etc target hooks Improved the AnalyzeBranch, InsertBranch, and RemoveBranch functions in order to handle more of our branch instructions. This requires changes to analyzeCompare and PredicateInstructions. Specifically, we've added support for new value compare jumps, improved handling of endloop, added more compare instructions, and improved support for predicate instructions. Differential Revision: http://reviews.llvm.org/D9559 llvm-svn: 236876
2015-05-09 00:16:29 +08:00
typedef unsigned Opcode_t;
Hexagon backend support llvm-svn: 146412
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explicit HexagonInstrInfo(HexagonSubtarget &ST);
/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
/// such, whenever a client has an instance of instruction info, it should
/// always be able to get register info as well (through this method).
///
[C++11] Add 'override' keywords and remove 'virtual'. Additionally add 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. Hexagon edition llvm-svn: 207508
2014-04-29 15:58:16 +08:00
const HexagonRegisterInfo &getRegisterInfo() const { return RI; }
Hexagon backend support llvm-svn: 146412
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/// isLoadFromStackSlot - If the specified machine instruction is a direct
/// load from a stack slot, return the virtual or physical register number of
/// the destination along with the FrameIndex of the loaded stack slot. If
/// not, return 0. This predicate must return 0 if the instruction has
/// any side effects other than loading from the stack slot.
[C++11] Add 'override' keywords and remove 'virtual'. Additionally add 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. Hexagon edition llvm-svn: 207508
2014-04-29 15:58:16 +08:00
unsigned isLoadFromStackSlot(const MachineInstr *MI,
int &FrameIndex) const override;
Hexagon backend support llvm-svn: 146412
2011-12-13 05:14:40 +08:00
/// isStoreToStackSlot - If the specified machine instruction is a direct
/// store to a stack slot, return the virtual or physical register number of
/// the source reg along with the FrameIndex of the loaded stack slot. If
/// not, return 0. This predicate must return 0 if the instruction has
/// any side effects other than storing to the stack slot.
[C++11] Add 'override' keywords and remove 'virtual'. Additionally add 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. Hexagon edition llvm-svn: 207508
2014-04-29 15:58:16 +08:00
unsigned isStoreToStackSlot(const MachineInstr *MI,
int &FrameIndex) const override;
bool AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
MachineBasicBlock *&FBB,
SmallVectorImpl<MachineOperand> &Cond,
bool AllowModify) const override;
unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB,
const SmallVectorImpl<MachineOperand> &Cond,
DebugLoc DL) const override;
bool analyzeCompare(const MachineInstr *MI,
unsigned &SrcReg, unsigned &SrcReg2,
int &Mask, int &Value) const override;
void copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I, DebugLoc DL,
unsigned DestReg, unsigned SrcReg,
bool KillSrc) const override;
void storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
unsigned SrcReg, bool isKill, int FrameIndex,
const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI) const override;
void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
SmallVectorImpl<MachineOperand> &Addr,
const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const;
void loadRegFromStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
unsigned DestReg, int FrameIndex,
const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI) const override;
void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
SmallVectorImpl<MachineOperand> &Addr,
const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const;
[Hexagon] Use single tailcall pseudoinst and fix checking for label jumping versus tail calling. llvm-svn: 231713
2015-03-10 06:05:21 +08:00
/// expandPostRAPseudo - This function is called for all pseudo instructions
/// that remain after register allocation. Many pseudo instructions are
/// created to help register allocation. This is the place to convert them
/// into real instructions. The target can edit MI in place, or it can insert
/// new instructions and erase MI. The function should return true if
/// anything was changed.
bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override;
ArrayRefize memory operand folding. NFC. llvm-svn: 230846
2015-02-28 20:04:00 +08:00
MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
ArrayRef<unsigned> Ops,
[InstrInfo] Refactor foldOperandImpl to thread through InsertPt. NFC Summary: This was a longstanding FIXME and is a necessary precursor to cases where foldOperandImpl may have to create more than one instruction (e.g. to constrain a register class). This is the split out NFC changes from D6262. Reviewers: pete, ributzka, uweigand, mcrosier Reviewed By: mcrosier Subscribers: mcrosier, ted, llvm-commits Differential Revision: http://reviews.llvm.org/D10174 llvm-svn: 239336
2015-06-09 04:09:58 +08:00
MachineBasicBlock::iterator InsertPt,
[C++11] Add 'override' keywords and remove 'virtual'. Additionally add 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. Hexagon edition llvm-svn: 207508
2014-04-29 15:58:16 +08:00
int FrameIndex) const override;
ArrayRefize memory operand folding. NFC. llvm-svn: 230846
2015-02-28 20:04:00 +08:00
MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
ArrayRef<unsigned> Ops,
[InstrInfo] Refactor foldOperandImpl to thread through InsertPt. NFC Summary: This was a longstanding FIXME and is a necessary precursor to cases where foldOperandImpl may have to create more than one instruction (e.g. to constrain a register class). This is the split out NFC changes from D6262. Reviewers: pete, ributzka, uweigand, mcrosier Reviewed By: mcrosier Subscribers: mcrosier, ted, llvm-commits Differential Revision: http://reviews.llvm.org/D10174 llvm-svn: 239336
2015-06-09 04:09:58 +08:00
MachineBasicBlock::iterator InsertPt,
ArrayRefize memory operand folding. NFC. llvm-svn: 230846
2015-02-28 20:04:00 +08:00
MachineInstr *LoadMI) const override {
[C++] Use 'nullptr'. llvm-svn: 207394
2014-04-28 12:05:08 +08:00
return nullptr;
Hexagon backend support llvm-svn: 146412
2011-12-13 05:14:40 +08:00
}
unsigned createVR(MachineFunction* MF, MVT VT) const;
[C++11] Add 'override' keywords and remove 'virtual'. Additionally add 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. Hexagon edition llvm-svn: 207508
2014-04-29 15:58:16 +08:00
bool isBranch(const MachineInstr *MI) const;
bool isPredicable(MachineInstr *MI) const override;
bool PredicateInstruction(MachineInstr *MI,
const SmallVectorImpl<MachineOperand> &Cond) const override;
bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
unsigned ExtraPredCycles,
const BranchProbability &Probability) const override;
bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
unsigned NumTCycles, unsigned ExtraTCycles,
MachineBasicBlock &FMBB,
unsigned NumFCycles, unsigned ExtraFCycles,
const BranchProbability &Probability) const override;
bool isPredicated(const MachineInstr *MI) const override;
bool isPredicated(unsigned Opcode) const;
bool isPredicatedTrue(const MachineInstr *MI) const;
bool isPredicatedTrue(unsigned Opcode) const;
bool isPredicatedNew(const MachineInstr *MI) const;
bool isPredicatedNew(unsigned Opcode) const;
bool DefinesPredicate(MachineInstr *MI,
std::vector<MachineOperand> &Pred) const override;
bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
const SmallVectorImpl<MachineOperand> &Pred2) const override;
bool
ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
const BranchProbability &Probability) const override;
Remove unused argument to CreateTargetScheduleState and change the TargetMachine to a TargetSubtargetInfo since everything we wanted is off of that. llvm-svn: 219382
2014-10-09 09:59:35 +08:00
DFAPacketizer *
CreateTargetScheduleState(const TargetSubtargetInfo &STI) const override;
VLIW specific scheduler framework that utilizes deterministic finite automaton (DFA). This new scheduler plugs into the existing selection DAG scheduling framework. It is a top-down critical path scheduler that tracks register pressure and uses a DFA for pipeline modeling. Patch by Sergei Larin! llvm-svn: 149547
2012-02-02 06:13:57 +08:00
[C++11] Add 'override' keywords and remove 'virtual'. Additionally add 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. Hexagon edition llvm-svn: 207508
2014-04-29 15:58:16 +08:00
bool isSchedulingBoundary(const MachineInstr *MI,
const MachineBasicBlock *MBB,
const MachineFunction &MF) const override;
[Hexagon] Consider constant-extended offsets to be valid llvm-svn: 235529
2015-04-23 01:51:26 +08:00
bool isValidOffset(unsigned Opcode, int Offset, bool Extend = true) const;
Hexagon backend support llvm-svn: 146412
2011-12-13 05:14:40 +08:00
bool isValidAutoIncImm(const EVT VT, const int Offset) const;
bool isMemOp(const MachineInstr *MI) const;
bool isSpillPredRegOp(const MachineInstr *MI) const;
bool isU6_3Immediate(const int value) const;
bool isU6_2Immediate(const int value) const;
bool isU6_1Immediate(const int value) const;
bool isU6_0Immediate(const int value) const;
bool isS4_3Immediate(const int value) const;
bool isS4_2Immediate(const int value) const;
bool isS4_1Immediate(const int value) const;
bool isS4_0Immediate(const int value) const;
bool isS12_Immediate(const int value) const;
bool isU6_Immediate(const int value) const;
bool isS8_Immediate(const int value) const;
bool isS6_Immediate(const int value) const;
Support for target dependent Hexagon VLIW packetizer. This patch creates and optimizes packets as per Hexagon ISA rules. llvm-svn: 156109
2012-05-04 05:52:53 +08:00
bool isSaveCalleeSavedRegsCall(const MachineInstr* MI) const;
bool isConditionalTransfer(const MachineInstr* MI) const;
Revert r155365, r155366, and r155367. All three of these have regression test suite failures. The failures occur at each stage, and only get worse, so I'm reverting all of them. Please resubmit these patches, one at a time, after verifying that the regression test suite passes. Never submit a patch without running the regression test suite. llvm-svn: 155372
2012-04-24 02:25:57 +08:00
bool isConditionalALU32 (const MachineInstr* MI) const;
bool isConditionalLoad (const MachineInstr* MI) const;
Support for target dependent Hexagon VLIW packetizer. This patch creates and optimizes packets as per Hexagon ISA rules. llvm-svn: 156109
2012-05-04 05:52:53 +08:00
bool isConditionalStore(const MachineInstr* MI) const;
Hexagon: Use MO operand flags to mark constant extended instructions. llvm-svn: 176500
2013-03-06 02:51:42 +08:00
bool isNewValueInst(const MachineInstr* MI) const;
Hexagon: Add multiclass/encoding bits for the New-Value Jump instructions. llvm-svn: 181235
2013-05-07 02:49:23 +08:00
bool isNewValue(const MachineInstr* MI) const;
[Hexagon] Update AnalyzeBranch, etc target hooks Improved the AnalyzeBranch, InsertBranch, and RemoveBranch functions in order to handle more of our branch instructions. This requires changes to analyzeCompare and PredicateInstructions. Specifically, we've added support for new value compare jumps, improved handling of endloop, added more compare instructions, and improved support for predicate instructions. Differential Revision: http://reviews.llvm.org/D9559 llvm-svn: 236876
2015-05-09 00:16:29 +08:00
bool isNewValue(Opcode_t Opcode) const;
Hexagon: Replace switch-case in isDotNewInst with TSFlags. llvm-svn: 178281
2013-03-29 03:44:04 +08:00
bool isDotNewInst(const MachineInstr* MI) const;
Hexagon: Fix switch statements in GetDotOldOp and IsNewifyStore. No functionality change. llvm-svn: 181628
2013-05-11 04:58:11 +08:00
int GetDotOldOp(const int opc) const;
Hexagon: Fix switch cases in HexagonVLIWPacketizer.cpp. llvm-svn: 181624
2013-05-11 04:27:34 +08:00
int GetDotNewOp(const MachineInstr* MI) const;
Hexagon: Remove switch cases from GetDotNewPredOp and isPostIncrement functions. No functionality change. llvm-svn: 181535
2013-05-10 03:16:07 +08:00
int GetDotNewPredOp(MachineInstr *MI,
const MachineBranchProbabilityInfo
*MBPI) const;
Hexagon: Fix switch statements in GetDotOldOp and IsNewifyStore. No functionality change. llvm-svn: 181628
2013-05-11 04:58:11 +08:00
bool mayBeNewStore(const MachineInstr* MI) const;
Hexagon backend support llvm-svn: 146412
2011-12-13 05:14:40 +08:00
bool isDeallocRet(const MachineInstr *MI) const;
Revert r155365, r155366, and r155367. All three of these have regression test suite failures. The failures occur at each stage, and only get worse, so I'm reverting all of them. Please resubmit these patches, one at a time, after verifying that the regression test suite passes. Never submit a patch without running the regression test suite. llvm-svn: 155372
2012-04-24 02:25:57 +08:00
unsigned getInvertedPredicatedOpcode(const int Opc) const;
Support for target dependent Hexagon VLIW packetizer. This patch creates and optimizes packets as per Hexagon ISA rules. llvm-svn: 156109
2012-05-04 05:52:53 +08:00
bool isExtendable(const MachineInstr* MI) const;
bool isExtended(const MachineInstr* MI) const;
bool isPostIncrement(const MachineInstr* MI) const;
bool isNewValueStore(const MachineInstr* MI) const;
Hexagon: Fix switch cases in HexagonVLIWPacketizer.cpp. llvm-svn: 181624
2013-05-11 04:27:34 +08:00
bool isNewValueStore(unsigned Opcode) const;
Support for target dependent Hexagon VLIW packetizer. This patch creates and optimizes packets as per Hexagon ISA rules. llvm-svn: 156109
2012-05-04 05:52:53 +08:00
bool isNewValueJump(const MachineInstr* MI) const;
[Hexagon] Update AnalyzeBranch, etc target hooks Improved the AnalyzeBranch, InsertBranch, and RemoveBranch functions in order to handle more of our branch instructions. This requires changes to analyzeCompare and PredicateInstructions. Specifically, we've added support for new value compare jumps, improved handling of endloop, added more compare instructions, and improved support for predicate instructions. Differential Revision: http://reviews.llvm.org/D9559 llvm-svn: 236876
2015-05-09 00:16:29 +08:00
bool isNewValueJump(Opcode_t Opcode) const;
Support for Hexagon feature, New Value Jump. llvm-svn: 156698
2012-05-12 13:10:30 +08:00
bool isNewValueJumpCandidate(const MachineInstr *MI) const;
Hexagon backend support llvm-svn: 146412
2011-12-13 05:14:40 +08:00
Hexagon: Add constant extender support framework. llvm-svn: 176358
2013-03-02 01:37:13 +08:00
void immediateExtend(MachineInstr *MI) const;
[Hexagon] Use constant extenders to fix up hardware loops Use a loop instruction with a constant extender for a hardware loop instruction that is too far away from the start of the loop. This is cheaper than changing the SA register value. Differential Revision: http://reviews.llvm.org/D9262 llvm-svn: 235882
2015-04-27 22:16:43 +08:00
bool isConstExtended(const MachineInstr *MI) const;
unsigned getSize(const MachineInstr *MI) const;
Hexagon: Honor __builtin_expect by using branch probabilities. * lib/Target/Hexagon/HexagonInstrInfo.cpp (GetDotNewPredOp): Given a jump opcode return the right pred.new jump opcode with a taken vs not-taken hint based on branch probabilities provided by the target independent module. * lib/Target/Hexagon/HexagonVLIWPacketizer.cpp: Use the above function. * lib/Target/Hexagon/HexagonNewValueJump.cpp(getNewvalueJumpOpcode): Enhance existing function use branch probabilities like HexagonInstrInfo::GetDotNewPredOp but for New Value (GPR) Jumps. llvm-svn: 180923
2013-05-02 23:39:30 +08:00
int getDotNewPredJumpOp(MachineInstr *MI,
const MachineBranchProbabilityInfo *MBPI) const;
Hexagon: Add constant extender support framework. llvm-svn: 176358
2013-03-02 01:37:13 +08:00
unsigned getAddrMode(const MachineInstr* MI) const;
bool isOperandExtended(const MachineInstr *MI,
unsigned short OperandNum) const;
unsigned short getCExtOpNum(const MachineInstr *MI) const;
int getMinValue(const MachineInstr *MI) const;
int getMaxValue(const MachineInstr *MI) const;
bool NonExtEquivalentExists (const MachineInstr *MI) const;
short getNonExtOpcode(const MachineInstr *MI) const;
Hexagon: Use multiclass for Jump instructions. llvm-svn: 180885
2013-05-02 05:37:34 +08:00
bool PredOpcodeHasJMP_c(Opcode_t Opcode) const;
[Hexagon] Update AnalyzeBranch, etc target hooks Improved the AnalyzeBranch, InsertBranch, and RemoveBranch functions in order to handle more of our branch instructions. This requires changes to analyzeCompare and PredicateInstructions. Specifically, we've added support for new value compare jumps, improved handling of endloop, added more compare instructions, and improved support for predicate instructions. Differential Revision: http://reviews.llvm.org/D9559 llvm-svn: 236876
2015-05-09 00:16:29 +08:00
bool predOpcodeHasNot(const SmallVectorImpl<MachineOperand> &Cond) const;
bool isEndLoopN(Opcode_t Opcode) const;
bool getPredReg(const SmallVectorImpl<MachineOperand> &Cond,
unsigned &PredReg, unsigned &PredRegPos,
unsigned &PredRegFlags) const;
Expand MUX instructions early on Hexagon This time with all files included. llvm-svn: 233696
2015-03-31 21:35:12 +08:00
int getCondOpcode(int Opc, bool sense) const;
Hexagon backend support llvm-svn: 146412
2011-12-13 05:14:40 +08:00
};
}
#endif