2010-12-08 11:26:16 +08:00
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//===-- RegAllocGreedy.cpp - greedy register allocator --------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the RAGreedy function pass for register allocation in
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// optimized builds.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "regalloc"
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#include "LiveIntervalUnion.h"
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#include "RegAllocBase.h"
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#include "Spiller.h"
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#include "VirtRegMap.h"
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#include "VirtRegRewriter.h"
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#include "llvm/Analysis/AliasAnalysis.h"
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#include "llvm/Function.h"
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#include "llvm/PassAnalysisSupport.h"
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#include "llvm/CodeGen/CalcSpillWeights.h"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "llvm/CodeGen/LiveStackAnalysis.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineLoopInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/RegAllocRegistry.h"
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#include "llvm/CodeGen/RegisterCoalescer.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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static RegisterRegAlloc greedyRegAlloc("greedy", "greedy register allocator",
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createGreedyRegisterAllocator);
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namespace {
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class RAGreedy : public MachineFunctionPass, public RegAllocBase {
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// context
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MachineFunction *MF;
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const TargetMachine *TM;
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MachineRegisterInfo *MRI;
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BitVector ReservedRegs;
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// analyses
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LiveStacks *LS;
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// state
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std::auto_ptr<Spiller> SpillerInstance;
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public:
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RAGreedy();
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/// Return the pass name.
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virtual const char* getPassName() const {
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return "Basic Register Allocator";
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}
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/// RAGreedy analysis usage.
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virtual void getAnalysisUsage(AnalysisUsage &AU) const;
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virtual void releaseMemory();
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virtual Spiller &spiller() { return *SpillerInstance; }
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2010-12-09 06:57:16 +08:00
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virtual float getPriority(LiveInterval *LI);
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2010-12-09 06:22:41 +08:00
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2010-12-08 11:26:16 +08:00
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virtual unsigned selectOrSplit(LiveInterval &VirtReg,
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SmallVectorImpl<LiveInterval*> &SplitVRegs);
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/// Perform register allocation.
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virtual bool runOnMachineFunction(MachineFunction &mf);
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static char ID;
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2010-12-10 02:15:21 +08:00
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private:
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bool reassignVReg(LiveInterval &InterferingVReg, unsigned OldPhysReg);
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bool reassignInterferences(LiveInterval &VirtReg, unsigned PhysReg);
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2010-12-08 11:26:16 +08:00
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};
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} // end anonymous namespace
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char RAGreedy::ID = 0;
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FunctionPass* llvm::createGreedyRegisterAllocator() {
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return new RAGreedy();
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}
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RAGreedy::RAGreedy(): MachineFunctionPass(ID) {
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initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
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initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
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initializeStrongPHIEliminationPass(*PassRegistry::getPassRegistry());
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initializeRegisterCoalescerAnalysisGroup(*PassRegistry::getPassRegistry());
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initializeCalculateSpillWeightsPass(*PassRegistry::getPassRegistry());
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initializeLiveStacksPass(*PassRegistry::getPassRegistry());
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initializeMachineDominatorTreePass(*PassRegistry::getPassRegistry());
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initializeMachineLoopInfoPass(*PassRegistry::getPassRegistry());
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initializeVirtRegMapPass(*PassRegistry::getPassRegistry());
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}
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void RAGreedy::getAnalysisUsage(AnalysisUsage &AU) const {
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AU.setPreservesCFG();
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AU.addRequired<AliasAnalysis>();
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AU.addPreserved<AliasAnalysis>();
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AU.addRequired<LiveIntervals>();
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AU.addPreserved<SlotIndexes>();
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if (StrongPHIElim)
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AU.addRequiredID(StrongPHIEliminationID);
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AU.addRequiredTransitive<RegisterCoalescer>();
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AU.addRequired<CalculateSpillWeights>();
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AU.addRequired<LiveStacks>();
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AU.addPreserved<LiveStacks>();
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AU.addRequiredID(MachineDominatorsID);
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AU.addPreservedID(MachineDominatorsID);
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AU.addRequired<MachineLoopInfo>();
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AU.addPreserved<MachineLoopInfo>();
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AU.addRequired<VirtRegMap>();
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AU.addPreserved<VirtRegMap>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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void RAGreedy::releaseMemory() {
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SpillerInstance.reset(0);
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RegAllocBase::releaseMemory();
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}
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2010-12-09 06:57:16 +08:00
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float RAGreedy::getPriority(LiveInterval *LI) {
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float Priority = LI->weight;
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// Prioritize hinted registers so they are allocated first.
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std::pair<unsigned, unsigned> Hint;
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if (Hint.first || Hint.second) {
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// The hint can be target specific, a virtual register, or a physreg.
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Priority *= 2;
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// Prefer physreg hints above anything else.
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if (Hint.first == 0 && TargetRegisterInfo::isPhysicalRegister(Hint.second))
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Priority *= 2;
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}
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return Priority;
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}
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2010-12-10 02:15:21 +08:00
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// Attempt to reassign this virtual register to a different physical register.
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//
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// FIXME: we are not yet caching these "second-level" interferences discovered
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// in the sub-queries. These interferences can change with each call to
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// selectOrSplit. However, we could implement a "may-interfere" cache that
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// could be conservatively dirtied when we reassign or split.
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//
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// FIXME: This may result in a lot of alias queries. We could summarize alias
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// live intervals in their parent register's live union, but it's messy.
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bool RAGreedy::reassignVReg(LiveInterval &InterferingVReg,
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unsigned OldPhysReg) {
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assert(OldPhysReg == VRM->getPhys(InterferingVReg.reg) &&
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"inconsistent phys reg assigment");
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const TargetRegisterClass *TRC = MRI->getRegClass(InterferingVReg.reg);
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for (TargetRegisterClass::iterator I = TRC->allocation_order_begin(*MF),
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E = TRC->allocation_order_end(*MF);
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I != E; ++I) {
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unsigned PhysReg = *I;
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2010-12-10 05:20:46 +08:00
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if (PhysReg == OldPhysReg || ReservedRegs.test(PhysReg))
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2010-12-10 02:15:21 +08:00
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continue;
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// Instantiate a "subquery", not to be confused with the Queries array.
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LiveIntervalUnion::Query subQ(&InterferingVReg,
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&PhysReg2LiveUnion[PhysReg]);
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if (subQ.checkInterference())
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continue;
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for (const unsigned *AliasI = TRI->getAliasSet(PhysReg);
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*AliasI; ++AliasI) {
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subQ.init(&InterferingVReg, &PhysReg2LiveUnion[*AliasI]);
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if (subQ.checkInterference())
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continue;
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}
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DEBUG(dbgs() << "reassigning: " << InterferingVReg << " from " <<
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TRI->getName(OldPhysReg) << " to " << TRI->getName(PhysReg) << '\n');
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// Reassign the interfering virtual reg to this physical reg.
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PhysReg2LiveUnion[OldPhysReg].extract(InterferingVReg);
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VRM->clearVirt(InterferingVReg.reg);
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VRM->assignVirt2Phys(InterferingVReg.reg, PhysReg);
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PhysReg2LiveUnion[PhysReg].unify(InterferingVReg);
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return true;
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}
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return false;
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}
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// Collect all virtual regs currently assigned to PhysReg that interfere with
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// VirtReg.
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//
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// Currently, for simplicity, we only attempt to reassign a single interference
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// within the same register class.
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bool RAGreedy::reassignInterferences(LiveInterval &VirtReg, unsigned PhysReg) {
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LiveIntervalUnion::Query &Q = query(VirtReg, PhysReg);
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// Limit the interference search to one interference.
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Q.collectInterferingVRegs(1);
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assert(Q.interferingVRegs().size() == 1 &&
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"expected at least one interference");
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// Do not attempt reassignment unless we find only a single interference.
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if (!Q.seenAllInterferences())
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return false;
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// Don't allow any interferences on aliases.
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for (const unsigned *AliasI = TRI->getAliasSet(PhysReg); *AliasI; ++AliasI) {
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if (query(VirtReg, *AliasI).checkInterference())
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return false;
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}
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return reassignVReg(*Q.interferingVRegs()[0], PhysReg);
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}
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2010-12-08 11:26:16 +08:00
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unsigned RAGreedy::selectOrSplit(LiveInterval &VirtReg,
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SmallVectorImpl<LiveInterval*> &SplitVRegs) {
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// Populate a list of physical register spill candidates.
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2010-12-10 02:15:21 +08:00
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SmallVector<unsigned, 8> PhysRegSpillCands, ReassignCands;
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2010-12-08 11:26:16 +08:00
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// Check for an available register in this class.
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const TargetRegisterClass *TRC = MRI->getRegClass(VirtReg.reg);
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DEBUG(dbgs() << "RegClass: " << TRC->getName() << ' ');
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2010-12-09 06:57:16 +08:00
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// Preferred physical register computed from hints.
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unsigned Hint = VRM->getRegAllocPref(VirtReg.reg);
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// Try a hinted allocation.
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if (Hint && !ReservedRegs.test(Hint) && TRC->contains(Hint) &&
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checkPhysRegInterference(VirtReg, Hint) == 0)
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return Hint;
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2010-12-08 11:26:16 +08:00
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for (TargetRegisterClass::iterator I = TRC->allocation_order_begin(*MF),
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E = TRC->allocation_order_end(*MF);
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I != E; ++I) {
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unsigned PhysReg = *I;
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if (ReservedRegs.test(PhysReg)) continue;
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// Check interference and as a side effect, intialize queries for this
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// VirtReg and its aliases.
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2010-12-10 02:15:21 +08:00
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unsigned InterfReg = checkPhysRegInterference(VirtReg, PhysReg);
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if (InterfReg == 0) {
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2010-12-08 11:26:16 +08:00
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// Found an available register.
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return PhysReg;
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}
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2010-12-09 07:51:35 +08:00
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assert(!VirtReg.empty() && "Empty VirtReg has interference");
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2010-12-10 02:15:21 +08:00
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LiveInterval *InterferingVirtReg =
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Queries[InterfReg].firstInterference().liveUnionPos().value();
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2010-12-08 11:26:16 +08:00
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2010-12-10 02:15:21 +08:00
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// The current VirtReg must either be spillable, or one of its interferences
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2010-12-08 11:26:16 +08:00
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// must have less spill weight.
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2010-12-10 02:15:21 +08:00
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if (InterferingVirtReg->weight < VirtReg.weight ) {
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// For simplicity, only consider reassigning registers in the same class.
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if (InterfReg == PhysReg)
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ReassignCands.push_back(PhysReg);
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else
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PhysRegSpillCands.push_back(PhysReg);
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2010-12-08 11:26:16 +08:00
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}
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}
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2010-12-10 02:15:21 +08:00
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// Try to reassign interfering physical register. Priority among
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// PhysRegSpillCands does not matter yet, because the reassigned virtual
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// registers will still be assigned to physical registers.
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for (SmallVectorImpl<unsigned>::iterator PhysRegI = ReassignCands.begin(),
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PhysRegE = ReassignCands.end(); PhysRegI != PhysRegE; ++PhysRegI) {
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if (reassignInterferences(VirtReg, *PhysRegI))
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// Reassignment successfull. The caller may allocate now to this PhysReg.
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return *PhysRegI;
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}
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PhysRegSpillCands.insert(PhysRegSpillCands.end(), ReassignCands.begin(),
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ReassignCands.end());
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2010-12-08 11:26:16 +08:00
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// Try to spill another interfering reg with less spill weight.
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//
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2010-12-10 02:15:21 +08:00
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// FIXME: do this in two steps: (1) check for unspillable interferences while
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// accumulating spill weight; (2) spill the interferences with lowest
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// aggregate spill weight.
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2010-12-08 11:26:16 +08:00
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for (SmallVectorImpl<unsigned>::iterator PhysRegI = PhysRegSpillCands.begin(),
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PhysRegE = PhysRegSpillCands.end(); PhysRegI != PhysRegE; ++PhysRegI) {
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if (!spillInterferences(VirtReg, *PhysRegI, SplitVRegs)) continue;
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assert(checkPhysRegInterference(VirtReg, *PhysRegI) == 0 &&
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"Interference after spill.");
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// Tell the caller to allocate to this newly freed physical register.
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return *PhysRegI;
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}
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2010-12-10 02:15:21 +08:00
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2010-12-08 11:26:16 +08:00
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// No other spill candidates were found, so spill the current VirtReg.
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DEBUG(dbgs() << "spilling: " << VirtReg << '\n');
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SmallVector<LiveInterval*, 1> pendingSpills;
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spiller().spill(&VirtReg, SplitVRegs, pendingSpills);
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// The live virtual register requesting allocation was spilled, so tell
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// the caller not to allocate anything during this round.
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return 0;
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}
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bool RAGreedy::runOnMachineFunction(MachineFunction &mf) {
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DEBUG(dbgs() << "********** GREEDY REGISTER ALLOCATION **********\n"
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<< "********** Function: "
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<< ((Value*)mf.getFunction())->getName() << '\n');
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MF = &mf;
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TM = &mf.getTarget();
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MRI = &mf.getRegInfo();
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const TargetRegisterInfo *TRI = TM->getRegisterInfo();
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RegAllocBase::init(*TRI, getAnalysis<VirtRegMap>(),
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getAnalysis<LiveIntervals>());
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ReservedRegs = TRI->getReservedRegs(*MF);
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SpillerInstance.reset(createSpiller(*this, *MF, *VRM));
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allocatePhysRegs();
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addMBBLiveIns(MF);
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// Run rewriter
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std::auto_ptr<VirtRegRewriter> rewriter(createVirtRegRewriter());
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rewriter->runOnMachineFunction(*MF, *VRM, LIS);
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// The pass output is in VirtRegMap. Release all the transient data.
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releaseMemory();
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return true;
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}
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