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llvm-project/llvm/lib/Target/PowerPC/PPCScheduleP8.td

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Add TableGen info for Power8. This is based on the Power7 version, with units added and renamed to match P8. Differential Revision: http://reviews.llvm.org/D6358 llvm-svn: 223257
2014-12-04 02:46:30 +08:00
//===-- PPCScheduleP8.td - PPC P8 Scheduling Definitions ---*- tablegen -*-===//
//
Update the file headers across all of the LLVM projects in the monorepo to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
2019-01-19 16:50:56 +08:00
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
Add TableGen info for Power8. This is based on the Power7 version, with units added and renamed to match P8. Differential Revision: http://reviews.llvm.org/D6358 llvm-svn: 223257
2014-12-04 02:46:30 +08:00
//
//===----------------------------------------------------------------------===//
//
// This file defines the itinerary class data for the POWER8 processor.
//
//===----------------------------------------------------------------------===//
// Scheduling for the P8 involves tracking two types of resources:
// 1. The dispatch bundle slots
// 2. The functional unit resources
// Dispatch units:
def P8_DU1 : FuncUnit;
def P8_DU2 : FuncUnit;
def P8_DU3 : FuncUnit;
def P8_DU4 : FuncUnit;
def P8_DU5 : FuncUnit;
def P8_DU6 : FuncUnit;
def P8_DU7 : FuncUnit; // Only branch instructions will use DU7,DU8
def P8_DU8 : FuncUnit;
// 10 insns per cycle (2-LU, 2-LSU, 2-FXU, 2-FPU, 1-CRU, 1-BRU).
def P8_LU1 : FuncUnit; // Loads or fixed-point operations 1
def P8_LU2 : FuncUnit; // Loads or fixed-point operations 2
// Load/Store pipelines can handle Stores, fixed-point loads, and simple
// fixed-point operations.
def P8_LSU1 : FuncUnit; // Load/Store pipeline 1
def P8_LSU2 : FuncUnit; // Load/Store pipeline 2
// Fixed Point unit
def P8_FXU1 : FuncUnit; // FX pipeline 1
def P8_FXU2 : FuncUnit; // FX pipeline 2
// The Floating-Point Unit (FPU) and Vector Media Extension (VMX) units
// are combined on P7 and newer into a Vector Scalar Unit (VSU).
// The P8 Instruction latency documents still refers to the unit as the
// FPU, so keep in mind that FPU==VSU.
// In contrast to the P7, the VMX units on P8 are symmetric, so no need to
// split vector integer ops or 128-bit load/store/perms to the specific units.
def P8_FPU1 : FuncUnit; // VS pipeline 1
def P8_FPU2 : FuncUnit; // VS pipeline 2
def P8_CRU : FuncUnit; // CR unit (CR logicals and move-from-SPRs)
def P8_BRU : FuncUnit; // BR unit
def P8Itineraries : ProcessorItineraries<
[P8_DU1, P8_DU2, P8_DU3, P8_DU4, P8_DU5, P8_DU6, P8_DU7, P8_DU8,
P8_LU1, P8_LU2, P8_LSU1, P8_LSU2, P8_FXU1, P8_FXU2,
P8_FPU1, P8_FPU2, P8_CRU, P8_BRU], [], [
InstrItinData<IIC_IntSimple , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
P8_DU4, P8_DU5, P8_DU6], 0>,
InstrStage<1, [P8_FXU1, P8_FXU2,
P8_LU1, P8_LU2,
P8_LSU1, P8_LSU2]>],
[1, 1, 1]>,
InstrItinData<IIC_IntGeneral , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
P8_DU4, P8_DU5, P8_DU6], 0>,
InstrStage<1, [P8_FXU1, P8_FXU2, P8_LU1,
P8_LU2, P8_LSU1, P8_LSU2]>],
[1, 1, 1]>,
[PowerPC] Better scheduling for isel on P7/P8 isel is actually a cracked instruction on the P7/P8, and must start a dispatch group. The scheduling model should reflect this so that we don't bunch too many of them together when possible. Thanks to Bill Schmidt and Pat Haugen for helping to sort this out. llvm-svn: 227758
2015-02-02 01:52:16 +08:00
InstrItinData<IIC_IntISEL, [InstrStage<1, [P8_DU1], 0>,
InstrStage<1, [P8_FXU1, P8_FXU2], 0>,
InstrStage<1, [P8_BRU]>],
[1, 1, 1, 1]>,
Add TableGen info for Power8. This is based on the Power7 version, with units added and renamed to match P8. Differential Revision: http://reviews.llvm.org/D6358 llvm-svn: 223257
2014-12-04 02:46:30 +08:00
InstrItinData<IIC_IntCompare , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
P8_DU4, P8_DU5, P8_DU6], 0>,
InstrStage<1, [P8_FXU1, P8_FXU2]>],
[1, 1, 1]>,
InstrItinData<IIC_IntDivW , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
P8_DU4, P8_DU5, P8_DU6], 0>,
InstrStage<15, [P8_FXU1, P8_FXU2]>],
[15, 1, 1]>,
InstrItinData<IIC_IntDivD , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
P8_DU4, P8_DU5, P8_DU6], 0>,
InstrStage<23, [P8_FXU1, P8_FXU2]>],
[23, 1, 1]>,
InstrItinData<IIC_IntMulHW , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
P8_DU4, P8_DU5, P8_DU6], 0>,
InstrStage<1, [P8_FXU1, P8_FXU2]>],
[4, 1, 1]>,
InstrItinData<IIC_IntMulHWU , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
P8_DU4, P8_DU5, P8_DU6], 0>,
InstrStage<1, [P8_FXU1, P8_FXU2]>],
[4, 1, 1]>,
[PowerPC] Add Itineraries of IIC_IntMulHD for P7/P8 When doing some instruction scheduling work, we noticed some missing itineraries. Before we switch to machine scheduler, those missing itineraries might not have impact to actually scheduling, because we can still get same latency due to default values. With machine scheduler, however, itineraries will have impact to scheduling. eg: NumMicroOps will default to be 0 if there is NO itineraries for specific instruction class. And most of the instruction class with itineraries will have NumMicroOps default to 1. This will has impact on the count of RetiredMOps, affects the Pending/Available Queue, then causing different scheduling or suboptimal scheduling further. Patch By: jsji (Jinsong Ji) Differential Revision: https://reviews.llvm.org/D52040 llvm-svn: 342441
2018-09-18 10:05:18 +08:00
InstrItinData<IIC_IntMulHD , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
P8_DU4, P8_DU5, P8_DU6], 0>,
InstrStage<1, [P8_FXU1, P8_FXU2]>],
[4, 1, 1]>,
Add TableGen info for Power8. This is based on the Power7 version, with units added and renamed to match P8. Differential Revision: http://reviews.llvm.org/D6358 llvm-svn: 223257
2014-12-04 02:46:30 +08:00
InstrItinData<IIC_IntMulLI , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
P8_DU4, P8_DU5, P8_DU6], 0>,
InstrStage<1, [P8_FXU1, P8_FXU2]>],
[4, 1, 1]>,
InstrItinData<IIC_IntRotate , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
P8_DU4, P8_DU5, P8_DU6], 0>,
InstrStage<1, [P8_FXU1, P8_FXU2]>],
[1, 1, 1]>,
InstrItinData<IIC_IntRotateD , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
P8_DU4, P8_DU5, P8_DU6], 0>,
InstrStage<1, [P8_FXU1, P8_FXU2]>],
[1, 1, 1]>,
[PowerPC] Add Itineraries of IIC_IntRotateDI for P7/P8 When doing some instruction scheduling work, we noticed some missing itineraries. Before we switch to machine scheduler, those missing itineraries might not have impact to actually scheduling, because we can still get same latency due to default values. With machine scheduler, however, itineraries will have impact to scheduling. eg: NumMicroOps will default to be 0 if there is NO itineraries for specific instruction class. And most of the instruction class with itineraries will have NumMicroOps default to 1. This will has impact on the count of RetiredMOps, affects the Pending/Available Queue, then causing different scheduling or suboptimal scheduling further. Patch by jsji (Jinsong Ji) Differential Revision: https://reviews.llvm.org/D51506 llvm-svn: 341293
2018-09-03 11:14:29 +08:00
InstrItinData<IIC_IntRotateDI , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
P8_DU4, P8_DU5, P8_DU6], 0>,
InstrStage<1, [P8_FXU1, P8_FXU2]>],
[1, 1, 1]>,
Add TableGen info for Power8. This is based on the Power7 version, with units added and renamed to match P8. Differential Revision: http://reviews.llvm.org/D6358 llvm-svn: 223257
2014-12-04 02:46:30 +08:00
InstrItinData<IIC_IntShift , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
P8_DU4, P8_DU5, P8_DU6], 0>,
InstrStage<1, [P8_FXU1, P8_FXU2]>],
[1, 1, 1]>,
InstrItinData<IIC_IntTrapW , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
P8_DU4, P8_DU5, P8_DU6], 0>,
InstrStage<1, [P8_FXU1, P8_FXU2]>],
[1, 1]>,
InstrItinData<IIC_IntTrapD , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
P8_DU4, P8_DU5, P8_DU6], 0>,
InstrStage<1, [P8_FXU1, P8_FXU2]>],
[1, 1]>,
InstrItinData<IIC_BrB , [InstrStage<1, [P8_DU7, P8_DU8], 0>,
InstrStage<1, [P8_BRU]>],
[3, 1, 1]>,
// FIXME - the Br* groups below are not branch related, so should probably
// be renamed.
// IIC_BrCR consists of the cr* instructions. (crand,crnor,creqv, etc).
// and should be 'First' in dispatch.
InstrItinData<IIC_BrCR , [InstrStage<1, [P8_DU1], 0>,
InstrStage<1, [P8_CRU]>],
[3, 1, 1]>,
// IIC_BrMCR consists of the mcrf instruction.
InstrItinData<IIC_BrMCR , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
P8_DU4, P8_DU5, P8_DU6], 0>,
InstrStage<1, [P8_CRU]>],
[3, 1, 1]>,
// IIC_BrMCRX consists of mcrxr (obsolete instruction) and mtcrf, which
// should be first in the dispatch group.
InstrItinData<IIC_BrMCRX , [InstrStage<1, [P8_DU1], 0>,
InstrStage<1, [P8_FXU1, P8_FXU2]>],
[3, 1, 1]>,
InstrItinData<IIC_BrMCRX , [InstrStage<1, [P8_DU1], 0>,
InstrStage<1, [P8_FXU1, P8_FXU2]>],
[3, 1]>,
InstrItinData<IIC_LdStLoad , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
P8_DU4, P8_DU5, P8_DU6], 0>,
InstrStage<1, [P8_LSU1, P8_LSU2,
P8_LU1, P8_LU2]>],
[2, 1, 1]>,
InstrItinData<IIC_LdStLoadUpd , [InstrStage<1, [P8_DU1], 0>,
InstrStage<1, [P8_DU2], 0>,
InstrStage<1, [P8_LSU1, P8_LSU2,
P8_LU1, P8_LU2 ], 0>,
InstrStage<1, [P8_FXU1, P8_FXU2]>],
[2, 2, 1, 1]>,
// Update-Indexed form loads/stores are no longer first and last in the
// dispatch group. They are simply cracked, so require DU1,DU2.
InstrItinData<IIC_LdStLoadUpdX, [InstrStage<1, [P8_DU1], 0>,
InstrStage<1, [P8_DU2], 0>,
InstrStage<1, [P8_LSU1, P8_LSU2,
P8_LU1, P8_LU2], 0>,
InstrStage<1, [P8_FXU1, P8_FXU2]>],
[3, 3, 1, 1]>,
InstrItinData<IIC_LdStLD , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
P8_DU4, P8_DU5, P8_DU6], 0>,
InstrStage<1, [P8_LSU1, P8_LSU2,
P8_LU1, P8_LU2]>],
[2, 1, 1]>,
InstrItinData<IIC_LdStLDU , [InstrStage<1, [P8_DU1], 0>,
InstrStage<1, [P8_DU2], 0>,
InstrStage<1, [P8_LSU1, P8_LSU2,
P8_LU1, P8_LU2], 0>,
InstrStage<1, [P8_FXU1, P8_FXU2]>],
[2, 2, 1, 1]>,
InstrItinData<IIC_LdStLDUX , [InstrStage<1, [P8_DU1], 0>,
InstrStage<1, [P8_DU2], 0>,
InstrStage<1, [P8_LSU1, P8_LSU2,
P8_LU1, P8_LU2], 0>,
InstrStage<1, [P8_FXU1, P8_FXU2]>],
[3, 3, 1, 1]>,
InstrItinData<IIC_LdStLFD , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
P8_DU4, P8_DU5, P8_DU6], 0>,
InstrStage<1, [P8_LU1, P8_LU2]>],
[3, 1, 1]>,
InstrItinData<IIC_LdStLVecX , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
P8_DU4, P8_DU5, P8_DU6], 0>,
InstrStage<1, [P8_LU1, P8_LU2]>],
[3, 1, 1]>,
InstrItinData<IIC_LdStLFDU , [InstrStage<1, [P8_DU1], 0>,
InstrStage<1, [P8_DU2], 0>,
InstrStage<1, [P8_LU1, P8_LU2], 0>,
InstrStage<1, [P8_FXU1, P8_FXU2]>],
[3, 3, 1, 1]>,
InstrItinData<IIC_LdStLFDUX , [InstrStage<1, [P8_DU1], 0>,
InstrStage<1, [P8_DU2], 0>,
InstrStage<1, [P8_LU1, P8_LU2], 0>,
InstrStage<1, [P8_FXU1, P8_FXU2]>],
[3, 3, 1, 1]>,
InstrItinData<IIC_LdStLHA , [InstrStage<1, [P8_DU1], 0>,
InstrStage<1, [P8_DU2], 0>,
InstrStage<1, [P8_LSU1, P8_LSU2,
P8_LU1, P8_LU2], 0>,
InstrStage<1, [P8_FXU1, P8_FXU2,
P8_LU1, P8_LU2]>],
[3, 1, 1]>,
InstrItinData<IIC_LdStLHAU , [InstrStage<1, [P8_DU1], 0>,
InstrStage<1, [P8_DU2], 0>,
InstrStage<1, [P8_LSU1, P8_LSU2,
P8_LU1, P8_LU2], 0>,
InstrStage<1, [P8_FXU1, P8_FXU2]>,
InstrStage<1, [P8_FXU1, P8_FXU2]>],
[4, 4, 1, 1]>,
// first+last in dispatch group.
InstrItinData<IIC_LdStLHAUX , [InstrStage<1, [P8_DU1], 0>,
InstrStage<1, [P8_DU2], 0>,
InstrStage<1, [P8_DU3], 0>,
InstrStage<1, [P8_DU4], 0>,
InstrStage<1, [P8_DU5], 0>,
InstrStage<1, [P8_DU6], 0>,
InstrStage<1, [P8_LSU1, P8_LSU2,
P8_LU1, P8_LU2], 0>,
InstrStage<1, [P8_FXU1, P8_FXU2]>,
InstrStage<1, [P8_FXU1, P8_FXU2]>],
[4, 4, 1, 1]>,
InstrItinData<IIC_LdStLWA , [InstrStage<1, [P8_DU1], 0>,
InstrStage<1, [P8_DU2], 0>,
InstrStage<1, [P8_LSU1, P8_LSU2,
P8_LU1, P8_LU2]>,
InstrStage<1, [P8_FXU1, P8_FXU2]>],
[3, 1, 1]>,
InstrItinData<IIC_LdStLWARX, [InstrStage<1, [P8_DU1], 0>,
InstrStage<1, [P8_DU2], 0>,
InstrStage<1, [P8_DU3], 0>,
InstrStage<1, [P8_DU4], 0>,
InstrStage<1, [P8_LSU1, P8_LSU2,
P8_LU1, P8_LU2]>],
[3, 1, 1]>,
// first+last
InstrItinData<IIC_LdStLDARX, [InstrStage<1, [P8_DU1], 0>,
InstrStage<1, [P8_DU2], 0>,
InstrStage<1, [P8_DU3], 0>,
InstrStage<1, [P8_DU4], 0>,
InstrStage<1, [P8_DU5], 0>,
InstrStage<1, [P8_DU6], 0>,
InstrStage<1, [P8_LSU1, P8_LSU2,
P8_LU1, P8_LU2]>],
[3, 1, 1]>,
InstrItinData<IIC_LdStLMW , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
P8_DU4, P8_DU5, P8_DU6], 0>,
InstrStage<1, [P8_LSU1, P8_LSU2,
P8_LU1, P8_LU2]>],
[2, 1, 1]>,
// Stores are dual-issued from the issue queue, so may only take up one
// dispatch slot. The instruction will be broken into two IOPS. The agen
// op is issued to the LSU, and the data op (register fetch) is issued
// to either the LU (GPR store) or the VSU (FPR store).
InstrItinData<IIC_LdStStore , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
P8_DU4, P8_DU5, P8_DU6], 0>,
InstrStage<1, [P8_LSU1, P8_LSU2]>,
InstrStage<1, [P8_LU1, P8_LU2]>],
[1, 1, 1]>,
InstrItinData<IIC_LdStSTD , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
P8_DU4, P8_DU5, P8_DU6], 0>,
InstrStage<1, [P8_LU1, P8_LU2,
P8_LSU1, P8_LSU2]>]
[1, 1, 1]>,
[PowerPC] Add Itineraries for STWU/STWUX etc When doing some instruction scheduling work, we noticed some missing itineraries. Before we switch to machine scheduler, those missing itineraries might not have impact to actually scheduling, because we can still get same latency due to default values. With machine scheduler, however, itineraries will have impact to scheduling. eg: NumMicroOps will default to be 0 if there is NO itineraries for specific instruction class. And most of the instruction class with itineraries will have NumMicroOps default to 1. This will has impact on the count of RetiredMOps, affects the Pending/Available Queue, then causing different scheduling or suboptimal scheduling further. This patch is for STWU/STWUX (IIC_LdStStoreUpd ) for P8. Since there are already multiple IIC for store update, this patch also merge IIC_LdStSTDU/IIC_LdStStoreUpd to IIC_LdStSTU IIC_LdStSTDUX to IIC_LdStSTUX and we add a new testcase in https://reviews.llvm.org/D54699 to show the difference. Differential Revision: https://reviews.llvm.org/D54700 llvm-svn: 347311
2018-11-20 23:11:42 +08:00
InstrItinData<IIC_LdStSTU , [InstrStage<1, [P8_DU1], 0>,
Add TableGen info for Power8. This is based on the Power7 version, with units added and renamed to match P8. Differential Revision: http://reviews.llvm.org/D6358 llvm-svn: 223257
2014-12-04 02:46:30 +08:00
InstrStage<1, [P8_DU2], 0>,
InstrStage<1, [P8_LU1, P8_LU2,
P8_LSU1, P8_LSU2], 0>,
InstrStage<1, [P8_FXU1, P8_FXU2]>],
[2, 1, 1, 1]>,
// First+last
[PowerPC] Add Itineraries for STWU/STWUX etc When doing some instruction scheduling work, we noticed some missing itineraries. Before we switch to machine scheduler, those missing itineraries might not have impact to actually scheduling, because we can still get same latency due to default values. With machine scheduler, however, itineraries will have impact to scheduling. eg: NumMicroOps will default to be 0 if there is NO itineraries for specific instruction class. And most of the instruction class with itineraries will have NumMicroOps default to 1. This will has impact on the count of RetiredMOps, affects the Pending/Available Queue, then causing different scheduling or suboptimal scheduling further. This patch is for STWU/STWUX (IIC_LdStStoreUpd ) for P8. Since there are already multiple IIC for store update, this patch also merge IIC_LdStSTDU/IIC_LdStStoreUpd to IIC_LdStSTU IIC_LdStSTDUX to IIC_LdStSTUX and we add a new testcase in https://reviews.llvm.org/D54699 to show the difference. Differential Revision: https://reviews.llvm.org/D54700 llvm-svn: 347311
2018-11-20 23:11:42 +08:00
InstrItinData<IIC_LdStSTUX , [InstrStage<1, [P8_DU1], 0>,
Add TableGen info for Power8. This is based on the Power7 version, with units added and renamed to match P8. Differential Revision: http://reviews.llvm.org/D6358 llvm-svn: 223257
2014-12-04 02:46:30 +08:00
InstrStage<1, [P8_DU2], 0>,
InstrStage<1, [P8_DU3], 0>,
InstrStage<1, [P8_DU4], 0>,
InstrStage<1, [P8_DU5], 0>,
InstrStage<1, [P8_DU6], 0>,
InstrStage<1, [P8_LSU1, P8_LSU2], 0>,
InstrStage<1, [P8_FXU1, P8_FXU2]>,
InstrStage<1, [P8_FXU1, P8_FXU2]>],
[2, 1, 1, 1]>,
InstrItinData<IIC_LdStSTFD , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
P8_DU4, P8_DU5, P8_DU6], 0>,
InstrStage<1, [P8_LSU1, P8_LSU2], 0>,
InstrStage<1, [P8_FPU1, P8_FPU2]>],
[1, 1, 1]>,
InstrItinData<IIC_LdStSTFDU , [InstrStage<1, [P8_DU1], 0>,
InstrStage<1, [P8_DU2], 0>,
InstrStage<1, [P8_LSU1, P8_LSU2], 0>,
InstrStage<1, [P8_FXU1, P8_FXU2], 0>,
InstrStage<1, [P8_FPU1, P8_FPU2]>],
[2, 1, 1, 1]>,
InstrItinData<IIC_LdStSTVEBX , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
P8_DU4, P8_DU5, P8_DU6], 0>,
InstrStage<1, [P8_LSU1, P8_LSU2], 0>,
InstrStage<1, [P8_FPU1, P8_FPU2]>],
[1, 1, 1]>,
InstrItinData<IIC_LdStSTDCX , [InstrStage<1, [P8_DU1], 0>,
InstrStage<1, [P8_DU2], 0>,
InstrStage<1, [P8_DU3], 0>,
InstrStage<1, [P8_DU4], 0>,
InstrStage<1, [P8_DU5], 0>,
InstrStage<1, [P8_DU6], 0>,
InstrStage<1, [P8_LSU1, P8_LSU2], 0>,
InstrStage<1, [P8_LU1, P8_LU2]>],
[1, 1, 1]>,
InstrItinData<IIC_LdStSTWCX , [InstrStage<1, [P8_DU1], 0>,
InstrStage<1, [P8_DU2], 0>,
InstrStage<1, [P8_DU3], 0>,
InstrStage<1, [P8_DU4], 0>,
InstrStage<1, [P8_DU5], 0>,
InstrStage<1, [P8_DU6], 0>,
InstrStage<1, [P8_LSU1, P8_LSU2], 0>,
InstrStage<1, [P8_LU1, P8_LU2]>],
[1, 1, 1]>,
InstrItinData<IIC_SprMFCR , [InstrStage<1, [P8_DU1], 0>,
InstrStage<1, [P8_CRU]>],
[6, 1]>,
InstrItinData<IIC_SprMFCRF , [InstrStage<1, [P8_DU1], 0>,
InstrStage<1, [P8_CRU]>],
[3, 1]>,
InstrItinData<IIC_SprMTSPR , [InstrStage<1, [P8_DU1], 0>,
InstrStage<1, [P8_FXU1, P8_FXU2]>],
[4, 1]>, // mtctr
InstrItinData<IIC_FPGeneral , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
P8_DU4, P8_DU5, P8_DU6], 0>,
InstrStage<1, [P8_FPU1, P8_FPU2]>],
[5, 1, 1]>,
[PowerPC] Fix the PPCInstrInfo::getInstrLatency implementation PowerPC uses itineraries to describe processor pipelines (and dispatch-group restrictions for P7/P8 cores). Unfortunately, the target-independent implementation of TII.getInstrLatency calls ItinData->getStageLatency, and that looks for the largest cycle count in the pipeline for any given instruction. This, however, yields the wrong answer for the PPC itineraries, because we don't encode the full pipeline. Because the functional units are fully pipelined, we only model the initial stages (there are no relevant hazards in the later stages to model), and so the technique employed by getStageLatency does not really work. Instead, we should take the maximum output operand latency, and that's what PPCInstrInfo::getInstrLatency now does. This caused some test-case churn, including two unfortunate side effects. First, the new arrangement of copies we get from function parameters now sometimes blocks VSX FMA mutation (a FIXME has been added to the code and the test cases), and we have one significant test-suite regression: SingleSource/Benchmarks/BenchmarkGame/spectral-norm 56.4185% +/- 18.9398% In this benchmark we have a loop with a vectorized FP divide, and it with the new scheduling both divides end up in the same dispatch group (which in this case seems to cause a problem, although why is not exactly clear). The grouping structure is hard to predict from the bottom of the loop, and there may not be much we can do to fix this. Very few other test-suite performance effects were really significant, but almost all weakly favor this change. However, in light of the issues highlighted above, I've left the old behavior available via a command-line flag. llvm-svn: 242188
2015-07-15 04:02:02 +08:00
InstrItinData<IIC_FPAddSub , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
P8_DU4, P8_DU5, P8_DU6], 0>,
InstrStage<1, [P8_FPU1, P8_FPU2]>],
[5, 1, 1]>,
Add TableGen info for Power8. This is based on the Power7 version, with units added and renamed to match P8. Differential Revision: http://reviews.llvm.org/D6358 llvm-svn: 223257
2014-12-04 02:46:30 +08:00
InstrItinData<IIC_FPCompare , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
P8_DU4, P8_DU5, P8_DU6], 0>,
InstrStage<1, [P8_FPU1, P8_FPU2]>],
[8, 1, 1]>,
InstrItinData<IIC_FPDivD , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
P8_DU4, P8_DU5, P8_DU6], 0>,
InstrStage<1, [P8_FPU1, P8_FPU2]>],
[33, 1, 1]>,
InstrItinData<IIC_FPDivS , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
P8_DU4, P8_DU5, P8_DU6], 0>,
InstrStage<1, [P8_FPU1, P8_FPU2]>],
[27, 1, 1]>,
InstrItinData<IIC_FPSqrtD , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
P8_DU4, P8_DU5, P8_DU6], 0>,
InstrStage<1, [P8_FPU1, P8_FPU2]>],
[44, 1, 1]>,
InstrItinData<IIC_FPSqrtS , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
P8_DU4, P8_DU5, P8_DU6], 0>,
InstrStage<1, [P8_FPU1, P8_FPU2]>],
[32, 1, 1]>,
InstrItinData<IIC_FPFused , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
P8_DU4, P8_DU5, P8_DU6], 0>,
InstrStage<1, [P8_FPU1, P8_FPU2]>],
[5, 1, 1, 1]>,
InstrItinData<IIC_FPRes , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
P8_DU4, P8_DU5, P8_DU6], 0>,
InstrStage<1, [P8_FPU1, P8_FPU2]>],
[5, 1, 1]>,
InstrItinData<IIC_VecGeneral , [InstrStage<1, [P8_DU1], 0>,
InstrStage<1, [P8_FPU1, P8_FPU2]>],
[2, 1, 1]>,
InstrItinData<IIC_VecVSL , [InstrStage<1, [P8_DU1], 0>,
InstrStage<1, [P8_FPU1, P8_FPU2]>],
[2, 1, 1]>,
InstrItinData<IIC_VecVSR , [InstrStage<1, [P8_DU1], 0>,
InstrStage<1, [P8_FPU1, P8_FPU2]>],
[2, 1, 1]>,
InstrItinData<IIC_VecFP , [InstrStage<1, [P8_DU1], 0>,
InstrStage<1, [P8_FPU1, P8_FPU2]>],
[6, 1, 1]>,
InstrItinData<IIC_VecFPCompare, [InstrStage<1, [P8_DU1], 0>,
InstrStage<1, [P8_FPU1, P8_FPU2]>],
[6, 1, 1]>,
InstrItinData<IIC_VecFPRound , [InstrStage<1, [P8_DU1], 0>,
InstrStage<1, [P8_FPU1, P8_FPU2]>],
[6, 1, 1]>,
InstrItinData<IIC_VecComplex , [InstrStage<1, [P8_DU1], 0>,
InstrStage<1, [P8_FPU1, P8_FPU2]>],
[7, 1, 1]>,
InstrItinData<IIC_VecPerm , [InstrStage<1, [P8_DU1, P8_DU2], 0>,
vec perm can go down either pipeline on P8. No observable changes, spotted while looking at the scheduling description. llvm-svn: 296277
2017-02-26 08:11:58 +08:00
InstrStage<1, [P8_FPU1, P8_FPU2]>],
Add TableGen info for Power8. This is based on the Power7 version, with units added and renamed to match P8. Differential Revision: http://reviews.llvm.org/D6358 llvm-svn: 223257
2014-12-04 02:46:30 +08:00
[3, 1, 1]>
]>;
// ===---------------------------------------------------------------------===//
// P8 machine model for scheduling and other instruction cost heuristics.
// P8 has an 8 insn dispatch group (6 non-branch, 2 branch) and can issue up
// to 10 insns per cycle (2-LU, 2-LSU, 2-FXU, 2-FPU, 1-CRU, 1-BRU).
def P8Model : SchedMachineModel {
let IssueWidth = 8; // up to 8 instructions dispatched per cycle.
// up to six non-branch instructions.
// up to two branches in a dispatch group.
let LoadLatency = 3; // Optimistic load latency assuming bypass.
// This is overriden by OperandCycles if the
// Itineraries are queried instead.
let MispredictPenalty = 16;
[PowerPC] Readjust the loop unrolling threshold Now that the way that the partial unrolling threshold for small loops is used to compute the unrolling factor as been corrected, a slightly smaller threshold is preferable. This is expected; other targets may need to re-tune as well. llvm-svn: 225566
2015-01-10 08:31:10 +08:00
// Try to make sure we have at least 10 dispatch groups in a loop.
let LoopMicroOpBufferSize = 60;
[PowerPC] Enable late partial unrolling on the POWER7 The P7 benefits from not have really-small loops so that we either have multiple dispatch groups in the loop and/or the ability to form more-full dispatch groups during scheduling. Setting the partial unrolling threshold to 44 seems good, empirically, for the P7. Compared to using no late partial unrolling, this yields the following test-suite speedups: SingleSource/Benchmarks/Adobe-C++/simple_types_constant_folding -66.3253% +/- 24.1975% SingleSource/Benchmarks/Misc-C++/oopack_v1p8 -44.0169% +/- 29.4881% SingleSource/Benchmarks/Misc/pi -27.8351% +/- 12.2712% SingleSource/Benchmarks/Stanford/Bubblesort -30.9898% +/- 22.4647% I've speculatively added a similar setting for the P8. Also, I've noticed that the unroller does not quite calculate the unrolling factor correctly for really tiny loops because it neglects to account for the fact that not every loop body replicant contains an ending branch and counter increment. I'll fix that later. llvm-svn: 225522
2015-01-09 23:51:16 +08:00
TableGen: Check scheduling models for completeness TableGen checks at compiletime that for scheduling models with "CompleteModel = 1" one of the following holds: - Is marked with the hasNoSchedulingInfo flag - The instruction is a subclass of Sched - There are InstRW definitions in the scheduling model Typical steps necessary to complete a model: - Ensure all pseudo instructions that are expanded before machine scheduling (usually everything handled with EmitYYY() functions in XXXTargetLowering). - If a CPU does not support some instructions mark the corresponding resource unsupported: "WriteRes<WriteXXX, []> { let Unsupported = 1; }". - Add missing scheduling information. Differential Revision: http://reviews.llvm.org/D17747 llvm-svn: 262384
2016-03-02 04:03:21 +08:00
let CompleteModel = 0;
Add TableGen info for Power8. This is based on the Power7 version, with units added and renamed to match P8. Differential Revision: http://reviews.llvm.org/D6358 llvm-svn: 223257
2014-12-04 02:46:30 +08:00
let Itineraries = P8Itineraries;
}