forked from OSchip/llvm-project
91 lines
2.3 KiB
LLVM
91 lines
2.3 KiB
LLVM
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; Test zE12 conditional traps
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=zEC12 | FileCheck %s
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declare void @llvm.trap()
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; Check conditional compare logical and trap
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define i32 @f1(i32 zeroext %a, i32 *%ptr) {
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; CHECK-LABEL: f1:
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; CHECK: clth %r2, 0(%r3)
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; CHECK: lhi %r2, 0
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; CHECK: br %r14
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entry:
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%b = load i32, i32 *%ptr
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%cmp = icmp ugt i32 %a, %b
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br i1 %cmp, label %if.then, label %if.end
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if.then: ; preds = %entry
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tail call void @llvm.trap()
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unreachable
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if.end: ; preds = %entry
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ret i32 0
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}
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; Check conditional compare logical grande and trap
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define i64 @f2(i64 zeroext %a, i64 *%ptr) {
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; CHECK-LABEL: f2:
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; CHECK: clgtl %r2, 0(%r3)
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; CHECK: lghi %r2, 0
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; CHECK: br %r14
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entry:
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%b = load i64, i64 *%ptr
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%cmp = icmp ult i64 %a, %b
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br i1 %cmp, label %if.then, label %if.end
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if.then: ; preds = %entry
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tail call void @llvm.trap()
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unreachable
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if.end: ; preds = %entry
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ret i64 0
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}
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; Verify that we don't attempt to use the compare and trap
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; instruction with an index operand.
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define i32 @f3(i32 zeroext %a, i32 *%base, i64 %offset) {
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; CHECK-LABEL: f3:
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; CHECK: cl %r2, 0(%r{{[0-5]}},%r3)
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; CHECK-LABEL: .Ltmp0
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; CHECK: jh .Ltmp0+2
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; CHECK: lhi %r2, 0
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; CHECK: br %r14
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entry:
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%ptr = getelementptr i32, i32 *%base, i64 %offset
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%b = load i32, i32 *%ptr
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%cmp = icmp ugt i32 %a, %b
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br i1 %cmp, label %if.then, label %if.end
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if.then: ; preds = %entry
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tail call void @llvm.trap()
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unreachable
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if.end: ; preds = %entry
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ret i32 0
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}
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; Verify that we don't attempt to use the compare and trap grande
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; instruction with an index operand.
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define i64 @f4(i64 %a, i64 *%base, i64 %offset) {
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; CHECK-LABEL: f4:
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; CHECK: clg %r2, 0(%r{{[0-5]}},%r3)
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; CHECK-LABEL: .Ltmp1
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; CHECK: jh .Ltmp1+2
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; CHECK: lghi %r2, 0
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; CHECK: br %r14
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entry:
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%ptr = getelementptr i64, i64 *%base, i64 %offset
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%b = load i64, i64 *%ptr
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%cmp = icmp ugt i64 %a, %b
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br i1 %cmp, label %if.then, label %if.end
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if.then: ; preds = %entry
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tail call void @llvm.trap()
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unreachable
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if.end: ; preds = %entry
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ret i64 0
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}
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