forked from OSchip/llvm-project
89 lines
3.1 KiB
LLVM
89 lines
3.1 KiB
LLVM
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; RUN: opt < %s -loop-reduce -S | FileCheck %s
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; CHECK: bb1:
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; CHECK: load double addrspace(1)* [[IV:%[^,]+]]
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; CHECK: store double {{.*}}, double addrspace(1)* [[IV]]
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; CHECK-NOT: cast
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; Make sure the GEP has the right index type
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; CHECK: getelementptr double addrspace(1)* [[IV]], i16 1
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; CHECK: br {{.*}} label %bb1
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; Make sure the GEP has the right index type
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; CHECK: getelementptr double addrspace(1)* {{.*}}, i16
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; This test tests several things. The load and store should use the
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; same address instead of having it computed twice, and SCEVExpander should
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; be able to reconstruct the full getelementptr, despite it having a few
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; obstacles set in its way.
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; We only check that the inner loop (bb1-bb2) is "reduced" because LSR
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; currently only operates on inner loops.
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target datalayout = "e-p:64:64:64-p1:16:16:16-n16:32:64"
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define void @foo(i64 %n, i64 %m, i64 %o, i64 %q, double addrspace(1)* nocapture %p) nounwind {
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entry:
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%tmp = icmp sgt i64 %n, 0 ; <i1> [#uses=1]
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br i1 %tmp, label %bb.nph3, label %return
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bb.nph: ; preds = %bb2.preheader
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%tmp1 = mul i64 %tmp16, %i.02 ; <i64> [#uses=1]
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%tmp2 = mul i64 %tmp19, %i.02 ; <i64> [#uses=1]
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br label %bb1
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bb1: ; preds = %bb2, %bb.nph
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%j.01 = phi i64 [ %tmp9, %bb2 ], [ 0, %bb.nph ] ; <i64> [#uses=3]
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%tmp3 = add i64 %j.01, %tmp1 ; <i64> [#uses=1]
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%tmp4 = add i64 %j.01, %tmp2 ; <i64> [#uses=1]
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%z0 = add i64 %tmp3, 5203
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%tmp5 = getelementptr double addrspace(1)* %p, i64 %z0 ; <double addrspace(1)*> [#uses=1]
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%tmp6 = load double addrspace(1)* %tmp5, align 8 ; <double> [#uses=1]
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%tmp7 = fdiv double %tmp6, 2.100000e+00 ; <double> [#uses=1]
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%z1 = add i64 %tmp4, 5203
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%tmp8 = getelementptr double addrspace(1)* %p, i64 %z1 ; <double addrspace(1)*> [#uses=1]
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store double %tmp7, double addrspace(1)* %tmp8, align 8
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%tmp9 = add i64 %j.01, 1 ; <i64> [#uses=2]
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br label %bb2
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bb2: ; preds = %bb1
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%tmp10 = icmp slt i64 %tmp9, %m ; <i1> [#uses=1]
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br i1 %tmp10, label %bb1, label %bb2.bb3_crit_edge
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bb2.bb3_crit_edge: ; preds = %bb2
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br label %bb3
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bb3: ; preds = %bb2.preheader, %bb2.bb3_crit_edge
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%tmp11 = add i64 %i.02, 1 ; <i64> [#uses=2]
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br label %bb4
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bb4: ; preds = %bb3
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%tmp12 = icmp slt i64 %tmp11, %n ; <i1> [#uses=1]
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br i1 %tmp12, label %bb2.preheader, label %bb4.return_crit_edge
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bb4.return_crit_edge: ; preds = %bb4
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br label %bb4.return_crit_edge.split
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bb4.return_crit_edge.split: ; preds = %bb.nph3, %bb4.return_crit_edge
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br label %return
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bb.nph3: ; preds = %entry
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%tmp13 = icmp sgt i64 %m, 0 ; <i1> [#uses=1]
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%tmp14 = mul i64 %n, 37 ; <i64> [#uses=1]
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%tmp15 = mul i64 %tmp14, %o ; <i64> [#uses=1]
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%tmp16 = mul i64 %tmp15, %q ; <i64> [#uses=1]
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%tmp17 = mul i64 %n, 37 ; <i64> [#uses=1]
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%tmp18 = mul i64 %tmp17, %o ; <i64> [#uses=1]
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%tmp19 = mul i64 %tmp18, %q ; <i64> [#uses=1]
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br i1 %tmp13, label %bb.nph3.split, label %bb4.return_crit_edge.split
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bb.nph3.split: ; preds = %bb.nph3
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br label %bb2.preheader
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bb2.preheader: ; preds = %bb.nph3.split, %bb4
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%i.02 = phi i64 [ %tmp11, %bb4 ], [ 0, %bb.nph3.split ] ; <i64> [#uses=3]
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br i1 true, label %bb.nph, label %bb3
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return: ; preds = %bb4.return_crit_edge.split, %entry
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ret void
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}
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