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llvm-project/llvm/test/CodeGen/Thumb2/thumb2-branch.ll

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Improve test cases from r134746. Use memory barriers to force if-conversion off for these tests instead of the internal llc command line option ifcvt-limit. llvm-svn: 134986
2011-07-13 00:06:01 +08:00
; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mattr=+thumb2 | FileCheck %s
Make tBX_RET and tBX_RET_vararg predicable. The normal tBX instruction is predicable, so there's no reason the pseudos for using it as a return shouldn't be. Gives us some nice code-gen improvements as can be seen by the test changes. In particular, several tests now have to disable if-conversion because it works too well and defeats the test. llvm-svn: 134746
2011-07-09 05:50:04 +08:00
; If-conversion defeats the purpose of this test, which is to check conditional
Improve test cases from r134746. Use memory barriers to force if-conversion off for these tests instead of the internal llc command line option ifcvt-limit. llvm-svn: 134986
2011-07-13 00:06:01 +08:00
; branch generation, so use memory barrier instruction to make sure it doesn't
; happen and we get actual branches.
Also shrink immediate branches; also more assembler workarounds. llvm-svn: 79014
2009-08-15 02:31:44 +08:00
Fix a bug which prevented tail merging of return instructions in beneficial cases. See the changes in test/CodeGen/X86/tail-opts.ll and test/CodeGen/ARM/ifcvt2.ll for details. The fix is to change HashEndOfMBB to hash at most one instruction, instead of trying to apply heuristics about when it will be profitable to consider more than one instruction. The regular tail-merging heuristics are already prepared to handle the same cases, and they're more precise. Also, make test/CodeGen/ARM/ifcvt5.ll and test/CodeGen/Thumb2/thumb2-branch.ll slightly more complex so that they continue to test what they're intended to test. And, this eliminates the problem in test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll, the testcase from PR5204. Update it accordingly. llvm-svn: 102907
2010-05-03 22:35:47 +08:00
define i32 @f1(i32 %a, i32 %b, i32* %v) {
Also shrink immediate branches; also more assembler workarounds. llvm-svn: 79014
2009-08-15 02:31:44 +08:00
entry:
; CHECK: f1:
Add missing colons for FileCheck. llvm-svn: 85674
2009-11-01 03:22:24 +08:00
; CHECK: bne LBB
Also shrink immediate branches; also more assembler workarounds. llvm-svn: 79014
2009-08-15 02:31:44 +08:00
%tmp = icmp eq i32 %a, %b ; <i1> [#uses=1]
br i1 %tmp, label %cond_true, label %return
cond_true: ; preds = %entry
Improve test cases from r134746. Use memory barriers to force if-conversion off for these tests instead of the internal llc command line option ifcvt-limit. llvm-svn: 134986
2011-07-13 00:06:01 +08:00
call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 false)
Also shrink immediate branches; also more assembler workarounds. llvm-svn: 79014
2009-08-15 02:31:44 +08:00
store i32 0, i32* %v
Fix a bug which prevented tail merging of return instructions in beneficial cases. See the changes in test/CodeGen/X86/tail-opts.ll and test/CodeGen/ARM/ifcvt2.ll for details. The fix is to change HashEndOfMBB to hash at most one instruction, instead of trying to apply heuristics about when it will be profitable to consider more than one instruction. The regular tail-merging heuristics are already prepared to handle the same cases, and they're more precise. Also, make test/CodeGen/ARM/ifcvt5.ll and test/CodeGen/Thumb2/thumb2-branch.ll slightly more complex so that they continue to test what they're intended to test. And, this eliminates the problem in test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll, the testcase from PR5204. Update it accordingly. llvm-svn: 102907
2010-05-03 22:35:47 +08:00
ret i32 0
Also shrink immediate branches; also more assembler workarounds. llvm-svn: 79014
2009-08-15 02:31:44 +08:00
return: ; preds = %entry
Improve test cases from r134746. Use memory barriers to force if-conversion off for these tests instead of the internal llc command line option ifcvt-limit. llvm-svn: 134986
2011-07-13 00:06:01 +08:00
call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 false)
Fix a bug which prevented tail merging of return instructions in beneficial cases. See the changes in test/CodeGen/X86/tail-opts.ll and test/CodeGen/ARM/ifcvt2.ll for details. The fix is to change HashEndOfMBB to hash at most one instruction, instead of trying to apply heuristics about when it will be profitable to consider more than one instruction. The regular tail-merging heuristics are already prepared to handle the same cases, and they're more precise. Also, make test/CodeGen/ARM/ifcvt5.ll and test/CodeGen/Thumb2/thumb2-branch.ll slightly more complex so that they continue to test what they're intended to test. And, this eliminates the problem in test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll, the testcase from PR5204. Update it accordingly. llvm-svn: 102907
2010-05-03 22:35:47 +08:00
ret i32 1
Also shrink immediate branches; also more assembler workarounds. llvm-svn: 79014
2009-08-15 02:31:44 +08:00
}
Fix a bug which prevented tail merging of return instructions in beneficial cases. See the changes in test/CodeGen/X86/tail-opts.ll and test/CodeGen/ARM/ifcvt2.ll for details. The fix is to change HashEndOfMBB to hash at most one instruction, instead of trying to apply heuristics about when it will be profitable to consider more than one instruction. The regular tail-merging heuristics are already prepared to handle the same cases, and they're more precise. Also, make test/CodeGen/ARM/ifcvt5.ll and test/CodeGen/Thumb2/thumb2-branch.ll slightly more complex so that they continue to test what they're intended to test. And, this eliminates the problem in test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll, the testcase from PR5204. Update it accordingly. llvm-svn: 102907
2010-05-03 22:35:47 +08:00
define i32 @f2(i32 %a, i32 %b, i32* %v) {
Also shrink immediate branches; also more assembler workarounds. llvm-svn: 79014
2009-08-15 02:31:44 +08:00
entry:
; CHECK: f2:
Add missing colons for FileCheck. llvm-svn: 85674
2009-11-01 03:22:24 +08:00
; CHECK: bge LBB
Also shrink immediate branches; also more assembler workarounds. llvm-svn: 79014
2009-08-15 02:31:44 +08:00
%tmp = icmp slt i32 %a, %b ; <i1> [#uses=1]
br i1 %tmp, label %cond_true, label %return
cond_true: ; preds = %entry
Improve test cases from r134746. Use memory barriers to force if-conversion off for these tests instead of the internal llc command line option ifcvt-limit. llvm-svn: 134986
2011-07-13 00:06:01 +08:00
call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 false)
Also shrink immediate branches; also more assembler workarounds. llvm-svn: 79014
2009-08-15 02:31:44 +08:00
store i32 0, i32* %v
Fix a bug which prevented tail merging of return instructions in beneficial cases. See the changes in test/CodeGen/X86/tail-opts.ll and test/CodeGen/ARM/ifcvt2.ll for details. The fix is to change HashEndOfMBB to hash at most one instruction, instead of trying to apply heuristics about when it will be profitable to consider more than one instruction. The regular tail-merging heuristics are already prepared to handle the same cases, and they're more precise. Also, make test/CodeGen/ARM/ifcvt5.ll and test/CodeGen/Thumb2/thumb2-branch.ll slightly more complex so that they continue to test what they're intended to test. And, this eliminates the problem in test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll, the testcase from PR5204. Update it accordingly. llvm-svn: 102907
2010-05-03 22:35:47 +08:00
ret i32 0
Also shrink immediate branches; also more assembler workarounds. llvm-svn: 79014
2009-08-15 02:31:44 +08:00
return: ; preds = %entry
Improve test cases from r134746. Use memory barriers to force if-conversion off for these tests instead of the internal llc command line option ifcvt-limit. llvm-svn: 134986
2011-07-13 00:06:01 +08:00
call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 false)
Fix a bug which prevented tail merging of return instructions in beneficial cases. See the changes in test/CodeGen/X86/tail-opts.ll and test/CodeGen/ARM/ifcvt2.ll for details. The fix is to change HashEndOfMBB to hash at most one instruction, instead of trying to apply heuristics about when it will be profitable to consider more than one instruction. The regular tail-merging heuristics are already prepared to handle the same cases, and they're more precise. Also, make test/CodeGen/ARM/ifcvt5.ll and test/CodeGen/Thumb2/thumb2-branch.ll slightly more complex so that they continue to test what they're intended to test. And, this eliminates the problem in test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll, the testcase from PR5204. Update it accordingly. llvm-svn: 102907
2010-05-03 22:35:47 +08:00
ret i32 1
Also shrink immediate branches; also more assembler workarounds. llvm-svn: 79014
2009-08-15 02:31:44 +08:00
}
Fix a bug which prevented tail merging of return instructions in beneficial cases. See the changes in test/CodeGen/X86/tail-opts.ll and test/CodeGen/ARM/ifcvt2.ll for details. The fix is to change HashEndOfMBB to hash at most one instruction, instead of trying to apply heuristics about when it will be profitable to consider more than one instruction. The regular tail-merging heuristics are already prepared to handle the same cases, and they're more precise. Also, make test/CodeGen/ARM/ifcvt5.ll and test/CodeGen/Thumb2/thumb2-branch.ll slightly more complex so that they continue to test what they're intended to test. And, this eliminates the problem in test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll, the testcase from PR5204. Update it accordingly. llvm-svn: 102907
2010-05-03 22:35:47 +08:00
define i32 @f3(i32 %a, i32 %b, i32* %v) {
Also shrink immediate branches; also more assembler workarounds. llvm-svn: 79014
2009-08-15 02:31:44 +08:00
entry:
; CHECK: f3:
Add missing colons for FileCheck. llvm-svn: 85674
2009-11-01 03:22:24 +08:00
; CHECK: bhs LBB
Also shrink immediate branches; also more assembler workarounds. llvm-svn: 79014
2009-08-15 02:31:44 +08:00
%tmp = icmp ult i32 %a, %b ; <i1> [#uses=1]
br i1 %tmp, label %cond_true, label %return
cond_true: ; preds = %entry
Improve test cases from r134746. Use memory barriers to force if-conversion off for these tests instead of the internal llc command line option ifcvt-limit. llvm-svn: 134986
2011-07-13 00:06:01 +08:00
call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 false)
Also shrink immediate branches; also more assembler workarounds. llvm-svn: 79014
2009-08-15 02:31:44 +08:00
store i32 0, i32* %v
Fix a bug which prevented tail merging of return instructions in beneficial cases. See the changes in test/CodeGen/X86/tail-opts.ll and test/CodeGen/ARM/ifcvt2.ll for details. The fix is to change HashEndOfMBB to hash at most one instruction, instead of trying to apply heuristics about when it will be profitable to consider more than one instruction. The regular tail-merging heuristics are already prepared to handle the same cases, and they're more precise. Also, make test/CodeGen/ARM/ifcvt5.ll and test/CodeGen/Thumb2/thumb2-branch.ll slightly more complex so that they continue to test what they're intended to test. And, this eliminates the problem in test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll, the testcase from PR5204. Update it accordingly. llvm-svn: 102907
2010-05-03 22:35:47 +08:00
ret i32 0
Also shrink immediate branches; also more assembler workarounds. llvm-svn: 79014
2009-08-15 02:31:44 +08:00
return: ; preds = %entry
Improve test cases from r134746. Use memory barriers to force if-conversion off for these tests instead of the internal llc command line option ifcvt-limit. llvm-svn: 134986
2011-07-13 00:06:01 +08:00
call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 false)
Fix a bug which prevented tail merging of return instructions in beneficial cases. See the changes in test/CodeGen/X86/tail-opts.ll and test/CodeGen/ARM/ifcvt2.ll for details. The fix is to change HashEndOfMBB to hash at most one instruction, instead of trying to apply heuristics about when it will be profitable to consider more than one instruction. The regular tail-merging heuristics are already prepared to handle the same cases, and they're more precise. Also, make test/CodeGen/ARM/ifcvt5.ll and test/CodeGen/Thumb2/thumb2-branch.ll slightly more complex so that they continue to test what they're intended to test. And, this eliminates the problem in test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll, the testcase from PR5204. Update it accordingly. llvm-svn: 102907
2010-05-03 22:35:47 +08:00
ret i32 1
Also shrink immediate branches; also more assembler workarounds. llvm-svn: 79014
2009-08-15 02:31:44 +08:00
}
Fix a bug which prevented tail merging of return instructions in beneficial cases. See the changes in test/CodeGen/X86/tail-opts.ll and test/CodeGen/ARM/ifcvt2.ll for details. The fix is to change HashEndOfMBB to hash at most one instruction, instead of trying to apply heuristics about when it will be profitable to consider more than one instruction. The regular tail-merging heuristics are already prepared to handle the same cases, and they're more precise. Also, make test/CodeGen/ARM/ifcvt5.ll and test/CodeGen/Thumb2/thumb2-branch.ll slightly more complex so that they continue to test what they're intended to test. And, this eliminates the problem in test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll, the testcase from PR5204. Update it accordingly. llvm-svn: 102907
2010-05-03 22:35:47 +08:00
define i32 @f4(i32 %a, i32 %b, i32* %v) {
Also shrink immediate branches; also more assembler workarounds. llvm-svn: 79014
2009-08-15 02:31:44 +08:00
entry:
; CHECK: f4:
Add missing colons for FileCheck. llvm-svn: 85674
2009-11-01 03:22:24 +08:00
; CHECK: blo LBB
Also shrink immediate branches; also more assembler workarounds. llvm-svn: 79014
2009-08-15 02:31:44 +08:00
%tmp = icmp ult i32 %a, %b ; <i1> [#uses=1]
br i1 %tmp, label %return, label %cond_true
cond_true: ; preds = %entry
Improve test cases from r134746. Use memory barriers to force if-conversion off for these tests instead of the internal llc command line option ifcvt-limit. llvm-svn: 134986
2011-07-13 00:06:01 +08:00
call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 false)
Also shrink immediate branches; also more assembler workarounds. llvm-svn: 79014
2009-08-15 02:31:44 +08:00
store i32 0, i32* %v
Fix a bug which prevented tail merging of return instructions in beneficial cases. See the changes in test/CodeGen/X86/tail-opts.ll and test/CodeGen/ARM/ifcvt2.ll for details. The fix is to change HashEndOfMBB to hash at most one instruction, instead of trying to apply heuristics about when it will be profitable to consider more than one instruction. The regular tail-merging heuristics are already prepared to handle the same cases, and they're more precise. Also, make test/CodeGen/ARM/ifcvt5.ll and test/CodeGen/Thumb2/thumb2-branch.ll slightly more complex so that they continue to test what they're intended to test. And, this eliminates the problem in test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll, the testcase from PR5204. Update it accordingly. llvm-svn: 102907
2010-05-03 22:35:47 +08:00
ret i32 0
Also shrink immediate branches; also more assembler workarounds. llvm-svn: 79014
2009-08-15 02:31:44 +08:00
return: ; preds = %entry
Improve test cases from r134746. Use memory barriers to force if-conversion off for these tests instead of the internal llc command line option ifcvt-limit. llvm-svn: 134986
2011-07-13 00:06:01 +08:00
call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 false)
Fix a bug which prevented tail merging of return instructions in beneficial cases. See the changes in test/CodeGen/X86/tail-opts.ll and test/CodeGen/ARM/ifcvt2.ll for details. The fix is to change HashEndOfMBB to hash at most one instruction, instead of trying to apply heuristics about when it will be profitable to consider more than one instruction. The regular tail-merging heuristics are already prepared to handle the same cases, and they're more precise. Also, make test/CodeGen/ARM/ifcvt5.ll and test/CodeGen/Thumb2/thumb2-branch.ll slightly more complex so that they continue to test what they're intended to test. And, this eliminates the problem in test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll, the testcase from PR5204. Update it accordingly. llvm-svn: 102907
2010-05-03 22:35:47 +08:00
ret i32 1
Also shrink immediate branches; also more assembler workarounds. llvm-svn: 79014
2009-08-15 02:31:44 +08:00
}
Improve test cases from r134746. Use memory barriers to force if-conversion off for these tests instead of the internal llc command line option ifcvt-limit. llvm-svn: 134986
2011-07-13 00:06:01 +08:00
declare void @llvm.memory.barrier(i1, i1, i1, i1, i1) nounwind