maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
llvm-project/llvm/test/CodeGen/Mips/atomic.ll

262 lines
8.6 KiB
LLVM
Raw Normal View History

[mips] Fix bug in test case. Disable machine LICM to prevent instruction from being moved out of a basic block. llvm-svn: 167322
2012-11-03 05:46:42 +08:00
; RUN: llc -march=mipsel --disable-machine-licm < %s | FileCheck %s
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
@x = common global i32 0, align 4
define i32 @AtomicLoadAdd32(i32 %incr) nounwind {
entry:
Convert more tests over to the new atomic instructions. llvm-svn: 140559
2011-09-27 04:27:49 +08:00
%0 = atomicrmw add i32* @x, i32 %incr monotonic
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
ret i32 %0
; CHECK: AtomicLoadAdd32:
Fix test cases. llvm-svn: 156697
2012-05-12 11:25:16 +08:00
; CHECK: lw $[[R0:[0-9]+]], %got(x)
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
; CHECK: $[[BB0:[A-Z_0-9]+]]:
; CHECK: ll $[[R1:[0-9]+]], 0($[[R0]])
; CHECK: addu $[[R2:[0-9]+]], $[[R1]], $4
; CHECK: sc $[[R2]], 0($[[R0]])
; CHECK: beq $[[R2]], $zero, $[[BB0]]
}
define i32 @AtomicLoadNand32(i32 %incr) nounwind {
entry:
Convert more tests over to the new atomic instructions. llvm-svn: 140559
2011-09-27 04:27:49 +08:00
%0 = atomicrmw nand i32* @x, i32 %incr monotonic
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
ret i32 %0
; CHECK: AtomicLoadNand32:
Fix test cases. llvm-svn: 156697
2012-05-12 11:25:16 +08:00
; CHECK: lw $[[R0:[0-9]+]], %got(x)
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
; CHECK: $[[BB0:[A-Z_0-9]+]]:
; CHECK: ll $[[R1:[0-9]+]], 0($[[R0]])
Set mayLoad or mayStore flags for SC and LL in order to prevent LICM from moving them out of the loop. Previously, stores and loads to a stack frame object were inserted to accomplish this. Remove the code that was needed to do this. Patch by Sasa Stankovic. llvm-svn: 135415
2011-07-19 02:52:12 +08:00
; CHECK: and $[[R3:[0-9]+]], $[[R1]], $4
; CHECK: nor $[[R2:[0-9]+]], $zero, $[[R3]]
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
; CHECK: sc $[[R2]], 0($[[R0]])
; CHECK: beq $[[R2]], $zero, $[[BB0]]
}
Set mayLoad or mayStore flags for SC and LL in order to prevent LICM from moving them out of the loop. Previously, stores and loads to a stack frame object were inserted to accomplish this. Remove the code that was needed to do this. Patch by Sasa Stankovic. llvm-svn: 135415
2011-07-19 02:52:12 +08:00
define i32 @AtomicSwap32(i32 %newval) nounwind {
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
entry:
Set mayLoad or mayStore flags for SC and LL in order to prevent LICM from moving them out of the loop. Previously, stores and loads to a stack frame object were inserted to accomplish this. Remove the code that was needed to do this. Patch by Sasa Stankovic. llvm-svn: 135415
2011-07-19 02:52:12 +08:00
%newval.addr = alloca i32, align 4
store i32 %newval, i32* %newval.addr, align 4
%tmp = load i32* %newval.addr, align 4
Convert more tests over to the new atomic instructions. llvm-svn: 140559
2011-09-27 04:27:49 +08:00
%0 = atomicrmw xchg i32* @x, i32 %tmp monotonic
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
ret i32 %0
; CHECK: AtomicSwap32:
Fix test cases. llvm-svn: 156697
2012-05-12 11:25:16 +08:00
; CHECK: lw $[[R0:[0-9]+]], %got(x)
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
; CHECK: $[[BB0:[A-Z_0-9]+]]:
Set mayLoad or mayStore flags for SC and LL in order to prevent LICM from moving them out of the loop. Previously, stores and loads to a stack frame object were inserted to accomplish this. Remove the code that was needed to do this. Patch by Sasa Stankovic. llvm-svn: 135415
2011-07-19 02:52:12 +08:00
; CHECK: ll ${{[0-9]+}}, 0($[[R0]])
; CHECK: sc $[[R2:[0-9]+]], 0($[[R0]])
; CHECK: beq $[[R2]], $zero, $[[BB0]]
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
}
define i32 @AtomicCmpSwap32(i32 %oldval, i32 %newval) nounwind {
entry:
Set mayLoad or mayStore flags for SC and LL in order to prevent LICM from moving them out of the loop. Previously, stores and loads to a stack frame object were inserted to accomplish this. Remove the code that was needed to do this. Patch by Sasa Stankovic. llvm-svn: 135415
2011-07-19 02:52:12 +08:00
%newval.addr = alloca i32, align 4
store i32 %newval, i32* %newval.addr, align 4
%tmp = load i32* %newval.addr, align 4
Convert more tests over to the new atomic instructions. llvm-svn: 140559
2011-09-27 04:27:49 +08:00
%0 = cmpxchg i32* @x, i32 %oldval, i32 %tmp monotonic
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
ret i32 %0
; CHECK: AtomicCmpSwap32:
Fix test cases. llvm-svn: 156697
2012-05-12 11:25:16 +08:00
; CHECK: lw $[[R0:[0-9]+]], %got(x)
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
; CHECK: $[[BB0:[A-Z_0-9]+]]:
; CHECK: ll $2, 0($[[R0]])
; CHECK: bne $2, $4, $[[BB1:[A-Z_0-9]+]]
Remove redundant instructions. - In EmitAtomicBinaryPartword, mask incr in loopMBB only if atomic.swap is the instruction being expanded, instead of masking it in thisMBB. - Remove redundant Or in EmitAtomicCmpSwap. llvm-svn: 135495
2011-07-20 02:14:26 +08:00
; CHECK: sc $[[R2:[0-9]+]], 0($[[R0]])
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
; CHECK: beq $[[R2]], $zero, $[[BB0]]
; CHECK: $[[BB1]]:
}
@y = common global i8 0, align 1
define signext i8 @AtomicLoadAdd8(i8 signext %incr) nounwind {
entry:
Convert more tests over to the new atomic instructions. llvm-svn: 140559
2011-09-27 04:27:49 +08:00
%0 = atomicrmw add i8* @y, i8 %incr monotonic
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
ret i8 %0
; CHECK: AtomicLoadAdd8:
Fix test cases. llvm-svn: 156697
2012-05-12 11:25:16 +08:00
; CHECK: lw $[[R0:[0-9]+]], %got(y)
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
; CHECK: addiu $[[R1:[0-9]+]], $zero, -4
; CHECK: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]
; CHECK: andi $[[R3:[0-9]+]], $[[R0]], 3
; CHECK: sll $[[R4:[0-9]+]], $[[R3]], 3
; CHECK: ori $[[R5:[0-9]+]], $zero, 255
Use the correct opcodes: SLLV/SRLV or AND must be used instead of SLL/SRL or ANDi, when the instruction does not have any immediate operands. llvm-svn: 135520
2011-07-20 04:34:00 +08:00
; CHECK: sllv $[[R6:[0-9]+]], $[[R5]], $[[R4]]
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
; CHECK: nor $[[R7:[0-9]+]], $zero, $[[R6]]
Use the correct opcodes: SLLV/SRLV or AND must be used instead of SLL/SRL or ANDi, when the instruction does not have any immediate operands. llvm-svn: 135520
2011-07-20 04:34:00 +08:00
; CHECK: sllv $[[R9:[0-9]+]], $4, $[[R4]]
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
; CHECK: $[[BB0:[A-Z_0-9]+]]:
; CHECK: ll $[[R10:[0-9]+]], 0($[[R2]])
; CHECK: addu $[[R11:[0-9]+]], $[[R10]], $[[R9]]
; CHECK: and $[[R12:[0-9]+]], $[[R11]], $[[R6]]
; CHECK: and $[[R13:[0-9]+]], $[[R10]], $[[R7]]
; CHECK: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]
; CHECK: sc $[[R14]], 0($[[R2]])
; CHECK: beq $[[R14]], $zero, $[[BB0]]
; CHECK: and $[[R15:[0-9]+]], $[[R10]], $[[R6]]
Use the correct opcodes: SLLV/SRLV or AND must be used instead of SLL/SRL or ANDi, when the instruction does not have any immediate operands. llvm-svn: 135520
2011-07-20 04:34:00 +08:00
; CHECK: srlv $[[R16:[0-9]+]], $[[R15]], $[[R4]]
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
; CHECK: sll $[[R17:[0-9]+]], $[[R16]], 24
; CHECK: sra $2, $[[R17]], 24
}
define signext i8 @AtomicLoadSub8(i8 signext %incr) nounwind {
entry:
Convert more tests over to the new atomic instructions. llvm-svn: 140559
2011-09-27 04:27:49 +08:00
%0 = atomicrmw sub i8* @y, i8 %incr monotonic
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
ret i8 %0
; CHECK: AtomicLoadSub8:
Fix test cases. llvm-svn: 156697
2012-05-12 11:25:16 +08:00
; CHECK: lw $[[R0:[0-9]+]], %got(y)
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
; CHECK: addiu $[[R1:[0-9]+]], $zero, -4
; CHECK: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]
; CHECK: andi $[[R3:[0-9]+]], $[[R0]], 3
; CHECK: sll $[[R4:[0-9]+]], $[[R3]], 3
; CHECK: ori $[[R5:[0-9]+]], $zero, 255
Use the correct opcodes: SLLV/SRLV or AND must be used instead of SLL/SRL or ANDi, when the instruction does not have any immediate operands. llvm-svn: 135520
2011-07-20 04:34:00 +08:00
; CHECK: sllv $[[R6:[0-9]+]], $[[R5]], $[[R4]]
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
; CHECK: nor $[[R7:[0-9]+]], $zero, $[[R6]]
Use the correct opcodes: SLLV/SRLV or AND must be used instead of SLL/SRL or ANDi, when the instruction does not have any immediate operands. llvm-svn: 135520
2011-07-20 04:34:00 +08:00
; CHECK: sllv $[[R9:[0-9]+]], $4, $[[R4]]
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
; CHECK: $[[BB0:[A-Z_0-9]+]]:
; CHECK: ll $[[R10:[0-9]+]], 0($[[R2]])
Do not treat atomic.load.sub differently than other atomic binary intrinsics. llvm-svn: 135418
2011-07-19 03:58:59 +08:00
; CHECK: subu $[[R11:[0-9]+]], $[[R10]], $[[R9]]
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
; CHECK: and $[[R12:[0-9]+]], $[[R11]], $[[R6]]
; CHECK: and $[[R13:[0-9]+]], $[[R10]], $[[R7]]
; CHECK: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]
; CHECK: sc $[[R14]], 0($[[R2]])
; CHECK: beq $[[R14]], $zero, $[[BB0]]
; CHECK: and $[[R15:[0-9]+]], $[[R10]], $[[R6]]
Use the correct opcodes: SLLV/SRLV or AND must be used instead of SLL/SRL or ANDi, when the instruction does not have any immediate operands. llvm-svn: 135520
2011-07-20 04:34:00 +08:00
; CHECK: srlv $[[R16:[0-9]+]], $[[R15]], $[[R4]]
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
; CHECK: sll $[[R17:[0-9]+]], $[[R16]], 24
; CHECK: sra $2, $[[R17]], 24
}
define signext i8 @AtomicLoadNand8(i8 signext %incr) nounwind {
entry:
Convert more tests over to the new atomic instructions. llvm-svn: 140559
2011-09-27 04:27:49 +08:00
%0 = atomicrmw nand i8* @y, i8 %incr monotonic
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
ret i8 %0
; CHECK: AtomicLoadNand8:
Fix test cases. llvm-svn: 156697
2012-05-12 11:25:16 +08:00
; CHECK: lw $[[R0:[0-9]+]], %got(y)
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
; CHECK: addiu $[[R1:[0-9]+]], $zero, -4
; CHECK: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]
; CHECK: andi $[[R3:[0-9]+]], $[[R0]], 3
; CHECK: sll $[[R4:[0-9]+]], $[[R3]], 3
; CHECK: ori $[[R5:[0-9]+]], $zero, 255
Use the correct opcodes: SLLV/SRLV or AND must be used instead of SLL/SRL or ANDi, when the instruction does not have any immediate operands. llvm-svn: 135520
2011-07-20 04:34:00 +08:00
; CHECK: sllv $[[R6:[0-9]+]], $[[R5]], $[[R4]]
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
; CHECK: nor $[[R7:[0-9]+]], $zero, $[[R6]]
Use the correct opcodes: SLLV/SRLV or AND must be used instead of SLL/SRL or ANDi, when the instruction does not have any immediate operands. llvm-svn: 135520
2011-07-20 04:34:00 +08:00
; CHECK: sllv $[[R9:[0-9]+]], $4, $[[R4]]
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
; CHECK: $[[BB0:[A-Z_0-9]+]]:
; CHECK: ll $[[R10:[0-9]+]], 0($[[R2]])
; CHECK: and $[[R18:[0-9]+]], $[[R10]], $[[R9]]
; CHECK: nor $[[R11:[0-9]+]], $zero, $[[R18]]
; CHECK: and $[[R12:[0-9]+]], $[[R11]], $[[R6]]
; CHECK: and $[[R13:[0-9]+]], $[[R10]], $[[R7]]
; CHECK: or $[[R14:[0-9]+]], $[[R13]], $[[R12]]
; CHECK: sc $[[R14]], 0($[[R2]])
; CHECK: beq $[[R14]], $zero, $[[BB0]]
; CHECK: and $[[R15:[0-9]+]], $[[R10]], $[[R6]]
Use the correct opcodes: SLLV/SRLV or AND must be used instead of SLL/SRL or ANDi, when the instruction does not have any immediate operands. llvm-svn: 135520
2011-07-20 04:34:00 +08:00
; CHECK: srlv $[[R16:[0-9]+]], $[[R15]], $[[R4]]
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
; CHECK: sll $[[R17:[0-9]+]], $[[R16]], 24
; CHECK: sra $2, $[[R17]], 24
}
Set mayLoad or mayStore flags for SC and LL in order to prevent LICM from moving them out of the loop. Previously, stores and loads to a stack frame object were inserted to accomplish this. Remove the code that was needed to do this. Patch by Sasa Stankovic. llvm-svn: 135415
2011-07-19 02:52:12 +08:00
define signext i8 @AtomicSwap8(i8 signext %newval) nounwind {
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
entry:
Convert more tests over to the new atomic instructions. llvm-svn: 140559
2011-09-27 04:27:49 +08:00
%0 = atomicrmw xchg i8* @y, i8 %newval monotonic
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
ret i8 %0
; CHECK: AtomicSwap8:
Fix test cases. llvm-svn: 156697
2012-05-12 11:25:16 +08:00
; CHECK: lw $[[R0:[0-9]+]], %got(y)
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
; CHECK: addiu $[[R1:[0-9]+]], $zero, -4
; CHECK: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]
; CHECK: andi $[[R3:[0-9]+]], $[[R0]], 3
; CHECK: sll $[[R4:[0-9]+]], $[[R3]], 3
; CHECK: ori $[[R5:[0-9]+]], $zero, 255
Use the correct opcodes: SLLV/SRLV or AND must be used instead of SLL/SRL or ANDi, when the instruction does not have any immediate operands. llvm-svn: 135520
2011-07-20 04:34:00 +08:00
; CHECK: sllv $[[R6:[0-9]+]], $[[R5]], $[[R4]]
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
; CHECK: nor $[[R7:[0-9]+]], $zero, $[[R6]]
Use the correct opcodes: SLLV/SRLV or AND must be used instead of SLL/SRL or ANDi, when the instruction does not have any immediate operands. llvm-svn: 135520
2011-07-20 04:34:00 +08:00
; CHECK: sllv $[[R9:[0-9]+]], $4, $[[R4]]
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
; CHECK: $[[BB0:[A-Z_0-9]+]]:
; CHECK: ll $[[R10:[0-9]+]], 0($[[R2]])
[mips] Fix bug in test case. Disable machine LICM to prevent instruction from being moved out of a basic block. llvm-svn: 167322
2012-11-03 05:46:42 +08:00
; CHECK: and $[[R18:[0-9]+]], $[[R9]], $[[R6]]
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
; CHECK: and $[[R13:[0-9]+]], $[[R10]], $[[R7]]
[mips] Fix bug in test case. Disable machine LICM to prevent instruction from being moved out of a basic block. llvm-svn: 167322
2012-11-03 05:46:42 +08:00
; CHECK: or $[[R14:[0-9]+]], $[[R13]], $[[R18]]
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
; CHECK: sc $[[R14]], 0($[[R2]])
; CHECK: beq $[[R14]], $zero, $[[BB0]]
; CHECK: and $[[R15:[0-9]+]], $[[R10]], $[[R6]]
Use the correct opcodes: SLLV/SRLV or AND must be used instead of SLL/SRL or ANDi, when the instruction does not have any immediate operands. llvm-svn: 135520
2011-07-20 04:34:00 +08:00
; CHECK: srlv $[[R16:[0-9]+]], $[[R15]], $[[R4]]
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
; CHECK: sll $[[R17:[0-9]+]], $[[R16]], 24
; CHECK: sra $2, $[[R17]], 24
}
define signext i8 @AtomicCmpSwap8(i8 signext %oldval, i8 signext %newval) nounwind {
entry:
Convert more tests over to the new atomic instructions. llvm-svn: 140559
2011-09-27 04:27:49 +08:00
%0 = cmpxchg i8* @y, i8 %oldval, i8 %newval monotonic
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
ret i8 %0
; CHECK: AtomicCmpSwap8:
Fix test cases. llvm-svn: 156697
2012-05-12 11:25:16 +08:00
; CHECK: lw $[[R0:[0-9]+]], %got(y)
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
; CHECK: addiu $[[R1:[0-9]+]], $zero, -4
; CHECK: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]
; CHECK: andi $[[R3:[0-9]+]], $[[R0]], 3
; CHECK: sll $[[R4:[0-9]+]], $[[R3]], 3
; CHECK: ori $[[R5:[0-9]+]], $zero, 255
Use the correct opcodes: SLLV/SRLV or AND must be used instead of SLL/SRL or ANDi, when the instruction does not have any immediate operands. llvm-svn: 135520
2011-07-20 04:34:00 +08:00
; CHECK: sllv $[[R6:[0-9]+]], $[[R5]], $[[R4]]
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
; CHECK: nor $[[R7:[0-9]+]], $zero, $[[R6]]
; CHECK: andi $[[R8:[0-9]+]], $4, 255
Use the correct opcodes: SLLV/SRLV or AND must be used instead of SLL/SRL or ANDi, when the instruction does not have any immediate operands. llvm-svn: 135520
2011-07-20 04:34:00 +08:00
; CHECK: sllv $[[R9:[0-9]+]], $[[R8]], $[[R4]]
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
; CHECK: andi $[[R10:[0-9]+]], $5, 255
Use the correct opcodes: SLLV/SRLV or AND must be used instead of SLL/SRL or ANDi, when the instruction does not have any immediate operands. llvm-svn: 135520
2011-07-20 04:34:00 +08:00
; CHECK: sllv $[[R11:[0-9]+]], $[[R10]], $[[R4]]
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
; CHECK: $[[BB0:[A-Z_0-9]+]]:
; CHECK: ll $[[R12:[0-9]+]], 0($[[R2]])
; CHECK: and $[[R13:[0-9]+]], $[[R12]], $[[R6]]
; CHECK: bne $[[R13]], $[[R9]], $[[BB1:[A-Z_0-9]+]]
; CHECK: and $[[R14:[0-9]+]], $[[R12]], $[[R7]]
; CHECK: or $[[R15:[0-9]+]], $[[R14]], $[[R11]]
; CHECK: sc $[[R15]], 0($[[R2]])
; CHECK: beq $[[R15]], $zero, $[[BB0]]
; CHECK: $[[BB1]]:
Use the correct opcodes: SLLV/SRLV or AND must be used instead of SLL/SRL or ANDi, when the instruction does not have any immediate operands. llvm-svn: 135520
2011-07-20 04:34:00 +08:00
; CHECK: srlv $[[R16:[0-9]+]], $[[R13]], $[[R4]]
This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. llvm-svn: 132323
2011-05-31 10:54:07 +08:00
; CHECK: sll $[[R17:[0-9]+]], $[[R16]], 24
; CHECK: sra $2, $[[R17]], 24
}
Lower memory barriers to sync instructions. llvm-svn: 135537
2011-07-20 07:30:50 +08:00
@countsint = common global i32 0, align 4
define i32 @CheckSync(i32 %v) nounwind noinline {
entry:
Convert more tests over to the new atomic instructions. llvm-svn: 140559
2011-09-27 04:27:49 +08:00
%0 = atomicrmw add i32* @countsint, i32 %v seq_cst
Lower memory barriers to sync instructions. llvm-svn: 135537
2011-07-20 07:30:50 +08:00
ret i32 %0
; CHECK: CheckSync:
; CHECK: sync 0
; CHECK: ll
; CHECK: sc
; CHECK: beq
; CHECK: sync 0
}
Do not replace operands of pseudo instructions with register $zero. llvm-svn: 156663
2012-05-12 07:22:18 +08:00
; make sure that this assertion in
; TwoAddressInstructionPass::TryInstructionTransform does not fail:
;
; line 1203: assert(TargetRegisterInfo::isVirtualRegister(regB) &&
;
; it failed when MipsDAGToDAGISel::ReplaceUsesWithZeroReg replaced an
; operand of an atomic instruction with register $zero.
@a = external global i32
define i32 @zeroreg() nounwind {
entry:
%0 = cmpxchg i32* @a, i32 1, i32 0 seq_cst
%1 = icmp eq i32 %0, 1
%conv = zext i1 %1 to i32
ret i32 %conv
}