maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
llvm-project/llvm/test/CodeGen/Hexagon/mux-undef.ll

Ignoring revisions in .git-blame-ignore-revs. Click here to bypass and see the normal blame view.

28 lines
648 B
LLVM
Raw Normal View History

[Hexagon] Skip mux generation when predicate register is undefined llvm-svn: 305014
2017-06-09 04:56:36 +08:00
; RUN: llc -march=hexagon -verify-machineinstrs < %s | FileCheck %s
;
; Make sure this test compiles successfully.
[Hexagon] Simplify CFG after atomic expansion This will remove suboptimal branching from the generated ll/sc loops. The extra simplification pass affects a lot of testcases, which have been modified to accommodate this change: either by modifying the test to become immune to the CFG simplification, or (less preferablt) by adding option -hexagon-initial-cfg-clenaup=0. llvm-svn: 338774
2018-08-03 06:17:53 +08:00
; CHECK: call foo
[Hexagon] Skip mux generation when predicate register is undefined llvm-svn: 305014
2017-06-09 04:56:36 +08:00
target triple = "hexagon--elf"
; Function Attrs: nounwind
[Hexagon] Simplify CFG after atomic expansion This will remove suboptimal branching from the generated ll/sc loops. The extra simplification pass affects a lot of testcases, which have been modified to accommodate this change: either by modifying the test to become immune to the CFG simplification, or (less preferablt) by adding option -hexagon-initial-cfg-clenaup=0. llvm-svn: 338774
2018-08-03 06:17:53 +08:00
define i32 @fred(i1 %a0) #0 {
[Hexagon] Skip mux generation when predicate register is undefined llvm-svn: 305014
2017-06-09 04:56:36 +08:00
b0:
call void @foo() #0
br label %b1
b1: ; preds = %b0
[Hexagon] Simplify CFG after atomic expansion This will remove suboptimal branching from the generated ll/sc loops. The extra simplification pass affects a lot of testcases, which have been modified to accommodate this change: either by modifying the test to become immune to the CFG simplification, or (less preferablt) by adding option -hexagon-initial-cfg-clenaup=0. llvm-svn: 338774
2018-08-03 06:17:53 +08:00
br i1 %a0, label %b2, label %b3
[Hexagon] Skip mux generation when predicate register is undefined llvm-svn: 305014
2017-06-09 04:56:36 +08:00
b2: ; preds = %b1
br label %b3
b3: ; preds = %b2, %b1
%v4 = phi i32 [ 1, %b1 ], [ 2, %b2 ]
ret i32 %v4
}
declare void @foo() #0
attributes #0 = { nounwind "target-cpu"="hexagonv60" }