llvm-project/llvm/test/CodeGen/Hexagon/expand-condsets-imm.mir

# RUN: llc -march=hexagon -run-pass expand-condsets %s -o - | FileCheck %s
# Check that we can expand a mux with a global as an immediate operand.
# CHECK: C2_cmoveif undef %0:predregs, @G

--- |
  @G = global i32 0, align 4
  define void @fred() { ret void }
...
---
name: fred
tracksRegLiveness: true

registers:
  - { id: 0, class: predregs }
  - { id: 1, class: intregs }
body: |
  bb.1:
    %1 = IMPLICIT_DEF
    %1 = C2_muxir undef %0, %1, @G
    $r0 = COPY %1
...
[Hexagon] Handle more types of immediate operands in expand-condsets llvm-svn: 305943 2017-06-22 03:21:30 +08:00			`# RUN: llc -march=hexagon -run-pass expand-condsets %s -o - \| FileCheck %s`
			`# Check that we can expand a mux with a global as an immediate operand.`
MIR: Print the register class or bank in vreg defs This updates the MIRPrinter to include the regclass when printing virtual register defs, which is already valid syntax for the parser. That is, given 64 bit %0 and %1 in a "gpr" regbank, %1(s64) = COPY %0(s64) would now be written as %1:gpr(s64) = COPY %0(s64) While this change alone introduces a bit of redundancy with the registers block, it allows us to update the tests to be more concise and understandable and brings us closer to being able to remove the registers block completely. Note: We generally only print the class in defs, but there is one exception. If there are uses without any defs whatsoever, we'll print the class on all uses. I'm not completely convinced this comes up in meaningful machine IR, but for now the MIRParser and MachineVerifier both accept that kind of stuff, so we don't want to have a situation where we can print something we can't parse. llvm-svn: 316479 2017-10-25 02:04:54 +08:00			`# CHECK: C2_cmoveif undef %0:predregs, @G`
[Hexagon] Handle more types of immediate operands in expand-condsets llvm-svn: 305943 2017-06-22 03:21:30 +08:00
			`--- \|`
			`@G = global i32 0, align 4`
			`define void @fred() { ret void }`
			`...`
			`---`
			`name: fred`
			`tracksRegLiveness: true`

			`registers:`
			`- { id: 0, class: predregs }`
			`- { id: 1, class: intregs }`
			`body: \|`
			`bb.1:`
			`%1 = IMPLICIT_DEF`
			`%1 = C2_muxir undef %0, %1, @G`
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922 2018-02-01 06:04:26 +08:00			`$r0 = COPY %1`
[Hexagon] Handle more types of immediate operands in expand-condsets llvm-svn: 305943 2017-06-22 03:21:30 +08:00			`...`