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llvm-project/llvm/test/CodeGen/AArch64/pacbti-module-attrs.ll

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[AArch64] PAC/BTI code generation for LLVM generated functions PAC/BTI-related codegen in the AArch64 backend is controlled by a set of LLVM IR function attributes, added to the function by Clang, based on command-line options and GCC-style function attributes. However, functions, generated in the LLVM middle end (for example, asan.module.ctor or __llvm_gcov_write_out) do not get any attributes and the backend incorrectly does not do any PAC/BTI code generation. This patch record the default state of PAC/BTI codegen in a set of LLVM IR module-level attributes, based on command-line options: * "sign-return-address", with non-zero value means generate code to sign return addresses (PAC-RET), zero value means disable PAC-RET. * "sign-return-address-all", with non-zero value means enable PAC-RET for all functions, zero value means enable PAC-RET only for functions, which spill LR. * "sign-return-address-with-bkey", with non-zero value means use B-key for signing, zero value mean use A-key. This set of attributes are always added for AArch64 targets (as opposed, for example, to interpreting a missing attribute as having a value 0) in order to be able to check for conflicts when combining module attributed during LTO. Module-level attributes are overridden by function level attributes. All the decision making about whether to not to generate PAC and/or BTI code is factored out into AArch64FunctionInfo, there shouldn't be any places left, other than AArch64FunctionInfo, which directly examine PAC/BTI attributes, except AArch64AsmPrinter.cpp, which is/will-be handled by a separate patch. Differential Revision: https://reviews.llvm.org/D85649
2020-09-25 18:45:22 +08:00
;; RUN: llc -mtriple=aarch64-eabi -mattr=+v8.5a %s -o - | FileCheck %s
declare i32 @g(i32) #5
define i32 @f0(i32 %x) #0 {
entry:
%call = tail call i32 @g(i32 %x) #5
%add = add nsw i32 %call, 1
ret i32 %add
}
;; CHECK-LABEL: f0:
;; CHECK-NOT: bti
;; CHECK-NOT: pacia
;; CHECK-NOT: reta
define i32 @f1(i32 %x) #1 {
entry:
%call = tail call i32 @g(i32 %x) #5
%add = add nsw i32 %call, 1
ret i32 %add
}
;; CHECK-LABEL: f1:
;; CHECK: bti c
;; CHECK-NOT: reta
define i32 @f2(i32 %x) #2 {
entry:
%call = tail call i32 @g(i32 %x) #5
%add = add nsw i32 %call, 1
ret i32 %add
}
;; CHECK-LABEL: f2:
;; CHECK: paciasp
;; CHECK: retaa
define i32 @f3(i32 %x) #3 {
entry:
%call = tail call i32 @g(i32 %x) #5
%add = add nsw i32 %call, 1
ret i32 %add
}
;; CHECK-LABEL: f3:
;; CHECK: pacibsp
;; CHECK: retab
define i32 @f4(i32 %x) #4 {
entry:
ret i32 1
}
;; CHECK-LABEL: f4:
;; CHECK: paciasp
;; CHECK: retaa
define i32 @f5(i32 %x) #5 {
entry:
%call = tail call i32 @g(i32 %x) #5
%add = add nsw i32 %call, 1
ret i32 %add
}
;; CHECK-LABEL: f5:
;; CHECK: paciasp
;; CHECK: retaa
attributes #0 = { nounwind "branch-target-enforcement"="false" "sign-return-address"="none" }
attributes #1 = { nounwind "branch-target-enforcement"="true" "sign-return-address"="none" }
attributes #2 = { nounwind "branch-target-enforcement"="false" "sign-return-address"="non-leaf" "sign-return-address-key"="a_key" }
attributes #3 = { nounwind "branch-target-enforcement"="false" "sign-return-address"="non-leaf" "sign-return-address-key"="b_key" }
attributes #4 = { nounwind "branch-target-enforcement"="false" "sign-return-address"="all" "sign-return-address-key"="a_key" }
attributes #5 = { nounwind }
!llvm.module.flags = !{!0, !1, !2, !3, !4}
!0 = !{i32 1, !"wchar_size", i32 4}
!1 = !{i32 1, !"branch-target-enforcement", i32 1}
!2 = !{i32 1, !"sign-return-address", i32 1}
!3 = !{i32 1, !"sign-return-address-all", i32 0}
!4 = !{i32 1, !"sign-return-address-with-bkey", i32 0}