2012-10-04 03:00:20 +08:00
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//===-- X86IntelInstPrinter.cpp - Intel assembly instruction printing -----===//
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2009-09-20 15:17:49 +08:00
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//
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2019-01-19 16:50:56 +08:00
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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2009-09-20 15:17:49 +08:00
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//
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//===----------------------------------------------------------------------===//
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//
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2012-10-04 03:00:20 +08:00
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// This file includes code for rendering MCInst instances as Intel-style
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2009-09-20 15:17:49 +08:00
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// assembly.
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//
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//===----------------------------------------------------------------------===//
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2017-06-06 19:49:48 +08:00
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#include "X86IntelInstPrinter.h"
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2019-05-11 07:24:38 +08:00
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#include "X86BaseInfo.h"
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2012-12-04 00:50:05 +08:00
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#include "X86InstComments.h"
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2009-09-20 15:17:49 +08:00
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#include "llvm/MC/MCExpr.h"
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2012-12-04 00:50:05 +08:00
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#include "llvm/MC/MCInst.h"
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[llvm-objdump] Symbolize binary addresses for low-noisy asm diff.
When diffing disassembly dump of two binaries, I see lots of noises from mismatched jump target addresses and global data references, which unnecessarily causes diffs on every function, making it impractical. I'm trying to symbolize the raw binary addresses to minimize the diff noise.
In this change, a local branch target is modeled as a label and the branch target operand will simply be printed as a label. Local labels are collected by a separate pre-decoding pass beforehand. A global data memory operand will be printed as a global symbol instead of the raw data address. Unfortunately, due to the way the disassembler is set up and to be less intrusive, a global symbol is always printed as the last operand of a memory access instruction. This is less than ideal but is probably acceptable from checking code quality point of view since on most targets an instruction can have at most one memory operand.
So far only the X86 disassemblers are supported.
Test Plan:
llvm-objdump -d --x86-asm-syntax=intel --no-show-raw-insn --no-leading-addr :
```
Disassembly of section .text:
<_start>:
push rax
mov dword ptr [rsp + 4], 0
mov dword ptr [rsp], 0
mov eax, dword ptr [rsp]
cmp eax, dword ptr [rip + 4112] # 202182 <g>
jge 0x20117e <_start+0x25>
call 0x201158 <foo>
inc dword ptr [rsp]
jmp 0x201169 <_start+0x10>
xor eax, eax
pop rcx
ret
```
llvm-objdump -d **--symbolize-operands** --x86-asm-syntax=intel --no-show-raw-insn --no-leading-addr :
```
Disassembly of section .text:
<_start>:
push rax
mov dword ptr [rsp + 4], 0
mov dword ptr [rsp], 0
<L1>:
mov eax, dword ptr [rsp]
cmp eax, dword ptr <g>
jge <L0>
call <foo>
inc dword ptr [rsp]
jmp <L1>
<L0>:
xor eax, eax
pop rcx
ret
```
Note that the jump instructions like `jge 0x20117e <_start+0x25>` without this work is printed as a real target address and an offset from the leading symbol. With a change in the optimizer that adds/deletes an instruction, the address and offset may shift for targets placed after the instruction. This will be a problem when diffing the disassembly from two optimizers where there are unnecessary false positives due to such branch target address changes. With `--symbolize-operand`, a label is printed for a branch target instead to reduce the false positives. Similarly, the disassemble of PC-relative global variable references is also prone to instruction insertion/deletion.
Reviewed By: jhenderson, MaskRay
Differential Revision: https://reviews.llvm.org/D84191
2020-07-21 00:45:32 +08:00
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#include "llvm/MC/MCInstrAnalysis.h"
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2017-02-07 05:55:43 +08:00
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#include "llvm/MC/MCInstrDesc.h"
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2012-04-02 15:01:04 +08:00
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#include "llvm/MC/MCInstrInfo.h"
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2018-04-22 08:52:02 +08:00
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#include "llvm/MC/MCSubtargetInfo.h"
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2017-02-07 05:55:43 +08:00
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#include "llvm/Support/Casting.h"
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2009-09-20 15:17:49 +08:00
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#include "llvm/Support/ErrorHandling.h"
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2017-02-07 05:55:43 +08:00
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#include <cassert>
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#include <cstdint>
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2009-09-20 15:17:49 +08:00
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using namespace llvm;
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2014-04-22 10:41:26 +08:00
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#define DEBUG_TYPE "asm-printer"
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2019-03-13 08:43:03 +08:00
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// Include the auto-generated portion of the assembly writer.
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#define PRINT_ALIAS_INSTR
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2009-09-20 15:17:49 +08:00
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#include "X86GenAsmWriter1.inc"
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2011-06-02 10:34:55 +08:00
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void X86IntelInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
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OS << getRegisterName(RegNo);
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2011-05-31 04:20:15 +08:00
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}
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2020-01-04 02:55:30 +08:00
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void X86IntelInstPrinter::printInst(const MCInst *MI, uint64_t Address,
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StringRef Annot, const MCSubtargetInfo &STI,
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raw_ostream &OS) {
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2018-06-05 18:41:39 +08:00
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printInstFlags(MI, OS);
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2018-03-17 21:29:46 +08:00
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2018-04-22 08:52:02 +08:00
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// In 16-bit mode, print data16 as data32.
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if (MI->getOpcode() == X86::DATA16_PREFIX &&
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STI.getFeatureBits()[X86::Mode16Bit]) {
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OS << "\tdata32";
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2020-03-27 14:55:43 +08:00
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} else if (!printAliasInstr(MI, Address, OS) && !printVecCompareInstr(MI, OS))
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2020-01-04 04:02:46 +08:00
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printInstruction(MI, Address, OS);
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2012-02-24 02:18:17 +08:00
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// Next always print the annotation.
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printAnnotation(OS, Annot);
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I have manually decoded the imm field of an insertps one too many
times. This patch causes llc and llvm-mc (which both default to
verbose-asm) to print out comments after a few common shuffle
instructions which indicates the shuffle mask, e.g.:
insertps $113, %xmm3, %xmm0 ## xmm0 = zero,xmm0[1,2],xmm3[1]
unpcklps %xmm1, %xmm0 ## xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
pshufd $1, %xmm1, %xmm1 ## xmm1 = xmm1[1,0,0,0]
This is carefully factored to keep the information extraction (of the
shuffle mask) separate from the printing logic. I plan to move the
extraction part out somewhere else at some point for other parts of
the x86 backend that want to introspect on the behavior of shuffles.
llvm-svn: 112387
2010-08-29 04:42:31 +08:00
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// If verbose assembly is enabled, we can print some informative comments.
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2012-02-24 02:18:17 +08:00
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if (CommentStream)
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2018-03-29 12:14:04 +08:00
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EmitAnyX86InstComments(MI, *CommentStream, MII);
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2010-04-04 12:47:45 +08:00
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}
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2009-09-20 15:17:49 +08:00
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[X86] Remove the _alt forms of XOP VPCOM instructions. Use a combination of custom printing and custom parsing to achieve the same result and more
Previously we had a regular form of the instruction used when the immediate was 0-7. And _alt form that allowed the full 8 bit immediate. Codegen would always use the 0-7 form since the immediate was always checked to be in range. Assembly parsing would use the 0-7 form when a mnemonic like vpcomtrueb was used. If the immediate was specified directly the _alt form was used. The disassembler would prefer to use the 0-7 form instruction when the immediate was in range and the _alt form otherwise. This way disassembly would print the most readable form when possible.
The assembly parsing for things like vpcomtrueb relied on splitting the mnemonic into 3 pieces. A "vpcom" prefix, an immediate representing the "true", and a suffix of "b". The tablegenerated printing code would similarly print a "vpcom" prefix, decode the immediate into a string, and then print "b".
The _alt form on the other hand parsed and printed like any other instruction with no specialness.
With this patch we drop to one form and solve the disassembly printing issue by doing custom printing when the immediate is 0-7. The parsing code has been tweaked to turn "vpcomtrueb" into "vpcomb" and then the immediate for the "true" is inserted either before or after the other operands depending on at&t or intel syntax.
I'd rather not do the custom printing, but I tried using an InstAlias for each possible mnemonic for all 8 immediates for all 16 combinations of element size, signedness, and memory/register. The code emitted into printAliasInstr ended up checking the number of operands, the register class of each operand, and the immediate for all 256 aliases. This was repeated for both the at&t and intel printer. Despite a lot of common checks between all of the aliases, when compiled with clang at least this commonality was not well optimized. Nor do all the checks seem necessary. Since I want to do a similar thing for vcmpps/pd/ss/sd which have 32 immediate values and 3 encoding flavors, 3 register sizes, etc. This didn't seem to scale well for clang binary size. So custom printing seemed a better trade off.
I also considered just using the InstAlias for the matching and not the printing. But that seemed like it would add a lot of extra rows to the matcher table. Especially given that the 32 immediates for vpcmpps have 46 strings associated with them.
Differential Revision: https://reviews.llvm.org/D59398
llvm-svn: 356343
2019-03-18 05:21:37 +08:00
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bool X86IntelInstPrinter::printVecCompareInstr(const MCInst *MI, raw_ostream &OS) {
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if (MI->getNumOperands() == 0 ||
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!MI->getOperand(MI->getNumOperands() - 1).isImm())
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return false;
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2019-03-18 15:05:01 +08:00
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int64_t Imm = MI->getOperand(MI->getNumOperands() - 1).getImm();
|
[X86] Remove the _alt forms of XOP VPCOM instructions. Use a combination of custom printing and custom parsing to achieve the same result and more
Previously we had a regular form of the instruction used when the immediate was 0-7. And _alt form that allowed the full 8 bit immediate. Codegen would always use the 0-7 form since the immediate was always checked to be in range. Assembly parsing would use the 0-7 form when a mnemonic like vpcomtrueb was used. If the immediate was specified directly the _alt form was used. The disassembler would prefer to use the 0-7 form instruction when the immediate was in range and the _alt form otherwise. This way disassembly would print the most readable form when possible.
The assembly parsing for things like vpcomtrueb relied on splitting the mnemonic into 3 pieces. A "vpcom" prefix, an immediate representing the "true", and a suffix of "b". The tablegenerated printing code would similarly print a "vpcom" prefix, decode the immediate into a string, and then print "b".
The _alt form on the other hand parsed and printed like any other instruction with no specialness.
With this patch we drop to one form and solve the disassembly printing issue by doing custom printing when the immediate is 0-7. The parsing code has been tweaked to turn "vpcomtrueb" into "vpcomb" and then the immediate for the "true" is inserted either before or after the other operands depending on at&t or intel syntax.
I'd rather not do the custom printing, but I tried using an InstAlias for each possible mnemonic for all 8 immediates for all 16 combinations of element size, signedness, and memory/register. The code emitted into printAliasInstr ended up checking the number of operands, the register class of each operand, and the immediate for all 256 aliases. This was repeated for both the at&t and intel printer. Despite a lot of common checks between all of the aliases, when compiled with clang at least this commonality was not well optimized. Nor do all the checks seem necessary. Since I want to do a similar thing for vcmpps/pd/ss/sd which have 32 immediate values and 3 encoding flavors, 3 register sizes, etc. This didn't seem to scale well for clang binary size. So custom printing seemed a better trade off.
I also considered just using the InstAlias for the matching and not the printing. But that seemed like it would add a lot of extra rows to the matcher table. Especially given that the 32 immediates for vpcmpps have 46 strings associated with them.
Differential Revision: https://reviews.llvm.org/D59398
llvm-svn: 356343
2019-03-18 05:21:37 +08:00
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const MCInstrDesc &Desc = MII.get(MI->getOpcode());
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// Custom print the vector compare instructions to get the immediate
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// translated into the mnemonic.
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switch (MI->getOpcode()) {
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2019-03-19 01:59:59 +08:00
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case X86::CMPPDrmi: case X86::CMPPDrri:
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case X86::CMPPSrmi: case X86::CMPPSrri:
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case X86::CMPSDrm: case X86::CMPSDrr:
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case X86::CMPSDrm_Int: case X86::CMPSDrr_Int:
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case X86::CMPSSrm: case X86::CMPSSrr:
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case X86::CMPSSrm_Int: case X86::CMPSSrr_Int:
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if (Imm >= 0 && Imm <= 7) {
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OS << '\t';
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printCMPMnemonic(MI, /*IsVCMP*/false, OS);
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printOperand(MI, 0, OS);
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OS << ", ";
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// Skip operand 1 as its tied to the dest.
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if ((Desc.TSFlags & X86II::FormMask) == X86II::MRMSrcMem) {
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if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XS)
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printdwordmem(MI, 2, OS);
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else if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XD)
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printqwordmem(MI, 2, OS);
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else
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printxmmwordmem(MI, 2, OS);
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} else
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printOperand(MI, 2, OS);
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return true;
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}
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break;
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case X86::VCMPPDrmi: case X86::VCMPPDrri:
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case X86::VCMPPDYrmi: case X86::VCMPPDYrri:
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case X86::VCMPPDZ128rmi: case X86::VCMPPDZ128rri:
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case X86::VCMPPDZ256rmi: case X86::VCMPPDZ256rri:
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case X86::VCMPPDZrmi: case X86::VCMPPDZrri:
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case X86::VCMPPSrmi: case X86::VCMPPSrri:
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case X86::VCMPPSYrmi: case X86::VCMPPSYrri:
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case X86::VCMPPSZ128rmi: case X86::VCMPPSZ128rri:
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case X86::VCMPPSZ256rmi: case X86::VCMPPSZ256rri:
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case X86::VCMPPSZrmi: case X86::VCMPPSZrri:
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case X86::VCMPSDrm: case X86::VCMPSDrr:
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case X86::VCMPSDZrm: case X86::VCMPSDZrr:
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case X86::VCMPSDrm_Int: case X86::VCMPSDrr_Int:
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case X86::VCMPSDZrm_Int: case X86::VCMPSDZrr_Int:
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case X86::VCMPSSrm: case X86::VCMPSSrr:
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case X86::VCMPSSZrm: case X86::VCMPSSZrr:
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case X86::VCMPSSrm_Int: case X86::VCMPSSrr_Int:
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case X86::VCMPSSZrm_Int: case X86::VCMPSSZrr_Int:
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case X86::VCMPPDZ128rmik: case X86::VCMPPDZ128rrik:
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case X86::VCMPPDZ256rmik: case X86::VCMPPDZ256rrik:
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case X86::VCMPPDZrmik: case X86::VCMPPDZrrik:
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case X86::VCMPPSZ128rmik: case X86::VCMPPSZ128rrik:
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case X86::VCMPPSZ256rmik: case X86::VCMPPSZ256rrik:
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case X86::VCMPPSZrmik: case X86::VCMPPSZrrik:
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case X86::VCMPSDZrm_Intk: case X86::VCMPSDZrr_Intk:
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case X86::VCMPSSZrm_Intk: case X86::VCMPSSZrr_Intk:
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case X86::VCMPPDZ128rmbi: case X86::VCMPPDZ128rmbik:
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case X86::VCMPPDZ256rmbi: case X86::VCMPPDZ256rmbik:
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case X86::VCMPPDZrmbi: case X86::VCMPPDZrmbik:
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case X86::VCMPPSZ128rmbi: case X86::VCMPPSZ128rmbik:
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case X86::VCMPPSZ256rmbi: case X86::VCMPPSZ256rmbik:
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case X86::VCMPPSZrmbi: case X86::VCMPPSZrmbik:
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case X86::VCMPPDZrrib: case X86::VCMPPDZrribk:
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case X86::VCMPPSZrrib: case X86::VCMPPSZrribk:
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case X86::VCMPSDZrrb_Int: case X86::VCMPSDZrrb_Intk:
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case X86::VCMPSSZrrb_Int: case X86::VCMPSSZrrb_Intk:
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if (Imm >= 0 && Imm <= 31) {
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OS << '\t';
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printCMPMnemonic(MI, /*IsVCMP*/true, OS);
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unsigned CurOp = 0;
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printOperand(MI, CurOp++, OS);
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if (Desc.TSFlags & X86II::EVEX_K) {
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// Print mask operand.
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OS << " {";
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printOperand(MI, CurOp++, OS);
|
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OS << "}";
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}
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OS << ", ";
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printOperand(MI, CurOp++, OS);
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OS << ", ";
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if ((Desc.TSFlags & X86II::FormMask) == X86II::MRMSrcMem) {
|
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if (Desc.TSFlags & X86II::EVEX_B) {
|
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// Broadcast form.
|
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|
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// Load size is based on W-bit.
|
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if (Desc.TSFlags & X86II::VEX_W)
|
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printqwordmem(MI, CurOp++, OS);
|
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else
|
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printdwordmem(MI, CurOp++, OS);
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// Print the number of elements broadcasted.
|
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unsigned NumElts;
|
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if (Desc.TSFlags & X86II::EVEX_L2)
|
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NumElts = (Desc.TSFlags & X86II::VEX_W) ? 8 : 16;
|
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else if (Desc.TSFlags & X86II::VEX_L)
|
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NumElts = (Desc.TSFlags & X86II::VEX_W) ? 4 : 8;
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else
|
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NumElts = (Desc.TSFlags & X86II::VEX_W) ? 2 : 4;
|
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OS << "{1to" << NumElts << "}";
|
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|
} else {
|
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if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XS)
|
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printdwordmem(MI, CurOp++, OS);
|
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else if ((Desc.TSFlags & X86II::OpPrefixMask) == X86II::XD)
|
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printqwordmem(MI, CurOp++, OS);
|
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else if (Desc.TSFlags & X86II::EVEX_L2)
|
|
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printzmmwordmem(MI, CurOp++, OS);
|
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else if (Desc.TSFlags & X86II::VEX_L)
|
|
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|
|
printymmwordmem(MI, CurOp++, OS);
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else
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printxmmwordmem(MI, CurOp++, OS);
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}
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} else {
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printOperand(MI, CurOp++, OS);
|
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if (Desc.TSFlags & X86II::EVEX_B)
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OS << ", {sae}";
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return true;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
|
[X86] Remove the _alt forms of XOP VPCOM instructions. Use a combination of custom printing and custom parsing to achieve the same result and more
Previously we had a regular form of the instruction used when the immediate was 0-7. And _alt form that allowed the full 8 bit immediate. Codegen would always use the 0-7 form since the immediate was always checked to be in range. Assembly parsing would use the 0-7 form when a mnemonic like vpcomtrueb was used. If the immediate was specified directly the _alt form was used. The disassembler would prefer to use the 0-7 form instruction when the immediate was in range and the _alt form otherwise. This way disassembly would print the most readable form when possible.
The assembly parsing for things like vpcomtrueb relied on splitting the mnemonic into 3 pieces. A "vpcom" prefix, an immediate representing the "true", and a suffix of "b". The tablegenerated printing code would similarly print a "vpcom" prefix, decode the immediate into a string, and then print "b".
The _alt form on the other hand parsed and printed like any other instruction with no specialness.
With this patch we drop to one form and solve the disassembly printing issue by doing custom printing when the immediate is 0-7. The parsing code has been tweaked to turn "vpcomtrueb" into "vpcomb" and then the immediate for the "true" is inserted either before or after the other operands depending on at&t or intel syntax.
I'd rather not do the custom printing, but I tried using an InstAlias for each possible mnemonic for all 8 immediates for all 16 combinations of element size, signedness, and memory/register. The code emitted into printAliasInstr ended up checking the number of operands, the register class of each operand, and the immediate for all 256 aliases. This was repeated for both the at&t and intel printer. Despite a lot of common checks between all of the aliases, when compiled with clang at least this commonality was not well optimized. Nor do all the checks seem necessary. Since I want to do a similar thing for vcmpps/pd/ss/sd which have 32 immediate values and 3 encoding flavors, 3 register sizes, etc. This didn't seem to scale well for clang binary size. So custom printing seemed a better trade off.
I also considered just using the InstAlias for the matching and not the printing. But that seemed like it would add a lot of extra rows to the matcher table. Especially given that the 32 immediates for vpcmpps have 46 strings associated with them.
Differential Revision: https://reviews.llvm.org/D59398
llvm-svn: 356343
2019-03-18 05:21:37 +08:00
|
|
|
case X86::VPCOMBmi: case X86::VPCOMBri:
|
|
|
|
|
case X86::VPCOMDmi: case X86::VPCOMDri:
|
|
|
|
|
case X86::VPCOMQmi: case X86::VPCOMQri:
|
|
|
|
|
case X86::VPCOMUBmi: case X86::VPCOMUBri:
|
|
|
|
|
case X86::VPCOMUDmi: case X86::VPCOMUDri:
|
|
|
|
|
case X86::VPCOMUQmi: case X86::VPCOMUQri:
|
|
|
|
|
case X86::VPCOMUWmi: case X86::VPCOMUWri:
|
|
|
|
|
case X86::VPCOMWmi: case X86::VPCOMWri:
|
|
|
|
|
if (Imm >= 0 && Imm <= 7) {
|
2019-03-18 10:53:11 +08:00
|
|
|
OS << '\t';
|
[X86] Remove the _alt forms of XOP VPCOM instructions. Use a combination of custom printing and custom parsing to achieve the same result and more
Previously we had a regular form of the instruction used when the immediate was 0-7. And _alt form that allowed the full 8 bit immediate. Codegen would always use the 0-7 form since the immediate was always checked to be in range. Assembly parsing would use the 0-7 form when a mnemonic like vpcomtrueb was used. If the immediate was specified directly the _alt form was used. The disassembler would prefer to use the 0-7 form instruction when the immediate was in range and the _alt form otherwise. This way disassembly would print the most readable form when possible.
The assembly parsing for things like vpcomtrueb relied on splitting the mnemonic into 3 pieces. A "vpcom" prefix, an immediate representing the "true", and a suffix of "b". The tablegenerated printing code would similarly print a "vpcom" prefix, decode the immediate into a string, and then print "b".
The _alt form on the other hand parsed and printed like any other instruction with no specialness.
With this patch we drop to one form and solve the disassembly printing issue by doing custom printing when the immediate is 0-7. The parsing code has been tweaked to turn "vpcomtrueb" into "vpcomb" and then the immediate for the "true" is inserted either before or after the other operands depending on at&t or intel syntax.
I'd rather not do the custom printing, but I tried using an InstAlias for each possible mnemonic for all 8 immediates for all 16 combinations of element size, signedness, and memory/register. The code emitted into printAliasInstr ended up checking the number of operands, the register class of each operand, and the immediate for all 256 aliases. This was repeated for both the at&t and intel printer. Despite a lot of common checks between all of the aliases, when compiled with clang at least this commonality was not well optimized. Nor do all the checks seem necessary. Since I want to do a similar thing for vcmpps/pd/ss/sd which have 32 immediate values and 3 encoding flavors, 3 register sizes, etc. This didn't seem to scale well for clang binary size. So custom printing seemed a better trade off.
I also considered just using the InstAlias for the matching and not the printing. But that seemed like it would add a lot of extra rows to the matcher table. Especially given that the 32 immediates for vpcmpps have 46 strings associated with them.
Differential Revision: https://reviews.llvm.org/D59398
llvm-svn: 356343
2019-03-18 05:21:37 +08:00
|
|
|
printVPCOMMnemonic(MI, OS);
|
|
|
|
|
printOperand(MI, 0, OS);
|
|
|
|
|
OS << ", ";
|
|
|
|
|
printOperand(MI, 1, OS);
|
|
|
|
|
OS << ", ";
|
|
|
|
|
if ((Desc.TSFlags & X86II::FormMask) == X86II::MRMSrcMem)
|
2019-03-18 06:57:21 +08:00
|
|
|
printxmmwordmem(MI, 2, OS);
|
[X86] Remove the _alt forms of XOP VPCOM instructions. Use a combination of custom printing and custom parsing to achieve the same result and more
Previously we had a regular form of the instruction used when the immediate was 0-7. And _alt form that allowed the full 8 bit immediate. Codegen would always use the 0-7 form since the immediate was always checked to be in range. Assembly parsing would use the 0-7 form when a mnemonic like vpcomtrueb was used. If the immediate was specified directly the _alt form was used. The disassembler would prefer to use the 0-7 form instruction when the immediate was in range and the _alt form otherwise. This way disassembly would print the most readable form when possible.
The assembly parsing for things like vpcomtrueb relied on splitting the mnemonic into 3 pieces. A "vpcom" prefix, an immediate representing the "true", and a suffix of "b". The tablegenerated printing code would similarly print a "vpcom" prefix, decode the immediate into a string, and then print "b".
The _alt form on the other hand parsed and printed like any other instruction with no specialness.
With this patch we drop to one form and solve the disassembly printing issue by doing custom printing when the immediate is 0-7. The parsing code has been tweaked to turn "vpcomtrueb" into "vpcomb" and then the immediate for the "true" is inserted either before or after the other operands depending on at&t or intel syntax.
I'd rather not do the custom printing, but I tried using an InstAlias for each possible mnemonic for all 8 immediates for all 16 combinations of element size, signedness, and memory/register. The code emitted into printAliasInstr ended up checking the number of operands, the register class of each operand, and the immediate for all 256 aliases. This was repeated for both the at&t and intel printer. Despite a lot of common checks between all of the aliases, when compiled with clang at least this commonality was not well optimized. Nor do all the checks seem necessary. Since I want to do a similar thing for vcmpps/pd/ss/sd which have 32 immediate values and 3 encoding flavors, 3 register sizes, etc. This didn't seem to scale well for clang binary size. So custom printing seemed a better trade off.
I also considered just using the InstAlias for the matching and not the printing. But that seemed like it would add a lot of extra rows to the matcher table. Especially given that the 32 immediates for vpcmpps have 46 strings associated with them.
Differential Revision: https://reviews.llvm.org/D59398
llvm-svn: 356343
2019-03-18 05:21:37 +08:00
|
|
|
else
|
|
|
|
|
printOperand(MI, 2, OS);
|
|
|
|
|
return true;
|
|
|
|
|
}
|
|
|
|
|
break;
|
2019-03-18 05:21:40 +08:00
|
|
|
|
|
|
|
|
case X86::VPCMPBZ128rmi: case X86::VPCMPBZ128rri:
|
|
|
|
|
case X86::VPCMPBZ256rmi: case X86::VPCMPBZ256rri:
|
|
|
|
|
case X86::VPCMPBZrmi: case X86::VPCMPBZrri:
|
|
|
|
|
case X86::VPCMPDZ128rmi: case X86::VPCMPDZ128rri:
|
|
|
|
|
case X86::VPCMPDZ256rmi: case X86::VPCMPDZ256rri:
|
|
|
|
|
case X86::VPCMPDZrmi: case X86::VPCMPDZrri:
|
|
|
|
|
case X86::VPCMPQZ128rmi: case X86::VPCMPQZ128rri:
|
|
|
|
|
case X86::VPCMPQZ256rmi: case X86::VPCMPQZ256rri:
|
|
|
|
|
case X86::VPCMPQZrmi: case X86::VPCMPQZrri:
|
|
|
|
|
case X86::VPCMPUBZ128rmi: case X86::VPCMPUBZ128rri:
|
|
|
|
|
case X86::VPCMPUBZ256rmi: case X86::VPCMPUBZ256rri:
|
|
|
|
|
case X86::VPCMPUBZrmi: case X86::VPCMPUBZrri:
|
|
|
|
|
case X86::VPCMPUDZ128rmi: case X86::VPCMPUDZ128rri:
|
|
|
|
|
case X86::VPCMPUDZ256rmi: case X86::VPCMPUDZ256rri:
|
|
|
|
|
case X86::VPCMPUDZrmi: case X86::VPCMPUDZrri:
|
|
|
|
|
case X86::VPCMPUQZ128rmi: case X86::VPCMPUQZ128rri:
|
|
|
|
|
case X86::VPCMPUQZ256rmi: case X86::VPCMPUQZ256rri:
|
|
|
|
|
case X86::VPCMPUQZrmi: case X86::VPCMPUQZrri:
|
|
|
|
|
case X86::VPCMPUWZ128rmi: case X86::VPCMPUWZ128rri:
|
|
|
|
|
case X86::VPCMPUWZ256rmi: case X86::VPCMPUWZ256rri:
|
|
|
|
|
case X86::VPCMPUWZrmi: case X86::VPCMPUWZrri:
|
|
|
|
|
case X86::VPCMPWZ128rmi: case X86::VPCMPWZ128rri:
|
|
|
|
|
case X86::VPCMPWZ256rmi: case X86::VPCMPWZ256rri:
|
|
|
|
|
case X86::VPCMPWZrmi: case X86::VPCMPWZrri:
|
|
|
|
|
case X86::VPCMPBZ128rmik: case X86::VPCMPBZ128rrik:
|
|
|
|
|
case X86::VPCMPBZ256rmik: case X86::VPCMPBZ256rrik:
|
|
|
|
|
case X86::VPCMPBZrmik: case X86::VPCMPBZrrik:
|
|
|
|
|
case X86::VPCMPDZ128rmik: case X86::VPCMPDZ128rrik:
|
|
|
|
|
case X86::VPCMPDZ256rmik: case X86::VPCMPDZ256rrik:
|
|
|
|
|
case X86::VPCMPDZrmik: case X86::VPCMPDZrrik:
|
|
|
|
|
case X86::VPCMPQZ128rmik: case X86::VPCMPQZ128rrik:
|
|
|
|
|
case X86::VPCMPQZ256rmik: case X86::VPCMPQZ256rrik:
|
|
|
|
|
case X86::VPCMPQZrmik: case X86::VPCMPQZrrik:
|
|
|
|
|
case X86::VPCMPUBZ128rmik: case X86::VPCMPUBZ128rrik:
|
|
|
|
|
case X86::VPCMPUBZ256rmik: case X86::VPCMPUBZ256rrik:
|
|
|
|
|
case X86::VPCMPUBZrmik: case X86::VPCMPUBZrrik:
|
|
|
|
|
case X86::VPCMPUDZ128rmik: case X86::VPCMPUDZ128rrik:
|
|
|
|
|
case X86::VPCMPUDZ256rmik: case X86::VPCMPUDZ256rrik:
|
|
|
|
|
case X86::VPCMPUDZrmik: case X86::VPCMPUDZrrik:
|
|
|
|
|
case X86::VPCMPUQZ128rmik: case X86::VPCMPUQZ128rrik:
|
|
|
|
|
case X86::VPCMPUQZ256rmik: case X86::VPCMPUQZ256rrik:
|
|
|
|
|
case X86::VPCMPUQZrmik: case X86::VPCMPUQZrrik:
|
|
|
|
|
case X86::VPCMPUWZ128rmik: case X86::VPCMPUWZ128rrik:
|
|
|
|
|
case X86::VPCMPUWZ256rmik: case X86::VPCMPUWZ256rrik:
|
|
|
|
|
case X86::VPCMPUWZrmik: case X86::VPCMPUWZrrik:
|
|
|
|
|
case X86::VPCMPWZ128rmik: case X86::VPCMPWZ128rrik:
|
|
|
|
|
case X86::VPCMPWZ256rmik: case X86::VPCMPWZ256rrik:
|
|
|
|
|
case X86::VPCMPWZrmik: case X86::VPCMPWZrrik:
|
|
|
|
|
case X86::VPCMPDZ128rmib: case X86::VPCMPDZ128rmibk:
|
|
|
|
|
case X86::VPCMPDZ256rmib: case X86::VPCMPDZ256rmibk:
|
|
|
|
|
case X86::VPCMPDZrmib: case X86::VPCMPDZrmibk:
|
|
|
|
|
case X86::VPCMPQZ128rmib: case X86::VPCMPQZ128rmibk:
|
|
|
|
|
case X86::VPCMPQZ256rmib: case X86::VPCMPQZ256rmibk:
|
|
|
|
|
case X86::VPCMPQZrmib: case X86::VPCMPQZrmibk:
|
|
|
|
|
case X86::VPCMPUDZ128rmib: case X86::VPCMPUDZ128rmibk:
|
|
|
|
|
case X86::VPCMPUDZ256rmib: case X86::VPCMPUDZ256rmibk:
|
|
|
|
|
case X86::VPCMPUDZrmib: case X86::VPCMPUDZrmibk:
|
|
|
|
|
case X86::VPCMPUQZ128rmib: case X86::VPCMPUQZ128rmibk:
|
|
|
|
|
case X86::VPCMPUQZ256rmib: case X86::VPCMPUQZ256rmibk:
|
|
|
|
|
case X86::VPCMPUQZrmib: case X86::VPCMPUQZrmibk:
|
|
|
|
|
if ((Imm >= 0 && Imm <= 2) || (Imm >= 4 && Imm <= 6)) {
|
2019-03-18 10:53:11 +08:00
|
|
|
OS << '\t';
|
2019-03-18 05:21:40 +08:00
|
|
|
printVPCMPMnemonic(MI, OS);
|
|
|
|
|
|
|
|
|
|
unsigned CurOp = 0;
|
|
|
|
|
printOperand(MI, CurOp++, OS);
|
|
|
|
|
|
|
|
|
|
if (Desc.TSFlags & X86II::EVEX_K) {
|
|
|
|
|
// Print mask operand.
|
|
|
|
|
OS << " {";
|
|
|
|
|
printOperand(MI, CurOp++, OS);
|
|
|
|
|
OS << "}";
|
|
|
|
|
}
|
|
|
|
|
OS << ", ";
|
|
|
|
|
printOperand(MI, CurOp++, OS);
|
|
|
|
|
OS << ", ";
|
|
|
|
|
|
|
|
|
|
if ((Desc.TSFlags & X86II::FormMask) == X86II::MRMSrcMem) {
|
|
|
|
|
if (Desc.TSFlags & X86II::EVEX_B) {
|
|
|
|
|
// Broadcast form.
|
|
|
|
|
// Load size is based on W-bit as only D and Q are supported.
|
|
|
|
|
if (Desc.TSFlags & X86II::VEX_W)
|
2019-03-18 06:57:21 +08:00
|
|
|
printqwordmem(MI, CurOp++, OS);
|
2019-03-18 05:21:40 +08:00
|
|
|
else
|
2019-03-18 06:57:21 +08:00
|
|
|
printdwordmem(MI, CurOp++, OS);
|
2019-03-18 05:21:40 +08:00
|
|
|
|
|
|
|
|
// Print the number of elements broadcasted.
|
|
|
|
|
unsigned NumElts;
|
|
|
|
|
if (Desc.TSFlags & X86II::EVEX_L2)
|
|
|
|
|
NumElts = (Desc.TSFlags & X86II::VEX_W) ? 8 : 16;
|
|
|
|
|
else if (Desc.TSFlags & X86II::VEX_L)
|
|
|
|
|
NumElts = (Desc.TSFlags & X86II::VEX_W) ? 4 : 8;
|
|
|
|
|
else
|
|
|
|
|
NumElts = (Desc.TSFlags & X86II::VEX_W) ? 2 : 4;
|
|
|
|
|
OS << "{1to" << NumElts << "}";
|
|
|
|
|
} else {
|
|
|
|
|
if (Desc.TSFlags & X86II::EVEX_L2)
|
2019-03-18 06:57:21 +08:00
|
|
|
printzmmwordmem(MI, CurOp++, OS);
|
2019-03-18 05:21:40 +08:00
|
|
|
else if (Desc.TSFlags & X86II::VEX_L)
|
2019-03-18 06:57:21 +08:00
|
|
|
printymmwordmem(MI, CurOp++, OS);
|
2019-03-18 05:21:40 +08:00
|
|
|
else
|
2019-03-18 06:57:21 +08:00
|
|
|
printxmmwordmem(MI, CurOp++, OS);
|
2019-03-18 05:21:40 +08:00
|
|
|
}
|
|
|
|
|
} else {
|
|
|
|
|
printOperand(MI, CurOp++, OS);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return true;
|
|
|
|
|
}
|
|
|
|
|
break;
|
[X86] Remove the _alt forms of XOP VPCOM instructions. Use a combination of custom printing and custom parsing to achieve the same result and more
Previously we had a regular form of the instruction used when the immediate was 0-7. And _alt form that allowed the full 8 bit immediate. Codegen would always use the 0-7 form since the immediate was always checked to be in range. Assembly parsing would use the 0-7 form when a mnemonic like vpcomtrueb was used. If the immediate was specified directly the _alt form was used. The disassembler would prefer to use the 0-7 form instruction when the immediate was in range and the _alt form otherwise. This way disassembly would print the most readable form when possible.
The assembly parsing for things like vpcomtrueb relied on splitting the mnemonic into 3 pieces. A "vpcom" prefix, an immediate representing the "true", and a suffix of "b". The tablegenerated printing code would similarly print a "vpcom" prefix, decode the immediate into a string, and then print "b".
The _alt form on the other hand parsed and printed like any other instruction with no specialness.
With this patch we drop to one form and solve the disassembly printing issue by doing custom printing when the immediate is 0-7. The parsing code has been tweaked to turn "vpcomtrueb" into "vpcomb" and then the immediate for the "true" is inserted either before or after the other operands depending on at&t or intel syntax.
I'd rather not do the custom printing, but I tried using an InstAlias for each possible mnemonic for all 8 immediates for all 16 combinations of element size, signedness, and memory/register. The code emitted into printAliasInstr ended up checking the number of operands, the register class of each operand, and the immediate for all 256 aliases. This was repeated for both the at&t and intel printer. Despite a lot of common checks between all of the aliases, when compiled with clang at least this commonality was not well optimized. Nor do all the checks seem necessary. Since I want to do a similar thing for vcmpps/pd/ss/sd which have 32 immediate values and 3 encoding flavors, 3 register sizes, etc. This didn't seem to scale well for clang binary size. So custom printing seemed a better trade off.
I also considered just using the InstAlias for the matching and not the printing. But that seemed like it would add a lot of extra rows to the matcher table. Especially given that the 32 immediates for vpcmpps have 46 strings associated with them.
Differential Revision: https://reviews.llvm.org/D59398
llvm-svn: 356343
2019-03-18 05:21:37 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
|
2009-09-20 15:17:49 +08:00
|
|
|
void X86IntelInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
|
2010-04-04 12:47:45 +08:00
|
|
|
raw_ostream &O) {
|
2009-09-20 15:17:49 +08:00
|
|
|
const MCOperand &Op = MI->getOperand(OpNo);
|
|
|
|
|
if (Op.isReg()) {
|
2013-07-31 10:47:52 +08:00
|
|
|
printRegName(O, Op.getReg());
|
2009-09-20 15:17:49 +08:00
|
|
|
} else if (Op.isImm()) {
|
2013-08-02 05:18:16 +08:00
|
|
|
O << formatImm((int64_t)Op.getImm());
|
2009-09-20 15:17:49 +08:00
|
|
|
} else {
|
|
|
|
|
assert(Op.isExpr() && "unknown operand kind in printOperand");
|
2017-09-26 03:26:48 +08:00
|
|
|
O << "offset ";
|
2015-06-09 08:31:39 +08:00
|
|
|
Op.getExpr()->print(O, &MAI);
|
2009-09-20 15:17:49 +08:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2010-07-09 07:46:44 +08:00
|
|
|
void X86IntelInstPrinter::printMemReference(const MCInst *MI, unsigned Op,
|
|
|
|
|
raw_ostream &O) {
|
[llvm-objdump] Symbolize binary addresses for low-noisy asm diff.
When diffing disassembly dump of two binaries, I see lots of noises from mismatched jump target addresses and global data references, which unnecessarily causes diffs on every function, making it impractical. I'm trying to symbolize the raw binary addresses to minimize the diff noise.
In this change, a local branch target is modeled as a label and the branch target operand will simply be printed as a label. Local labels are collected by a separate pre-decoding pass beforehand. A global data memory operand will be printed as a global symbol instead of the raw data address. Unfortunately, due to the way the disassembler is set up and to be less intrusive, a global symbol is always printed as the last operand of a memory access instruction. This is less than ideal but is probably acceptable from checking code quality point of view since on most targets an instruction can have at most one memory operand.
So far only the X86 disassemblers are supported.
Test Plan:
llvm-objdump -d --x86-asm-syntax=intel --no-show-raw-insn --no-leading-addr :
```
Disassembly of section .text:
<_start>:
push rax
mov dword ptr [rsp + 4], 0
mov dword ptr [rsp], 0
mov eax, dword ptr [rsp]
cmp eax, dword ptr [rip + 4112] # 202182 <g>
jge 0x20117e <_start+0x25>
call 0x201158 <foo>
inc dword ptr [rsp]
jmp 0x201169 <_start+0x10>
xor eax, eax
pop rcx
ret
```
llvm-objdump -d **--symbolize-operands** --x86-asm-syntax=intel --no-show-raw-insn --no-leading-addr :
```
Disassembly of section .text:
<_start>:
push rax
mov dword ptr [rsp + 4], 0
mov dword ptr [rsp], 0
<L1>:
mov eax, dword ptr [rsp]
cmp eax, dword ptr <g>
jge <L0>
call <foo>
inc dword ptr [rsp]
jmp <L1>
<L0>:
xor eax, eax
pop rcx
ret
```
Note that the jump instructions like `jge 0x20117e <_start+0x25>` without this work is printed as a real target address and an offset from the leading symbol. With a change in the optimizer that adds/deletes an instruction, the address and offset may shift for targets placed after the instruction. This will be a problem when diffing the disassembly from two optimizers where there are unnecessary false positives due to such branch target address changes. With `--symbolize-operand`, a label is printed for a branch target instead to reduce the false positives. Similarly, the disassemble of PC-relative global variable references is also prone to instruction insertion/deletion.
Reviewed By: jhenderson, MaskRay
Differential Revision: https://reviews.llvm.org/D84191
2020-07-21 00:45:32 +08:00
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// Do not print the exact form of the memory operand if it references a known
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// binary object.
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if (SymbolizeOperands && MIA) {
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uint64_t Target;
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if (MIA->evaluateBranch(*MI, 0, 0, Target))
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return;
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if (MIA->evaluateMemoryOperandAddress(*MI, 0, 0))
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return;
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}
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2014-03-19 00:14:11 +08:00
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const MCOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg);
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unsigned ScaleVal = MI->getOperand(Op+X86::AddrScaleAmt).getImm();
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const MCOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg);
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const MCOperand &DispSpec = MI->getOperand(Op+X86::AddrDisp);
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2014-12-04 13:20:33 +08:00
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2010-07-09 07:46:44 +08:00
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// If this has a segment register, print it.
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2018-06-05 18:41:39 +08:00
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printOptionalSegReg(MI, Op + X86::AddrSegmentReg, O);
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2014-12-04 13:20:33 +08:00
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2009-09-20 15:17:49 +08:00
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O << '[';
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2014-12-04 13:20:33 +08:00
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2009-09-20 15:17:49 +08:00
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bool NeedPlus = false;
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if (BaseReg.getReg()) {
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2014-03-19 00:14:11 +08:00
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printOperand(MI, Op+X86::AddrBaseReg, O);
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2009-09-20 15:17:49 +08:00
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NeedPlus = true;
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}
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2014-12-04 13:20:33 +08:00
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2009-09-20 15:17:49 +08:00
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if (IndexReg.getReg()) {
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if (NeedPlus) O << " + ";
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if (ScaleVal != 1)
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O << ScaleVal << '*';
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2014-03-19 00:14:11 +08:00
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printOperand(MI, Op+X86::AddrIndexReg, O);
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2009-09-20 15:17:49 +08:00
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NeedPlus = true;
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}
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2012-10-04 03:00:20 +08:00
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2009-09-20 15:17:49 +08:00
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if (!DispSpec.isImm()) {
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if (NeedPlus) O << " + ";
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assert(DispSpec.isExpr() && "non-immediate displacement for LEA?");
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2015-06-09 08:31:39 +08:00
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DispSpec.getExpr()->print(O, &MAI);
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2009-09-20 15:17:49 +08:00
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} else {
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int64_t DispVal = DispSpec.getImm();
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if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) {
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if (NeedPlus) {
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if (DispVal > 0)
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O << " + ";
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else {
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O << " - ";
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DispVal = -DispVal;
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}
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}
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2013-08-02 05:18:16 +08:00
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O << formatImm(DispVal);
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2009-09-20 15:17:49 +08:00
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}
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}
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2014-12-04 13:20:33 +08:00
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2009-09-20 15:17:49 +08:00
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O << ']';
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}
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2013-08-26 06:23:38 +08:00
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2014-01-22 23:08:08 +08:00
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void X86IntelInstPrinter::printSrcIdx(const MCInst *MI, unsigned Op,
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raw_ostream &O) {
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// If this has a segment register, print it.
|
2018-06-05 18:41:39 +08:00
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printOptionalSegReg(MI, Op + 1, O);
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2014-01-22 23:08:08 +08:00
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O << '[';
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printOperand(MI, Op, O);
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O << ']';
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}
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2014-01-22 23:08:21 +08:00
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void X86IntelInstPrinter::printDstIdx(const MCInst *MI, unsigned Op,
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raw_ostream &O) {
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// DI accesses are always ES-based.
|
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O << "es:[";
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printOperand(MI, Op, O);
|
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O << ']';
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}
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2013-08-26 06:23:38 +08:00
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void X86IntelInstPrinter::printMemOffset(const MCInst *MI, unsigned Op,
|
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|
raw_ostream &O) {
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const MCOperand &DispSpec = MI->getOperand(Op);
|
2014-01-16 15:36:58 +08:00
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|
// If this has a segment register, print it.
|
2018-06-05 18:41:39 +08:00
|
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printOptionalSegReg(MI, Op + 1, O);
|
2013-08-26 06:23:38 +08:00
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O << '[';
|
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if (DispSpec.isImm()) {
|
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|
O << formatImm(DispSpec.getImm());
|
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|
} else {
|
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|
assert(DispSpec.isExpr() && "non-immediate displacement?");
|
2015-06-09 08:31:39 +08:00
|
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|
DispSpec.getExpr()->print(O, &MAI);
|
2013-08-26 06:23:38 +08:00
|
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|
}
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O << ']';
|
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|
}
|
2015-01-23 16:00:59 +08:00
|
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|
void X86IntelInstPrinter::printU8Imm(const MCInst *MI, unsigned Op,
|
|
|
|
|
raw_ostream &O) {
|
2016-10-20 09:58:34 +08:00
|
|
|
if (MI->getOperand(Op).isExpr())
|
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|
|
|
return MI->getOperand(Op).getExpr()->print(O, &MAI);
|
|
|
|
|
|
2015-01-23 16:00:59 +08:00
|
|
|
O << formatImm(MI->getOperand(Op).getImm() & 0xff);
|
|
|
|
|
}
|
2019-02-04 12:15:10 +08:00
|
|
|
|
|
|
|
|
void X86IntelInstPrinter::printSTiRegOperand(const MCInst *MI, unsigned OpNo,
|
|
|
|
|
raw_ostream &OS) {
|
|
|
|
|
const MCOperand &Op = MI->getOperand(OpNo);
|
|
|
|
|
unsigned Reg = Op.getReg();
|
|
|
|
|
// Override the default printing to print st(0) instead st.
|
|
|
|
|
if (Reg == X86::ST0)
|
|
|
|
|
OS << "st(0)";
|
|
|
|
|
else
|
|
|
|
|
printRegName(OS, Reg);
|
|
|
|
|
}
|