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llvm-project/llvm/test/CodeGen/ARM/smml.ll

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In Thumb1, materialize a move between low registers as a `movs`, if CPSR isn't live. Summary: Previously, it had always been materialized as a push/pop sequence. Reviewers: labrinea, jroelofs Reviewed By: jroelofs Subscribers: llvm-commits, rengolin Differential Revision: https://reviews.llvm.org/D30648 llvm-svn: 297134
2017-03-07 17:38:16 +08:00
; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-V4
; RUN: llc -mtriple=armv6-eabi %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-V6
; RUN: llc -mtriple=armv7-eabi %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-V6
; RUN: llc -mtriple=thumb-eabi %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-THUMB
[ARM] Enable SETCCCARRY lowering for Thumb1. We've had Thumb1 support for ARMISD::SUBE for a while now, so this just works. Reduces codesize a bit for 64-bit integer comparisons. Differential Revision: https://reviews.llvm.org/D47387 llvm-svn: 333445
2018-05-30 02:17:16 +08:00
; RUN: llc -mtriple=thumbv6-eabi %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-THUMB
In Thumb1, materialize a move between low registers as a `movs`, if CPSR isn't live. Summary: Previously, it had always been materialized as a push/pop sequence. Reviewers: labrinea, jroelofs Reviewed By: jroelofs Subscribers: llvm-commits, rengolin Differential Revision: https://reviews.llvm.org/D30648 llvm-svn: 297134
2017-03-07 17:38:16 +08:00
; RUN: llc -mtriple=thumbv6t2-eabi %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-THUMBV6T2
; RUN: llc -mtriple=thumbv7-eabi %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-THUMBV6T2
[ARM] Fix erroneous availability of SMMLS for Armv7-M Differential Revision: https://reviews.llvm.org/D41855 llvm-svn: 322360
2018-01-12 17:21:09 +08:00
; RUN: llc -mtriple=thumbv7m-eabi %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-V4
[ARM][NFC] codegen tests cleanup: remove dangling check prefixes I am working on making FileCheck stricter (in D54769 and D53710) so that it issues diagnostics when there's something wrong with tests. This is a cleanup for dangling prefixes in the ARM codegen tests, e.g.: --check-prefixes=A,B where A occurs in the check file, but B doesn't. This can be innocent if A does all the required checking, but can also be a bug in that test if it results in the test actually not checking anything (if A for example only checks a common label). Test CodeGen/ARM/smml.ll is such an example. Differential Revision: https://reviews.llvm.org/D54842 llvm-svn: 347487
2018-11-23 18:08:39 +08:00
; RUN: llc -mtriple=thumbv7em-eabi %s -o - | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-THUMBV6T2
ARM: update even more tests More updating of tests to be explicit about the target triple rather than relying on the default target triple supporting ARM mode. Indicate to lit that object emission is not yet available for Windows on ARM. llvm-svn: 205545
2014-04-04 01:35:22 +08:00
[DebugInfo][If-Converter] Update call site info during the optimization During the If-Converter optimization pay attention when copying or deleting call instructions in order to keep call site information in valid state. Reviewers: aprantl, vsk, efriedma Reviewed By: vsk, efriedma Differential Revision: https://reviews.llvm.org/D66955 llvm-svn: 374068
2019-10-08 23:43:12 +08:00
; Next test would previously trigger an assertion responsible for verification of
; call site info state.
Revert "Reland "[DebugInfo] Enable the debug entry values feature by default"" This reverts commit rGa82d3e8a6e67.
2020-02-18 23:37:16 +08:00
; RUN: llc -stop-after=if-converter -debug-entry-values -mtriple=thumbv6t2-eabi %s -o -| FileCheck %s -check-prefix=CHECK-CALLSITE
[DebugInfo][If-Converter] Update call site info during the optimization During the If-Converter optimization pay attention when copying or deleting call instructions in order to keep call site information in valid state. Reviewers: aprantl, vsk, efriedma Reviewed By: vsk, efriedma Differential Revision: https://reviews.llvm.org/D66955 llvm-svn: 374068
2019-10-08 23:43:12 +08:00
; CHECK-CALLSITE: name: test_used_flags
; CHECK-CALLSITE: callSites:
[ARM] Enable ISel of SMMLS for ARM and Thumb2 Use ISelDAGToDAG to recognise the SMMLS instruction pattern. Differential Revision: https://reviews.llvm.org/D22562 llvm-svn: 276624
2016-07-25 17:20:20 +08:00
define i32 @Test0(i32 %a, i32 %b, i32 %c) nounwind readnone ssp {
Remove incorrect pattern for ARM SMML instruction. Patch by Meador Inge. llvm-svn: 156989
2012-05-17 21:12:13 +08:00
entry:
[ARM] Enable ISel of SMMLS for ARM and Thumb2 Use ISelDAGToDAG to recognise the SMMLS instruction pattern. Differential Revision: https://reviews.llvm.org/D22562 llvm-svn: 276624
2016-07-25 17:20:20 +08:00
; CHECK-LABEL: Test0
Remove incorrect pattern for ARM SMML instruction. Patch by Meador Inge. llvm-svn: 156989
2012-05-17 21:12:13 +08:00
; CHECK-NOT: smmls
%conv4 = zext i32 %a to i64
%conv1 = sext i32 %b to i64
%conv2 = sext i32 %c to i64
%mul = mul nsw i64 %conv2, %conv1
%shr5 = lshr i64 %mul, 32
%sub = sub nsw i64 %conv4, %shr5
%conv3 = trunc i64 %sub to i32
ret i32 %conv3
}
[ARM] Enable ISel of SMMLS for ARM and Thumb2 Use ISelDAGToDAG to recognise the SMMLS instruction pattern. Differential Revision: https://reviews.llvm.org/D22562 llvm-svn: 276624
2016-07-25 17:20:20 +08:00
define i32 @Test1(i32 %a, i32 %b, i32 %c) {
;CHECK-LABEL: Test1
In Thumb1, materialize a move between low registers as a `movs`, if CPSR isn't live. Summary: Previously, it had always been materialized as a push/pop sequence. Reviewers: labrinea, jroelofs Reviewed By: jroelofs Subscribers: llvm-commits, rengolin Differential Revision: https://reviews.llvm.org/D30648 llvm-svn: 297134
2017-03-07 17:38:16 +08:00
;CHECK-V4-NOT: smmls
[ARM] Enable ISel of SMMLS for ARM and Thumb2 Use ISelDAGToDAG to recognise the SMMLS instruction pattern. Differential Revision: https://reviews.llvm.org/D22562 llvm-svn: 276624
2016-07-25 17:20:20 +08:00
;CHECK-THUMB-NOT: smmls
;CHECK-V6: smmls r0, [[Rn:r[1-2]]], [[Rm:r[1-2]]], r0
;CHECK-THUMBV6T2: smmls r0, [[Rn:r[1-2]]], [[Rm:r[1-2]]], r0
entry:
%conv = sext i32 %b to i64
%conv1 = sext i32 %c to i64
%mul = mul nsw i64 %conv1, %conv
%conv26 = zext i32 %a to i64
%shl = shl nuw i64 %conv26, 32
%sub = sub nsw i64 %shl, %mul
%shr7 = lshr i64 %sub, 32
%conv3 = trunc i64 %shr7 to i32
ret i32 %conv3
}
ARM: only form SMMLS when SUBE flags unused. In this particular example we wouldn't want the smmls anyway (the value is actually unused), but in general smmls does not provide the required flags register so if that SUBE result is used we can't replace it. llvm-svn: 277541
2016-08-03 07:12:36 +08:00
declare void @opaque(i32)
define void @test_used_flags(i32 %in1, i32 %in2) {
In Thumb1, materialize a move between low registers as a `movs`, if CPSR isn't live. Summary: Previously, it had always been materialized as a push/pop sequence. Reviewers: labrinea, jroelofs Reviewed By: jroelofs Subscribers: llvm-commits, rengolin Differential Revision: https://reviews.llvm.org/D30648 llvm-svn: 297134
2017-03-07 17:38:16 +08:00
; CHECK-LABEL: test_used_flags:
[ARM] Enable SETCCCARRY lowering for Thumb1. We've had Thumb1 support for ARMISD::SUBE for a while now, so this just works. Reduces codesize a bit for 64-bit integer comparisons. Differential Revision: https://reviews.llvm.org/D47387 llvm-svn: 333445
2018-05-30 02:17:16 +08:00
; CHECK-THUMB: movs r2, #0
[ARM] Add missing pseudo-instruction for Thumb1 RSBS. Shows up rarely for 64-bit arithmetic, more frequently for the compare patterns added in r325323. Differential Revision: https://reviews.llvm.org/D53848 llvm-svn: 345782
2018-11-01 05:45:48 +08:00
; CHECK-THUMB: rsbs r0, r0, #0
[ARM] Enable SETCCCARRY lowering for Thumb1. We've had Thumb1 support for ARMISD::SUBE for a while now, so this just works. Reduces codesize a bit for 64-bit integer comparisons. Differential Revision: https://reviews.llvm.org/D47387 llvm-svn: 333445
2018-05-30 02:17:16 +08:00
; CHECK-THUMB: sbcs r2, r1
; CHECK-THUMB: bge
In Thumb1, materialize a move between low registers as a `movs`, if CPSR isn't live. Summary: Previously, it had always been materialized as a push/pop sequence. Reviewers: labrinea, jroelofs Reviewed By: jroelofs Subscribers: llvm-commits, rengolin Differential Revision: https://reviews.llvm.org/D30648 llvm-svn: 297134
2017-03-07 17:38:16 +08:00
; CHECK-V6: smull [[PROD_LO:r[0-9]+]], [[PROD_HI:r[0-9]+]], r0, r1
; CHECK-V6: rsbs {{.*}}, [[PROD_LO]], #0
; CHECK-V6: rscs {{.*}}, [[PROD_HI]], #0
; CHECK-THUMBV6T2: smull [[PROD_LO:r[0-9]+]], [[PROD_HI:r[0-9]+]], r0, r1
; CHECK-THUMBV6T2: movs [[ZERO:r[0-9]+]], #0
; CHECK-THUMBV6T2: rsbs {{.*}}, [[PROD_LO]], #0
; CHECK-THUMBV6T2: sbcs.w {{.*}}, [[ZERO]], [[PROD_HI]]
ARM: only form SMMLS when SUBE flags unused. In this particular example we wouldn't want the smmls anyway (the value is actually unused), but in general smmls does not provide the required flags register so if that SUBE result is used we can't replace it. llvm-svn: 277541
2016-08-03 07:12:36 +08:00
%in1.64 = sext i32 %in1 to i64
%in2.64 = sext i32 %in2 to i64
%mul = mul nsw i64 %in1.64, %in2.64
%tst = icmp slt i64 %mul, 1
br i1 %tst, label %true, label %false
true:
call void @opaque(i32 42)
ret void
false:
call void @opaque(i32 56)
ret void
}