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llvm-project/llvm/test/CodeGen/X86/vec_insert-mmx.ll

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[X86][SSE] Regenerated the vec_insert tests. llvm-svn: 265179
2016-04-02 03:42:23 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-darwin -mattr=+mmx,+sse2 | FileCheck %s --check-prefix=X32
; RUN: llc < %s -mtriple=x86_64-darwin -mattr=+mmx,+sse4.1 | FileCheck %s --check-prefix=X64
[X86][MMX] Cleanup shuffle, bitcast and insert element tests - Merge MMX arg passing test files - Merge MMX bitcast, insert elt and shuffle tests llvm-svn: 227867
2015-02-03 05:56:11 +08:00
; This is not an MMX operation; promoted to XMM.
define x86_mmx @t0(i32 %A) nounwind {
[X86][SSE] Regenerated the vec_insert tests. llvm-svn: 265179
2016-04-02 03:42:23 +08:00
; X32-LABEL: t0:
; X32: ## BB#0:
; X32-NEXT: subl $12, %esp
; X32-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X32-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,0,1,1]
; X32-NEXT: movq %xmm0, (%esp)
; X32-NEXT: movq (%esp), %mm0
; X32-NEXT: addl $12, %esp
; X32-NEXT: retl
;
; X64-LABEL: t0:
; X64: ## BB#0:
VirtRegMap: Replace some identity copies with KILL instructions. An identity COPY like this: %AL = COPY %AL, %EAX<imp-def> has no semantic effect, but encodes liveness information: Further users of %EAX only depend on this instruction even though it does not define the full register. Replace the COPY with a KILL instruction in those cases to maintain this liveness information. (This reverts a small part of r238588 but this time adds a comment explaining why a KILL instruction is useful). llvm-svn: 274952
2016-07-09 08:19:07 +08:00
; X64-NEXT: ## kill: %EDI<def> %EDI<kill> %RDI<def>
[X86][SSE] Regenerated the vec_insert tests. llvm-svn: 265179
2016-04-02 03:42:23 +08:00
; X64-NEXT: movd %rdi, %xmm0
; X64-NEXT: pslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7]
; X64-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
; X64-NEXT: retq
[X86][MMX] Cleanup shuffle, bitcast and insert element tests - Merge MMX arg passing test files - Merge MMX bitcast, insert elt and shuffle tests llvm-svn: 227867
2015-02-03 05:56:11 +08:00
%tmp3 = insertelement <2 x i32> < i32 0, i32 undef >, i32 %A, i32 1
%tmp4 = bitcast <2 x i32> %tmp3 to x86_mmx
ret x86_mmx %tmp4
}
define <8 x i8> @t1(i8 zeroext %x) nounwind {
[X86][SSE] Regenerated the vec_insert tests. llvm-svn: 265179
2016-04-02 03:42:23 +08:00
; X32-LABEL: t1:
; X32: ## BB#0:
; X32-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
; X32-NEXT: retl
;
; X64-LABEL: t1:
; X64: ## BB#0:
; X64-NEXT: movd %edi, %xmm0
; X64-NEXT: retq
[X86][MMX] Cleanup shuffle, bitcast and insert element tests - Merge MMX arg passing test files - Merge MMX bitcast, insert elt and shuffle tests llvm-svn: 227867
2015-02-03 05:56:11 +08:00
%r = insertelement <8 x i8> undef, i8 %x, i32 0
ret <8 x i8> %r
}
; PR2574
define <2 x float> @t2(<2 x float> %a0) {
[X86][SSE] Regenerated the vec_insert tests. llvm-svn: 265179
2016-04-02 03:42:23 +08:00
; X32-LABEL: t2:
; X32: ## BB#0:
; X32-NEXT: xorps %xmm0, %xmm0
; X32-NEXT: retl
;
; X64-LABEL: t2:
; X64: ## BB#0:
; X64-NEXT: xorps %xmm0, %xmm0
; X64-NEXT: retq
[X86][MMX] Cleanup shuffle, bitcast and insert element tests - Merge MMX arg passing test files - Merge MMX bitcast, insert elt and shuffle tests llvm-svn: 227867
2015-02-03 05:56:11 +08:00
%v1 = insertelement <2 x float> %a0, float 0.000000e+00, i32 0
%v2 = insertelement <2 x float> %v1, float 0.000000e+00, i32 1
ret <2 x float> %v2
}
@g0 = external global i16
@g1 = external global <4 x i16>
; PR2562
define void @t3() {
[X86][SSE] Regenerated the vec_insert tests. llvm-svn: 265179
2016-04-02 03:42:23 +08:00
; X32-LABEL: t3:
; X32: ## BB#0:
; X32-NEXT: movl L_g0$non_lazy_ptr, %eax
; X32-NEXT: movl L_g1$non_lazy_ptr, %ecx
; X32-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; X32-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
; X32-NEXT: movzwl (%eax), %eax
; X32-NEXT: movd %eax, %xmm1
; X32-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
; X32-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7]
; X32-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,6,6,7]
; X32-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
; X32-NEXT: movq %xmm0, (%ecx)
; X32-NEXT: retl
;
; X64-LABEL: t3:
; X64: ## BB#0:
; X64-NEXT: movq _g0@{{.*}}(%rip), %rax
; X64-NEXT: movq _g1@{{.*}}(%rip), %rcx
; X64-NEXT: pmovzxwd {{.*#+}} xmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero
; X64-NEXT: movzwl (%rax), %eax
; X64-NEXT: pinsrd $0, %eax, %xmm0
; X64-NEXT: pshufb {{.*#+}} xmm0 = xmm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
; X64-NEXT: movq %xmm0, (%rcx)
; X64-NEXT: retq
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
load i16, i16* @g0
load <4 x i16>, <4 x i16>* @g1
[X86][MMX] Cleanup shuffle, bitcast and insert element tests - Merge MMX arg passing test files - Merge MMX bitcast, insert elt and shuffle tests llvm-svn: 227867
2015-02-03 05:56:11 +08:00
insertelement <4 x i16> %2, i16 %1, i32 0
store <4 x i16> %3, <4 x i16>* @g1
ret void
}