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llvm-project/llvm/test/CodeGen/AMDGPU/i1-copy-implicit-def.ll

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R600/SI: Add a stub GCNTargetMachine This is equivalent to the AMDGPUTargetMachine now, but it is the starting point for separating R600 and GCN functionality into separate targets. It is recommened that users start using the gcn triple for GCN-based GPUs, because using the r600 triple for these GPUs will be deprecated in the future. llvm-svn: 225277
2015-01-07 02:00:21 +08:00
; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
R600/SI: Enable all tests that pass on VI without changes llvm-svn: 227214
2015-01-28 01:27:15 +08:00
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
R600/SI: Fix verifier error from a branch on IMPLICIT_DEF SIILowerI1Copies wasn't correctly handling this case. llvm-svn: 222020
2014-11-15 02:43:41 +08:00
; SILowerI1Copies was not handling IMPLICIT_DEF
R600/SI: Move SIFixSGPRCopies to inst selector passes This should expose more of the actually used VALU instructions to the machine optimization passes. This also should help getting i1 handling into a better state. For not entirly understood reasons, this fixes the split-scalar-i64-add.ll test where a 64-bit add would only partially be moved to the VALU resulting in use of undefined VCC. llvm-svn: 222256
2014-11-19 05:06:58 +08:00
; SI-LABEL: {{^}}br_implicit_def:
R600/SI: Fix verifier error from a branch on IMPLICIT_DEF SIILowerI1Copies wasn't correctly handling this case. llvm-svn: 222020
2014-11-15 02:43:41 +08:00
; SI: BB#0:
AMDGPU/SI: Detect uniform branches and emit s_cbranch instructions Reviewers: arsenm Subscribers: mareko, MatzeB, qcolombet, arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D16603 llvm-svn: 260765
2016-02-13 07:45:29 +08:00
; SI-NEXT: s_and_b64 vcc, exec
; SI-NEXT: s_cbranch_vccnz
R600/SI: Fix verifier error from a branch on IMPLICIT_DEF SIILowerI1Copies wasn't correctly handling this case. llvm-svn: 222020
2014-11-15 02:43:41 +08:00
define void @br_implicit_def(i32 addrspace(1)* %out, i32 %arg) #0 {
bb:
br i1 undef, label %bb1, label %bb2
bb1:
store volatile i32 123, i32 addrspace(1)* %out
ret void
bb2:
ret void
}
attributes #0 = { nounwind }