2016-06-23 02:51:08 +08:00
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; RUN: llc -mtriple=amdgcn--amdhsa -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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declare i32 @llvm.amdgcn.workitem.id.x() #0
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; GCN-LABEL: {{^}}convergent_inlineasm:
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; GCN: BB#0:
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2016-09-30 09:50:20 +08:00
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; GCN: v_cmp_ne_u32_e64
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2016-08-11 03:11:42 +08:00
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; GCN: ; mask branch
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; GCN: BB{{[0-9]+_[0-9]+}}:
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2016-06-23 02:51:08 +08:00
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define void @convergent_inlineasm(i64 addrspace(1)* nocapture %arg) {
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bb:
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%tmp = call i32 @llvm.amdgcn.workitem.id.x()
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2016-09-30 09:50:20 +08:00
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%tmp1 = tail call i64 asm "v_cmp_ne_u32_e64 $0, 0, $1", "=s,v"(i32 1) #1
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2016-06-23 02:51:08 +08:00
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%tmp2 = icmp eq i32 %tmp, 8
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br i1 %tmp2, label %bb3, label %bb5
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bb3: ; preds = %bb
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%tmp4 = getelementptr i64, i64 addrspace(1)* %arg, i32 %tmp
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store i64 %tmp1, i64 addrspace(1)* %arg, align 8
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br label %bb5
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bb5: ; preds = %bb3, %bb
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ret void
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}
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; GCN-LABEL: {{^}}nonconvergent_inlineasm:
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2016-08-11 03:11:42 +08:00
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; GCN: ; mask branch
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; GCN: BB{{[0-9]+_[0-9]+}}:
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2016-09-30 09:50:20 +08:00
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; GCN: v_cmp_ne_u32_e64
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2016-08-11 03:11:42 +08:00
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; GCN: BB{{[0-9]+_[0-9]+}}:
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Codegen: Make chains from trellis-shaped CFGs
Lay out trellis-shaped CFGs optimally.
A trellis of the shape below:
A B
|\ /|
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| / \ |
|/ \|
C D
would be laid out A; B->C ; D by the current layout algorithm. Now we identify
trellises and lay them out either A->C; B->D or A->D; B->C. This scales with an
increasing number of predecessors. A trellis is a a group of 2 or more
predecessor blocks that all have the same successors.
because of this we can tail duplicate to extend existing trellises.
As an example consider the following CFG:
B D F H
/ \ / \ / \ / \
A---C---E---G---Ret
Where A,C,E,G are all small (Currently 2 instructions).
The CFG preserving layout is then A,B,C,D,E,F,G,H,Ret.
The current code will copy C into B, E into D and G into F and yield the layout
A,C,B(C),E,D(E),F(G),G,H,ret
define void @straight_test(i32 %tag) {
entry:
br label %test1
test1: ; A
%tagbit1 = and i32 %tag, 1
%tagbit1eq0 = icmp eq i32 %tagbit1, 0
br i1 %tagbit1eq0, label %test2, label %optional1
optional1: ; B
call void @a()
br label %test2
test2: ; C
%tagbit2 = and i32 %tag, 2
%tagbit2eq0 = icmp eq i32 %tagbit2, 0
br i1 %tagbit2eq0, label %test3, label %optional2
optional2: ; D
call void @b()
br label %test3
test3: ; E
%tagbit3 = and i32 %tag, 4
%tagbit3eq0 = icmp eq i32 %tagbit3, 0
br i1 %tagbit3eq0, label %test4, label %optional3
optional3: ; F
call void @c()
br label %test4
test4: ; G
%tagbit4 = and i32 %tag, 8
%tagbit4eq0 = icmp eq i32 %tagbit4, 0
br i1 %tagbit4eq0, label %exit, label %optional4
optional4: ; H
call void @d()
br label %exit
exit:
ret void
}
here is the layout after D27742:
straight_test: # @straight_test
; ... Prologue elided
; BB#0: # %entry ; A (merged with test1)
; ... More prologue elided
mr 30, 3
andi. 3, 30, 1
bc 12, 1, .LBB0_2
; BB#1: # %test2 ; C
rlwinm. 3, 30, 0, 30, 30
beq 0, .LBB0_3
b .LBB0_4
.LBB0_2: # %optional1 ; B (copy of C)
bl a
nop
rlwinm. 3, 30, 0, 30, 30
bne 0, .LBB0_4
.LBB0_3: # %test3 ; E
rlwinm. 3, 30, 0, 29, 29
beq 0, .LBB0_5
b .LBB0_6
.LBB0_4: # %optional2 ; D (copy of E)
bl b
nop
rlwinm. 3, 30, 0, 29, 29
bne 0, .LBB0_6
.LBB0_5: # %test4 ; G
rlwinm. 3, 30, 0, 28, 28
beq 0, .LBB0_8
b .LBB0_7
.LBB0_6: # %optional3 ; F (copy of G)
bl c
nop
rlwinm. 3, 30, 0, 28, 28
beq 0, .LBB0_8
.LBB0_7: # %optional4 ; H
bl d
nop
.LBB0_8: # %exit ; Ret
ld 30, 96(1) # 8-byte Folded Reload
addi 1, 1, 112
ld 0, 16(1)
mtlr 0
blr
The tail-duplication has produced some benefit, but it has also produced a
trellis which is not laid out optimally. With this patch, we improve the layouts
of such trellises, and decrease the cost calculation for tail-duplication
accordingly.
This patch produces the layout A,C,E,G,B,D,F,H,Ret. This layout does have
back edges, which is a negative, but it has a bigger compensating
positive, which is that it handles the case where there are long strings
of skipped blocks much better than the original layout. Both layouts
handle runs of executed blocks equally well. Branch prediction also
improves if there is any correlation between subsequent optional blocks.
Here is the resulting concrete layout:
straight_test: # @straight_test
; BB#0: # %entry ; A (merged with test1)
mr 30, 3
andi. 3, 30, 1
bc 12, 1, .LBB0_4
; BB#1: # %test2 ; C
rlwinm. 3, 30, 0, 30, 30
bne 0, .LBB0_5
.LBB0_2: # %test3 ; E
rlwinm. 3, 30, 0, 29, 29
bne 0, .LBB0_6
.LBB0_3: # %test4 ; G
rlwinm. 3, 30, 0, 28, 28
bne 0, .LBB0_7
b .LBB0_8
.LBB0_4: # %optional1 ; B (Copy of C)
bl a
nop
rlwinm. 3, 30, 0, 30, 30
beq 0, .LBB0_2
.LBB0_5: # %optional2 ; D (Copy of E)
bl b
nop
rlwinm. 3, 30, 0, 29, 29
beq 0, .LBB0_3
.LBB0_6: # %optional3 ; F (Copy of G)
bl c
nop
rlwinm. 3, 30, 0, 28, 28
beq 0, .LBB0_8
.LBB0_7: # %optional4 ; H
bl d
nop
.LBB0_8: # %exit
Differential Revision: https://reviews.llvm.org/D28522
llvm-svn: 295223
2017-02-16 03:49:14 +08:00
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2016-06-23 02:51:08 +08:00
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define void @nonconvergent_inlineasm(i64 addrspace(1)* nocapture %arg) {
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bb:
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%tmp = call i32 @llvm.amdgcn.workitem.id.x()
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2016-09-30 09:50:20 +08:00
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%tmp1 = tail call i64 asm "v_cmp_ne_u32_e64 $0, 0, $1", "=s,v"(i32 1)
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2016-06-23 02:51:08 +08:00
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%tmp2 = icmp eq i32 %tmp, 8
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br i1 %tmp2, label %bb3, label %bb5
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bb3: ; preds = %bb
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%tmp4 = getelementptr i64, i64 addrspace(1)* %arg, i32 %tmp
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store i64 %tmp1, i64 addrspace(1)* %arg, align 8
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br label %bb5
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bb5: ; preds = %bb3, %bb
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ret void
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}
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attributes #0 = { nounwind readnone }
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attributes #1 = { convergent nounwind readnone }
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