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llvm-project/llvm/test/MC/RISCV/rv32fc-valid.s

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[RISCV] Enable emission of alias instructions by default This patch switches the default for -riscv-no-aliases to false and updates all affected MC and CodeGen tests. As recommended in D41071, MC tests use the canonical instructions and the CodeGen tests use the aliases. Additionally, for the f and d instructions with rounding mode, the tests for the aliased versions are moved and tightened such that they can actually detect if alias emission is enabled. (see D40902 for context) Differential Revision: https://reviews.llvm.org/D41225 Patch by Mario Werner. llvm-svn: 320797
2017-12-15 17:47:01 +08:00
# RUN: llvm-mc %s -triple=riscv32 -mattr=+c,+f -riscv-no-aliases -show-encoding \
[RISCV] MC layer support for the remaining RVC instructions Differential Revision: https://reviews.llvm.org/D40003 Patch by Shiva Chen. llvm-svn: 320558
2017-12-13 17:32:55 +08:00
# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s
# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+c,+f < %s \
[RISCV] Add ELFObjectFileBase::getRISCVFeatures let llvm-objdump could get RISCV target feature llvm-objdump could get C feature by ELF::EF_RISCV_RVC e_flag, so then we don't have to add -mattr=+c on the command line. Differential Revision: https://reviews.llvm.org/D42629 llvm-svn: 324058
2018-02-02 14:01:02 +08:00
# RUN: | llvm-objdump -mattr=+f -riscv-no-aliases -d - \
[RISCV] Enable emission of alias instructions by default This patch switches the default for -riscv-no-aliases to false and updates all affected MC and CodeGen tests. As recommended in D41071, MC tests use the canonical instructions and the CodeGen tests use the aliases. Additionally, for the f and d instructions with rounding mode, the tests for the aliased versions are moved and tightened such that they can actually detect if alias emission is enabled. (see D40902 for context) Differential Revision: https://reviews.llvm.org/D41225 Patch by Mario Werner. llvm-svn: 320797
2017-12-15 17:47:01 +08:00
# RUN: | FileCheck -check-prefix=CHECK-INST %s
[RISCV] Fixed setting predicates for compressed instructions. Summary: Fixed setting predicates for compressed instructions. Some instructions were being generated with C extension enabled only, without proper checks for the other required extensions like F, D and 32 and 64-bit target checks. Affected instructions: C_FLD, C_FLW, C_LD, C_FSD, C_FSW, C_SD, C_JAL, C_ADDIW, C_SUBW, C_ADDW, C_FLDSP, C_FLWSP, C_LDSP, C_FSDSP, C_FSWSP, C_SDSP Reviewers: asb, shiva0217 Reviewed By: asb Subscribers: rbar, johnrusso, simoncook, jordy.potman.lists, sabuasal, niosHD, llvm-commits Differential Revision: https://reviews.llvm.org/D42132 llvm-svn: 322876
2018-01-19 02:54:05 +08:00
# RUN: not llvm-mc -triple riscv32 -mattr=+c \
# RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \
# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
# RUN: not llvm-mc -triple riscv32 \
# RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \
# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
# RUN: not llvm-mc -triple riscv64 -mattr=+c,+f \
# RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \
# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
[RISCV] MC layer support for the remaining RVC instructions Differential Revision: https://reviews.llvm.org/D40003 Patch by Shiva Chen. llvm-svn: 320558
2017-12-13 17:32:55 +08:00
# CHECK-INST: c.flwsp fs0, 252(sp)
# CHECK: encoding: [0x7e,0x74]
[RISCV] Fixed setting predicates for compressed instructions. Summary: Fixed setting predicates for compressed instructions. Some instructions were being generated with C extension enabled only, without proper checks for the other required extensions like F, D and 32 and 64-bit target checks. Affected instructions: C_FLD, C_FLW, C_LD, C_FSD, C_FSW, C_SD, C_JAL, C_ADDIW, C_SUBW, C_ADDW, C_FLDSP, C_FLWSP, C_LDSP, C_FSDSP, C_FSWSP, C_SDSP Reviewers: asb, shiva0217 Reviewed By: asb Subscribers: rbar, johnrusso, simoncook, jordy.potman.lists, sabuasal, niosHD, llvm-commits Differential Revision: https://reviews.llvm.org/D42132 llvm-svn: 322876
2018-01-19 02:54:05 +08:00
# CHECK-NO-EXT: error: instruction use requires an option to be enabled
[RISCV] MC layer support for the remaining RVC instructions Differential Revision: https://reviews.llvm.org/D40003 Patch by Shiva Chen. llvm-svn: 320558
2017-12-13 17:32:55 +08:00
c.flwsp fs0, 252(sp)
# CHECK-INST: c.fswsp fa7, 252(sp)
# CHECK: encoding: [0xc6,0xff]
[RISCV] Fixed setting predicates for compressed instructions. Summary: Fixed setting predicates for compressed instructions. Some instructions were being generated with C extension enabled only, without proper checks for the other required extensions like F, D and 32 and 64-bit target checks. Affected instructions: C_FLD, C_FLW, C_LD, C_FSD, C_FSW, C_SD, C_JAL, C_ADDIW, C_SUBW, C_ADDW, C_FLDSP, C_FLWSP, C_LDSP, C_FSDSP, C_FSWSP, C_SDSP Reviewers: asb, shiva0217 Reviewed By: asb Subscribers: rbar, johnrusso, simoncook, jordy.potman.lists, sabuasal, niosHD, llvm-commits Differential Revision: https://reviews.llvm.org/D42132 llvm-svn: 322876
2018-01-19 02:54:05 +08:00
# CHECK-NO-EXT: error: instruction use requires an option to be enabled
[RISCV] MC layer support for the remaining RVC instructions Differential Revision: https://reviews.llvm.org/D40003 Patch by Shiva Chen. llvm-svn: 320558
2017-12-13 17:32:55 +08:00
c.fswsp fa7, 252(sp)
# CHECK-INST: c.flw fa3, 124(a5)
# CHECK: encoding: [0xf4,0x7f]
[RISCV] Fixed setting predicates for compressed instructions. Summary: Fixed setting predicates for compressed instructions. Some instructions were being generated with C extension enabled only, without proper checks for the other required extensions like F, D and 32 and 64-bit target checks. Affected instructions: C_FLD, C_FLW, C_LD, C_FSD, C_FSW, C_SD, C_JAL, C_ADDIW, C_SUBW, C_ADDW, C_FLDSP, C_FLWSP, C_LDSP, C_FSDSP, C_FSWSP, C_SDSP Reviewers: asb, shiva0217 Reviewed By: asb Subscribers: rbar, johnrusso, simoncook, jordy.potman.lists, sabuasal, niosHD, llvm-commits Differential Revision: https://reviews.llvm.org/D42132 llvm-svn: 322876
2018-01-19 02:54:05 +08:00
# CHECK-NO-EXT: error: instruction use requires an option to be enabled
[RISCV] MC layer support for the remaining RVC instructions Differential Revision: https://reviews.llvm.org/D40003 Patch by Shiva Chen. llvm-svn: 320558
2017-12-13 17:32:55 +08:00
c.flw fa3, 124(a5)
# CHECK-INST: c.fsw fa2, 124(a1)
# CHECK: encoding: [0xf0,0xfd]
[RISCV] Fixed setting predicates for compressed instructions. Summary: Fixed setting predicates for compressed instructions. Some instructions were being generated with C extension enabled only, without proper checks for the other required extensions like F, D and 32 and 64-bit target checks. Affected instructions: C_FLD, C_FLW, C_LD, C_FSD, C_FSW, C_SD, C_JAL, C_ADDIW, C_SUBW, C_ADDW, C_FLDSP, C_FLWSP, C_LDSP, C_FSDSP, C_FSWSP, C_SDSP Reviewers: asb, shiva0217 Reviewed By: asb Subscribers: rbar, johnrusso, simoncook, jordy.potman.lists, sabuasal, niosHD, llvm-commits Differential Revision: https://reviews.llvm.org/D42132 llvm-svn: 322876
2018-01-19 02:54:05 +08:00
# CHECK-NO-EXT: error: instruction use requires an option to be enabled
[RISCV] MC layer support for the remaining RVC instructions Differential Revision: https://reviews.llvm.org/D40003 Patch by Shiva Chen. llvm-svn: 320558
2017-12-13 17:32:55 +08:00
c.fsw fa2, 124(a1)