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llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/regbankselect-default.mir

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[AArch64][GlobalISel] Add tests for default RegBank mappings. NFC. llvm-svn: 281733
2016-09-16 22:44:48 +08:00
# RUN: llc -O0 -mtriple arm64-- -run-pass=regbankselect -global-isel %s -o - | FileCheck %s
# Check the default mappings for various instructions.
--- |
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
define void @test_add_s32() { ret void }
define void @test_add_v4s32() { ret void }
define void @test_sub_s32() { ret void }
define void @test_sub_v4s32() { ret void }
define void @test_mul_s32() { ret void }
define void @test_mul_v4s32() { ret void }
define void @test_and_s32() { ret void }
define void @test_and_v4s32() { ret void }
define void @test_or_s32() { ret void }
define void @test_or_v4s32() { ret void }
define void @test_xor_s32() { ret void }
define void @test_xor_v4s32() { ret void }
define void @test_shl_s32() { ret void }
define void @test_shl_v4s32() { ret void }
define void @test_lshr_s32() { ret void }
define void @test_ashr_s32() { ret void }
define void @test_sdiv_s32() { ret void }
define void @test_udiv_s32() { ret void }
[AArch64][GlobalISel] Add default regbank mappings for mixed-type ops. We used to only support instructions with same-type operands. Instead, use the per-register type information to map each operand more accurately. llvm-svn: 281734
2016-09-16 22:44:51 +08:00
define void @test_anyext_s64_s32() { ret void }
define void @test_sext_s64_s32() { ret void }
define void @test_zext_s64_s32() { ret void }
define void @test_trunc_s32_s64() { ret void }
define void @test_constant_s32() { ret void }
define void @test_constant_p0() { ret void }
[AArch64][GlobalISel] Test default regbank mapping for G_ICMP. Also relax a RegisterBankInfo verifier check that's incompatible with 1-bit mappings. llvm-svn: 281735
2016-09-16 22:44:54 +08:00
define void @test_icmp_s32() { ret void }
define void @test_icmp_p0() { ret void }
[AArch64][GlobalISel] Add default regbank mappings for mixed-type ops. We used to only support instructions with same-type operands. Instead, use the per-register type information to map each operand more accurately. llvm-svn: 281734
2016-09-16 22:44:51 +08:00
define void @test_frame_index_p0() {
%ptr0 = alloca i64
ret void
}
define void @test_ptrtoint_s64_p0() { ret void }
define void @test_inttoptr_p0_s64() { ret void }
define void @test_load_s32_p0() { ret void }
define void @test_store_s32_p0() { ret void }
[AArch64][GlobalISel] Add default regbank mapping for FP ops. These should have all their operands - even scalars - go on FPR. llvm-svn: 281737
2016-09-16 23:12:40 +08:00
define void @test_fadd_s32() { ret void }
define void @test_fsub_s32() { ret void }
define void @test_fmul_s32() { ret void }
define void @test_fdiv_s32() { ret void }
define void @test_fpext_s64_s32() { ret void }
define void @test_fptrunc_s32_s64() { ret void }
define void @test_fconstant_s32() { ret void }
[AArch64][GlobalISel] Add default regbank mapping for G_FCMP. llvm-svn: 281738
2016-09-16 23:12:43 +08:00
define void @test_fcmp_s32() { ret void }
[AArch64][GlobalISel] Add default regbank mapping for int<>FP. llvm-svn: 281739
2016-09-16 23:12:46 +08:00
define void @test_sitofp_s64_s32() { ret void }
define void @test_uitofp_s32_s64() { ret void }
define void @test_fptosi_s64_s32() { ret void }
define void @test_fptoui_s32_s64() { ret void }
[AArch64][GlobalISel] Add tests for default RegBank mappings. NFC. llvm-svn: 281733
2016-09-16 22:44:48 +08:00
...
---
# CHECK-LABEL: name: test_add_s32
name: test_add_s32
legalized: true
# CHECK: registers:
# CHECK: - { id: 0, class: gpr }
# CHECK: - { id: 1, class: gpr }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
body: |
bb.0:
liveins: %w0
; CHECK: %0(s32) = COPY %w0
; CHECK: %1(s32) = G_ADD %0, %0
%0(s32) = COPY %w0
%1(s32) = G_ADD %0, %0
...
---
# CHECK-LABEL: name: test_add_v4s32
name: test_add_v4s32
legalized: true
# CHECK: registers:
# CHECK: - { id: 0, class: fpr }
# CHECK: - { id: 1, class: fpr }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
body: |
bb.0:
liveins: %q0
; CHECK: %0(<4 x s32>) = COPY %q0
; CHECK: %1(<4 x s32>) = G_ADD %0, %0
%0(<4 x s32>) = COPY %q0
%1(<4 x s32>) = G_ADD %0, %0
...
---
# CHECK-LABEL: name: test_sub_s32
name: test_sub_s32
legalized: true
# CHECK: registers:
# CHECK: - { id: 0, class: gpr }
# CHECK: - { id: 1, class: gpr }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
body: |
bb.0:
liveins: %w0
; CHECK: %0(s32) = COPY %w0
; CHECK: %1(s32) = G_SUB %0, %0
%0(s32) = COPY %w0
%1(s32) = G_SUB %0, %0
...
---
# CHECK-LABEL: name: test_sub_v4s32
name: test_sub_v4s32
legalized: true
# CHECK: registers:
# CHECK: - { id: 0, class: fpr }
# CHECK: - { id: 1, class: fpr }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
body: |
bb.0:
liveins: %q0
; CHECK: %0(<4 x s32>) = COPY %q0
; CHECK: %1(<4 x s32>) = G_SUB %0, %0
%0(<4 x s32>) = COPY %q0
%1(<4 x s32>) = G_SUB %0, %0
...
---
# CHECK-LABEL: name: test_mul_s32
name: test_mul_s32
legalized: true
# CHECK: registers:
# CHECK: - { id: 0, class: gpr }
# CHECK: - { id: 1, class: gpr }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
body: |
bb.0:
liveins: %w0
; CHECK: %0(s32) = COPY %w0
; CHECK: %1(s32) = G_MUL %0, %0
%0(s32) = COPY %w0
%1(s32) = G_MUL %0, %0
...
---
# CHECK-LABEL: name: test_mul_v4s32
name: test_mul_v4s32
legalized: true
# CHECK: registers:
# CHECK: - { id: 0, class: fpr }
# CHECK: - { id: 1, class: fpr }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
body: |
bb.0:
liveins: %q0
; CHECK: %0(<4 x s32>) = COPY %q0
; CHECK: %1(<4 x s32>) = G_MUL %0, %0
%0(<4 x s32>) = COPY %q0
%1(<4 x s32>) = G_MUL %0, %0
...
---
# CHECK-LABEL: name: test_and_s32
name: test_and_s32
legalized: true
# CHECK: registers:
# CHECK: - { id: 0, class: gpr }
# CHECK: - { id: 1, class: gpr }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
body: |
bb.0:
liveins: %w0
; CHECK: %0(s32) = COPY %w0
; CHECK: %1(s32) = G_AND %0, %0
%0(s32) = COPY %w0
%1(s32) = G_AND %0, %0
...
---
# CHECK-LABEL: name: test_and_v4s32
name: test_and_v4s32
legalized: true
# CHECK: registers:
# CHECK: - { id: 0, class: fpr }
# CHECK: - { id: 1, class: fpr }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
body: |
bb.0:
liveins: %q0
; CHECK: %0(<4 x s32>) = COPY %q0
; CHECK: %1(<4 x s32>) = G_AND %0, %0
%0(<4 x s32>) = COPY %q0
%1(<4 x s32>) = G_AND %0, %0
...
---
# CHECK-LABEL: name: test_or_s32
name: test_or_s32
legalized: true
# CHECK: registers:
# CHECK: - { id: 0, class: gpr }
# CHECK: - { id: 1, class: gpr }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
body: |
bb.0:
liveins: %w0
; CHECK: %0(s32) = COPY %w0
; CHECK: %1(s32) = G_OR %0, %0
%0(s32) = COPY %w0
%1(s32) = G_OR %0, %0
...
---
# CHECK-LABEL: name: test_or_v4s32
name: test_or_v4s32
legalized: true
# CHECK: registers:
# CHECK: - { id: 0, class: fpr }
# CHECK: - { id: 1, class: fpr }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
body: |
bb.0:
liveins: %q0
; CHECK: %0(<4 x s32>) = COPY %q0
; CHECK: %1(<4 x s32>) = G_OR %0, %0
%0(<4 x s32>) = COPY %q0
%1(<4 x s32>) = G_OR %0, %0
...
---
# CHECK-LABEL: name: test_xor_s32
name: test_xor_s32
legalized: true
# CHECK: registers:
# CHECK: - { id: 0, class: gpr }
# CHECK: - { id: 1, class: gpr }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
body: |
bb.0:
liveins: %w0
; CHECK: %0(s32) = COPY %w0
; CHECK: %1(s32) = G_XOR %0, %0
%0(s32) = COPY %w0
%1(s32) = G_XOR %0, %0
...
---
# CHECK-LABEL: name: test_xor_v4s32
name: test_xor_v4s32
legalized: true
# CHECK: registers:
# CHECK: - { id: 0, class: fpr }
# CHECK: - { id: 1, class: fpr }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
body: |
bb.0:
liveins: %q0
; CHECK: %0(<4 x s32>) = COPY %q0
; CHECK: %1(<4 x s32>) = G_XOR %0, %0
%0(<4 x s32>) = COPY %q0
%1(<4 x s32>) = G_XOR %0, %0
...
---
# CHECK-LABEL: name: test_shl_s32
name: test_shl_s32
legalized: true
# CHECK: registers:
# CHECK: - { id: 0, class: gpr }
# CHECK: - { id: 1, class: gpr }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
body: |
bb.0:
liveins: %w0
; CHECK: %0(s32) = COPY %w0
; CHECK: %1(s32) = G_SHL %0, %0
%0(s32) = COPY %w0
%1(s32) = G_SHL %0, %0
...
---
# CHECK-LABEL: name: test_shl_v4s32
name: test_shl_v4s32
legalized: true
# CHECK: registers:
# CHECK: - { id: 0, class: fpr }
# CHECK: - { id: 1, class: fpr }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
body: |
bb.0:
liveins: %q0
; CHECK: %0(<4 x s32>) = COPY %q0
; CHECK: %1(<4 x s32>) = G_SHL %0, %0
%0(<4 x s32>) = COPY %q0
%1(<4 x s32>) = G_SHL %0, %0
...
---
# CHECK-LABEL: name: test_lshr_s32
name: test_lshr_s32
legalized: true
# CHECK: registers:
# CHECK: - { id: 0, class: gpr }
# CHECK: - { id: 1, class: gpr }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
body: |
bb.0:
liveins: %w0
; CHECK: %0(s32) = COPY %w0
; CHECK: %1(s32) = G_LSHR %0, %0
%0(s32) = COPY %w0
%1(s32) = G_LSHR %0, %0
...
---
# CHECK-LABEL: name: test_ashr_s32
name: test_ashr_s32
legalized: true
# CHECK: registers:
# CHECK: - { id: 0, class: gpr }
# CHECK: - { id: 1, class: gpr }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
body: |
bb.0:
liveins: %w0
; CHECK: %0(s32) = COPY %w0
; CHECK: %1(s32) = G_ASHR %0, %0
%0(s32) = COPY %w0
%1(s32) = G_ASHR %0, %0
...
---
# CHECK-LABEL: name: test_sdiv_s32
name: test_sdiv_s32
legalized: true
# CHECK: registers:
# CHECK: - { id: 0, class: gpr }
# CHECK: - { id: 1, class: gpr }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
body: |
bb.0:
liveins: %w0
; CHECK: %0(s32) = COPY %w0
; CHECK: %1(s32) = G_SDIV %0, %0
%0(s32) = COPY %w0
%1(s32) = G_SDIV %0, %0
...
---
# CHECK-LABEL: name: test_udiv_s32
name: test_udiv_s32
legalized: true
# CHECK: registers:
# CHECK: - { id: 0, class: gpr }
# CHECK: - { id: 1, class: gpr }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
body: |
bb.0:
liveins: %w0
; CHECK: %0(s32) = COPY %w0
; CHECK: %1(s32) = G_UDIV %0, %0
%0(s32) = COPY %w0
%1(s32) = G_UDIV %0, %0
...
[AArch64][GlobalISel] Add default regbank mappings for mixed-type ops. We used to only support instructions with same-type operands. Instead, use the per-register type information to map each operand more accurately. llvm-svn: 281734
2016-09-16 22:44:51 +08:00
---
# CHECK-LABEL: name: test_anyext_s64_s32
name: test_anyext_s64_s32
legalized: true
# CHECK: registers:
# CHECK: - { id: 0, class: gpr }
# CHECK: - { id: 1, class: gpr }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
body: |
bb.0:
liveins: %w0
; CHECK: %0(s32) = COPY %w0
; CHECK: %1(s64) = G_ANYEXT %0
%0(s32) = COPY %w0
%1(s64) = G_ANYEXT %0
...
---
# CHECK-LABEL: name: test_sext_s64_s32
name: test_sext_s64_s32
legalized: true
# CHECK: registers:
# CHECK: - { id: 0, class: gpr }
# CHECK: - { id: 1, class: gpr }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
body: |
bb.0:
liveins: %w0
; CHECK: %0(s32) = COPY %w0
; CHECK: %1(s64) = G_SEXT %0
%0(s32) = COPY %w0
%1(s64) = G_SEXT %0
...
---
# CHECK-LABEL: name: test_zext_s64_s32
name: test_zext_s64_s32
legalized: true
# CHECK: registers:
# CHECK: - { id: 0, class: gpr }
# CHECK: - { id: 1, class: gpr }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
body: |
bb.0:
liveins: %w0
; CHECK: %0(s32) = COPY %w0
; CHECK: %1(s64) = G_ZEXT %0
%0(s32) = COPY %w0
%1(s64) = G_ZEXT %0
...
---
# CHECK-LABEL: name: test_trunc_s32_s64
name: test_trunc_s32_s64
legalized: true
# CHECK: registers:
# CHECK: - { id: 0, class: gpr }
# CHECK: - { id: 1, class: gpr }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
body: |
bb.0:
liveins: %x0
; CHECK: %0(s64) = COPY %x0
; CHECK: %1(s32) = G_TRUNC %0
%0(s64) = COPY %x0
%1(s32) = G_TRUNC %0
...
---
# CHECK-LABEL: name: test_constant_s32
name: test_constant_s32
legalized: true
# CHECK: registers:
# CHECK: - { id: 0, class: gpr }
registers:
- { id: 0, class: _ }
body: |
bb.0:
; CHECK: %0(s32) = G_CONSTANT 123
%0(s32) = G_CONSTANT 123
...
---
# CHECK-LABEL: name: test_constant_p0
name: test_constant_p0
legalized: true
# CHECK: registers:
# CHECK: - { id: 0, class: gpr }
registers:
- { id: 0, class: _ }
body: |
bb.0:
; CHECK: %0(p0) = G_CONSTANT 0
%0(p0) = G_CONSTANT 0
...
[AArch64][GlobalISel] Test default regbank mapping for G_ICMP. Also relax a RegisterBankInfo verifier check that's incompatible with 1-bit mappings. llvm-svn: 281735
2016-09-16 22:44:54 +08:00
---
# CHECK-LABEL: name: test_icmp_s32
name: test_icmp_s32
legalized: true
# CHECK: registers:
# CHECK: - { id: 0, class: gpr }
# CHECK: - { id: 1, class: gpr }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
body: |
bb.0:
liveins: %w0
; CHECK: %0(s32) = COPY %w0
; CHECK: %1(s1) = G_ICMP intpred(ne), %0(s32), %0
%0(s32) = COPY %w0
%1(s1) = G_ICMP intpred(ne), %0, %0
...
---
# CHECK-LABEL: name: test_icmp_p0
name: test_icmp_p0
legalized: true
# CHECK: registers:
# CHECK: - { id: 0, class: gpr }
# CHECK: - { id: 1, class: gpr }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
body: |
bb.0:
liveins: %x0
; CHECK: %0(p0) = COPY %x0
; CHECK: %1(s1) = G_ICMP intpred(ne), %0(p0), %0
%0(p0) = COPY %x0
%1(s1) = G_ICMP intpred(ne), %0, %0
...
[AArch64][GlobalISel] Add default regbank mappings for mixed-type ops. We used to only support instructions with same-type operands. Instead, use the per-register type information to map each operand more accurately. llvm-svn: 281734
2016-09-16 22:44:51 +08:00
---
# CHECK-LABEL: name: test_frame_index_p0
name: test_frame_index_p0
legalized: true
# CHECK: registers:
# CHECK: - { id: 0, class: gpr }
registers:
- { id: 0, class: _ }
stack:
- { id: 0, name: ptr0, offset: 0, size: 8, alignment: 8 }
body: |
bb.0:
; CHECK: %0(p0) = G_FRAME_INDEX %stack.0.ptr0
%0(p0) = G_FRAME_INDEX %stack.0.ptr0
...
---
# CHECK-LABEL: name: test_ptrtoint_s64_p0
name: test_ptrtoint_s64_p0
legalized: true
# CHECK: registers:
# CHECK: - { id: 0, class: gpr }
# CHECK: - { id: 1, class: gpr }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
body: |
bb.0:
liveins: %x0
; CHECK: %0(p0) = COPY %x0
; CHECK: %1(s64) = G_PTRTOINT %0
%0(p0) = COPY %x0
%1(s64) = G_PTRTOINT %0
...
---
# CHECK-LABEL: name: test_inttoptr_p0_s64
name: test_inttoptr_p0_s64
legalized: true
# CHECK: registers:
# CHECK: - { id: 0, class: gpr }
# CHECK: - { id: 1, class: gpr }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
body: |
bb.0:
liveins: %x0
; CHECK: %0(s64) = COPY %x0
; CHECK: %1(p0) = G_INTTOPTR %0
%0(s64) = COPY %x0
%1(p0) = G_INTTOPTR %0
...
---
# CHECK-LABEL: name: test_load_s32_p0
name: test_load_s32_p0
legalized: true
# CHECK: registers:
# CHECK: - { id: 0, class: gpr }
# CHECK: - { id: 1, class: gpr }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
body: |
bb.0:
liveins: %x0
; CHECK: %0(p0) = COPY %x0
; CHECK: %1(s32) = G_LOAD %0
%0(p0) = COPY %x0
GlobalISel: verify that generic loads & stores have a mem operand. The mem operand is used by GlobalISel to convey atomic constraints so dropping it is invalid. llvm-svn: 295476
2017-02-18 02:50:15 +08:00
%1(s32) = G_LOAD %0 :: (load 4)
[AArch64][GlobalISel] Add default regbank mappings for mixed-type ops. We used to only support instructions with same-type operands. Instead, use the per-register type information to map each operand more accurately. llvm-svn: 281734
2016-09-16 22:44:51 +08:00
...
---
# CHECK-LABEL: name: test_store_s32_p0
name: test_store_s32_p0
legalized: true
# CHECK: registers:
# CHECK: - { id: 0, class: gpr }
# CHECK: - { id: 1, class: gpr }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
body: |
bb.0:
liveins: %x0, %w1
; CHECK: %0(p0) = COPY %x0
; CHECK: %1(s32) = COPY %w1
; CHECK: G_STORE %1(s32), %0(p0)
%0(p0) = COPY %x0
%1(s32) = COPY %w1
GlobalISel: verify that generic loads & stores have a mem operand. The mem operand is used by GlobalISel to convey atomic constraints so dropping it is invalid. llvm-svn: 295476
2017-02-18 02:50:15 +08:00
G_STORE %1, %0 :: (store 4)
[AArch64][GlobalISel] Add default regbank mappings for mixed-type ops. We used to only support instructions with same-type operands. Instead, use the per-register type information to map each operand more accurately. llvm-svn: 281734
2016-09-16 22:44:51 +08:00
...
[AArch64][GlobalISel] Add default regbank mapping for FP ops. These should have all their operands - even scalars - go on FPR. llvm-svn: 281737
2016-09-16 23:12:40 +08:00
---
# CHECK-LABEL: name: test_fadd_s32
name: test_fadd_s32
legalized: true
# CHECK: registers:
# CHECK: - { id: 0, class: fpr }
# CHECK: - { id: 1, class: fpr }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
body: |
bb.0:
liveins: %s0
; CHECK: %0(s32) = COPY %s0
; CHECK: %1(s32) = G_FADD %0, %0
%0(s32) = COPY %s0
%1(s32) = G_FADD %0, %0
...
---
# CHECK-LABEL: name: test_fsub_s32
name: test_fsub_s32
legalized: true
# CHECK: registers:
# CHECK: - { id: 0, class: fpr }
# CHECK: - { id: 1, class: fpr }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
body: |
bb.0:
liveins: %s0
; CHECK: %0(s32) = COPY %s0
; CHECK: %1(s32) = G_FSUB %0, %0
%0(s32) = COPY %s0
%1(s32) = G_FSUB %0, %0
...
---
# CHECK-LABEL: name: test_fmul_s32
name: test_fmul_s32
legalized: true
# CHECK: registers:
# CHECK: - { id: 0, class: fpr }
# CHECK: - { id: 1, class: fpr }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
body: |
bb.0:
liveins: %s0
; CHECK: %0(s32) = COPY %s0
; CHECK: %1(s32) = G_FMUL %0, %0
%0(s32) = COPY %s0
%1(s32) = G_FMUL %0, %0
...
---
# CHECK-LABEL: name: test_fdiv_s32
name: test_fdiv_s32
legalized: true
# CHECK: registers:
# CHECK: - { id: 0, class: fpr }
# CHECK: - { id: 1, class: fpr }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
body: |
bb.0:
liveins: %s0
; CHECK: %0(s32) = COPY %s0
; CHECK: %1(s32) = G_FDIV %0, %0
%0(s32) = COPY %s0
%1(s32) = G_FDIV %0, %0
...
---
# CHECK-LABEL: name: test_fpext_s64_s32
name: test_fpext_s64_s32
legalized: true
# CHECK: registers:
# CHECK: - { id: 0, class: fpr }
# CHECK: - { id: 1, class: fpr }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
body: |
bb.0:
liveins: %s0
; CHECK: %0(s32) = COPY %s0
; CHECK: %1(s64) = G_FPEXT %0
%0(s32) = COPY %s0
%1(s64) = G_FPEXT %0
...
---
# CHECK-LABEL: name: test_fptrunc_s32_s64
name: test_fptrunc_s32_s64
legalized: true
# CHECK: registers:
# CHECK: - { id: 0, class: fpr }
# CHECK: - { id: 1, class: fpr }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
body: |
bb.0:
liveins: %d0
; CHECK: %0(s64) = COPY %d0
; CHECK: %1(s32) = G_FPTRUNC %0
%0(s64) = COPY %d0
%1(s32) = G_FPTRUNC %0
...
---
# CHECK-LABEL: name: test_fconstant_s32
name: test_fconstant_s32
legalized: true
# CHECK: registers:
# CHECK: - { id: 0, class: fpr }
registers:
- { id: 0, class: _ }
body: |
bb.0:
; CHECK: %0(s32) = G_FCONSTANT float 1.0
%0(s32) = G_FCONSTANT float 1.0
...
[AArch64][GlobalISel] Add default regbank mapping for G_FCMP. llvm-svn: 281738
2016-09-16 23:12:43 +08:00
---
# CHECK-LABEL: name: test_fcmp_s32
name: test_fcmp_s32
legalized: true
# CHECK: registers:
# CHECK: - { id: 0, class: fpr }
# CHECK: - { id: 1, class: gpr }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
body: |
bb.0:
liveins: %s0
; CHECK: %0(s32) = COPY %s0
; CHECK: %1(s1) = G_FCMP floatpred(olt), %0(s32), %0
%0(s32) = COPY %s0
%1(s1) = G_FCMP floatpred(olt), %0, %0
...
[AArch64][GlobalISel] Add default regbank mapping for int<>FP. llvm-svn: 281739
2016-09-16 23:12:46 +08:00
---
# CHECK-LABEL: name: test_sitofp_s64_s32
name: test_sitofp_s64_s32
legalized: true
# CHECK: registers:
# CHECK: - { id: 0, class: gpr }
# CHECK: - { id: 1, class: fpr }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
body: |
bb.0:
liveins: %w0
; CHECK: %0(s32) = COPY %w0
; CHECK: %1(s64) = G_SITOFP %0
%0(s32) = COPY %w0
%1(s64) = G_SITOFP %0
...
---
# CHECK-LABEL: name: test_uitofp_s32_s64
name: test_uitofp_s32_s64
legalized: true
# CHECK: registers:
# CHECK: - { id: 0, class: gpr }
# CHECK: - { id: 1, class: fpr }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
body: |
bb.0:
liveins: %x0
; CHECK: %0(s64) = COPY %x0
; CHECK: %1(s32) = G_UITOFP %0
%0(s64) = COPY %x0
%1(s32) = G_UITOFP %0
...
---
# CHECK-LABEL: name: test_fptosi_s64_s32
name: test_fptosi_s64_s32
legalized: true
# CHECK: registers:
# CHECK: - { id: 0, class: fpr }
# CHECK: - { id: 1, class: gpr }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
body: |
bb.0:
liveins: %s0
; CHECK: %0(s32) = COPY %s0
; CHECK: %1(s64) = G_FPTOSI %0
%0(s32) = COPY %s0
%1(s64) = G_FPTOSI %0
...
---
# CHECK-LABEL: name: test_fptoui_s32_s64
name: test_fptoui_s32_s64
legalized: true
# CHECK: registers:
# CHECK: - { id: 0, class: fpr }
# CHECK: - { id: 1, class: gpr }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
body: |
bb.0:
liveins: %d0
; CHECK: %0(s64) = COPY %d0
; CHECK: %1(s32) = G_FPTOUI %0
%0(s64) = COPY %d0
%1(s32) = G_FPTOUI %0
...