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llvm-project/llvm/test/CodeGen/Mips/longbranch.ll

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[mips] Add partial support for R6 in the long branch pass MIPSR6 introduced several new jump instructions and deprecated the use of the 'j' instruction. For microMIPS32R6, 'j' was removed entirely and it only has non delay slot jumps. This patch adds support for MIPSR6 by using some R6 instructions-- 'bc' instead of 'j', 'jic $reg, 0' instead of 'jalr $zero, $reg'-- and modifies the sequences not to use delay slots for R6. Reviewers: atanasyan Reviewed By: atanasyan Subscribers: dschuff, arichardson, llvm-commits Differential Revision: https://reviews.llvm.org/D40786 llvm-svn: 320703
2017-12-14 22:55:25 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; Except for the NACL version which isn't parsed by update_llc_test_checks.py
; RUN: llc -mtriple=mipsel-unknown-linux-gnu -O3 -relocation-model=pic < %s \
; RUN: | FileCheck %s -check-prefix=NOLONGBRANCH
; RUN: llc -mtriple=mipsel-unknown-linux-gnu -force-mips-long-branch -O3 -relocation-model=pic < %s \
; RUN: | FileCheck %s -check-prefix=O32-PIC
; RUN: llc -mtriple=mipsel-unknown-linux-gnu -force-mips-long-branch -O3 -relocation-model=static < %s \
; RUN: | FileCheck %s -check-prefix=O32-STATIC
; RUN: llc -mtriple=mipsel-unknown-linux-gnu -mcpu=mips32r6 -force-mips-long-branch -O3 \
; RUN: -relocation-model=pic < %s | FileCheck %s -check-prefix=O32-R6-PIC
; RUN: llc -mtriple=mips64el-unknown-linux-gnu -mcpu=mips4 -target-abi=n64 -force-mips-long-branch -O3 -relocation-model=pic \
; RUN: < %s | FileCheck %s -check-prefix=MIPS4
; RUN: llc -mtriple=mips64el-unknown-linux-gnu -mcpu=mips64 -target-abi=n64 -force-mips-long-branch -O3 -relocation-model=pic \
; RUN: < %s | FileCheck %s -check-prefix=MIPS64
; RUN: llc -mtriple=mips64el-unknown-linux-gnu -mcpu=mips64r6 -target-abi=n64 -force-mips-long-branch -O3 \
; RUN: -relocation-model=pic < %s | FileCheck %s -check-prefix=N64-R6
; RUN: llc -mtriple=mipsel-unknown-linux-gnu -mcpu=mips32r2 -mattr=micromips \
Revert r305382, it caused PR33513. llvm-svn: 305735
2017-06-20 03:48:59 +08:00
; RUN: -force-mips-long-branch -O3 -relocation-model=pic < %s | FileCheck %s -check-prefix=MICROMIPS
[mips] Add partial support for R6 in the long branch pass MIPSR6 introduced several new jump instructions and deprecated the use of the 'j' instruction. For microMIPS32R6, 'j' was removed entirely and it only has non delay slot jumps. This patch adds support for MIPSR6 by using some R6 instructions-- 'bc' instead of 'j', 'jic $reg, 0' instead of 'jalr $zero, $reg'-- and modifies the sequences not to use delay slots for R6. Reviewers: atanasyan Reviewed By: atanasyan Subscribers: dschuff, arichardson, llvm-commits Differential Revision: https://reviews.llvm.org/D40786 llvm-svn: 320703
2017-12-14 22:55:25 +08:00
; RUN: llc -mtriple=mipsel-unknown-linux-gnu -mcpu=mips32r2 -mattr=micromips \
; RUN: -force-mips-long-branch -O3 -relocation-model=static < %s | FileCheck %s -check-prefix=MICROMIPSSTATIC
; RUN: llc -mtriple=mipsel-unknown-linux-gnu -mcpu=mips32r6 -mattr=micromips \
; RUN: -force-mips-long-branch -O3 -relocation-model=static < %s | FileCheck %s -check-prefix=MICROMIPSR6STATIC
; RUN: llc -mtriple=mipsel-unknown-linux-gnu -mcpu=mips32r6 -mattr=micromips \
; RUN: -force-mips-long-branch -O3 -relocation-model=pic < %s | FileCheck %s -check-prefix=MICROMIPSR6PIC
Revert r305382, it caused PR33513. llvm-svn: 305735
2017-06-20 03:48:59 +08:00
; RUN: llc -mtriple=mipsel-none-nacl -force-mips-long-branch -O3 -relocation-model=pic < %s \
[mips] Modify long branch for NaCl: * Move the instruction that changes sp outside of the branch delay slot. * Bundle-align the target of indirect branch. Differential Revision: http://llvm-reviews.chandlerc.com/D3928 llvm-svn: 210262
2014-06-05 21:52:08 +08:00
; RUN: | FileCheck %s -check-prefix=NACL
Test case for MIPS long branch pass. llvm-svn: 158438
2012-06-14 10:12:21 +08:00
[mips] Fix MipsLongBranch pass to work when the offset from the branch to the target cannot be determined accurately. This is the case for NaCl where the sandboxing instructions are added in MC layer, after the MipsLongBranch pass. It is also the case when the code has inline assembly. Instead of calculating offset in the MipsLongBranch pass, use %hi(sym1 - sym2) and %lo(sym1 - sym2) expressions that are resolved during the fixup. This patch also deletes microMIPS test file test/CodeGen/Mips/micromips-long-branch.ll and implements microMIPS CHECKs in a much simpler way in a file test/CodeGen/Mips/longbranch.ll, together with MIPS32 and MIPS64. llvm-svn: 207656
2014-04-30 23:06:25 +08:00
@x = external global i32
[mips] Promote i32 arguments to i64 for the N32/N64 ABI and fix <64-bit structs... Summary: ... and after all that refactoring, it's possible to distinguish softfloat floating point values from integers so this patch no longer breaks softfloat to do it. Remove direct handling of i32's in the N32/N64 ABI by promoting them to i64. This more closely reflects the ABI documentation and also fixes problems with stack arguments on big-endian targets. We now rely on signext/zeroext annotations (already generated by clang) and the Assert[SZ]ext nodes to avoid the introduction of unnecessary sign/zero extends. It was not possible to convert three tests to use signext/zeroext. These tests are bswap.ll, ctlz-v.ll, ctlz-v.ll. It's not possible to put signext on a vector type so we just accept the sign extends here for now. These tests don't pass the vectors the same way clang does (clang puts multiple elements in the same argument, these map 1 element to 1 argument) so we don't need to worry too much about it. With this patch, all known N32/N64 bugs should be fixed and we now pass the first 10,000 tests generated by ABITest.py. Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6117 llvm-svn: 221534
2014-11-08 00:54:21 +08:00
define void @test1(i32 signext %s) {
[mips] Add partial support for R6 in the long branch pass MIPSR6 introduced several new jump instructions and deprecated the use of the 'j' instruction. For microMIPS32R6, 'j' was removed entirely and it only has non delay slot jumps. This patch adds support for MIPSR6 by using some R6 instructions-- 'bc' instead of 'j', 'jic $reg, 0' instead of 'jalr $zero, $reg'-- and modifies the sequences not to use delay slots for R6. Reviewers: atanasyan Reviewed By: atanasyan Subscribers: dschuff, arichardson, llvm-commits Differential Revision: https://reviews.llvm.org/D40786 llvm-svn: 320703
2017-12-14 22:55:25 +08:00
; NOLONGBRANCH-LABEL: test1:
; NOLONGBRANCH: # %bb.0: # %entry
; NOLONGBRANCH-NEXT: lui $2, %hi(_gp_disp)
; NOLONGBRANCH-NEXT: addiu $2, $2, %lo(_gp_disp)
; NOLONGBRANCH-NEXT: beqz $4, $BB0_2
; NOLONGBRANCH-NEXT: addu $2, $2, $25
; NOLONGBRANCH-NEXT: # %bb.1: # %then
; NOLONGBRANCH-NEXT: lw $1, %got(x)($2)
; NOLONGBRANCH-NEXT: addiu $2, $zero, 1
; NOLONGBRANCH-NEXT: sw $2, 0($1)
; NOLONGBRANCH-NEXT: $BB0_2: # %end
; NOLONGBRANCH-NEXT: jr $ra
; NOLONGBRANCH-NEXT: nop
;
; O32-PIC-LABEL: test1:
; O32-PIC: # %bb.0: # %entry
; O32-PIC-NEXT: lui $2, %hi(_gp_disp)
; O32-PIC-NEXT: addiu $2, $2, %lo(_gp_disp)
; O32-PIC-NEXT: bnez $4, $BB0_3
; O32-PIC-NEXT: addu $2, $2, $25
; O32-PIC-NEXT: # %bb.1: # %entry
; O32-PIC-NEXT: addiu $sp, $sp, -8
; O32-PIC-NEXT: sw $ra, 0($sp)
; O32-PIC-NEXT: lui $1, %hi(($BB0_4)-($BB0_2))
; O32-PIC-NEXT: bal $BB0_2
; O32-PIC-NEXT: addiu $1, $1, %lo(($BB0_4)-($BB0_2))
; O32-PIC-NEXT: $BB0_2: # %entry
; O32-PIC-NEXT: addu $1, $ra, $1
; O32-PIC-NEXT: lw $ra, 0($sp)
; O32-PIC-NEXT: jr $1
; O32-PIC-NEXT: addiu $sp, $sp, 8
; O32-PIC-NEXT: $BB0_3: # %then
; O32-PIC-NEXT: lw $1, %got(x)($2)
; O32-PIC-NEXT: addiu $2, $zero, 1
; O32-PIC-NEXT: sw $2, 0($1)
; O32-PIC-NEXT: $BB0_4: # %end
; O32-PIC-NEXT: jr $ra
; O32-PIC-NEXT: nop
;
; O32-STATIC-LABEL: test1:
; O32-STATIC: # %bb.0: # %entry
; O32-STATIC-NEXT: bnez $4, $BB0_2
; O32-STATIC-NEXT: nop
; O32-STATIC-NEXT: # %bb.1: # %entry
; O32-STATIC-NEXT: j $BB0_3
; O32-STATIC-NEXT: nop
; O32-STATIC-NEXT: $BB0_2: # %then
; O32-STATIC-NEXT: lui $1, %hi(x)
; O32-STATIC-NEXT: addiu $2, $zero, 1
; O32-STATIC-NEXT: sw $2, %lo(x)($1)
; O32-STATIC-NEXT: $BB0_3: # %end
; O32-STATIC-NEXT: jr $ra
; O32-STATIC-NEXT: nop
;
; O32-R6-PIC-LABEL: test1:
; O32-R6-PIC: # %bb.0: # %entry
; O32-R6-PIC-NEXT: lui $2, %hi(_gp_disp)
; O32-R6-PIC-NEXT: addiu $2, $2, %lo(_gp_disp)
; O32-R6-PIC-NEXT: bnez $4, $BB0_3
; O32-R6-PIC-NEXT: addu $2, $2, $25
; O32-R6-PIC-NEXT: # %bb.1: # %entry
; O32-R6-PIC-NEXT: addiu $sp, $sp, -8
; O32-R6-PIC-NEXT: sw $ra, 0($sp)
; O32-R6-PIC-NEXT: lui $1, %hi(($BB0_4)-($BB0_2))
; O32-R6-PIC-NEXT: addiu $1, $1, %lo(($BB0_4)-($BB0_2))
; O32-R6-PIC-NEXT: balc $BB0_2
; O32-R6-PIC-NEXT: $BB0_2: # %entry
; O32-R6-PIC-NEXT: addu $1, $ra, $1
; O32-R6-PIC-NEXT: lw $ra, 0($sp)
; O32-R6-PIC-NEXT: addiu $sp, $sp, 8
; O32-R6-PIC-NEXT: jrc $1
; O32-R6-PIC-NEXT: $BB0_3: # %then
; O32-R6-PIC-NEXT: lw $1, %got(x)($2)
; O32-R6-PIC-NEXT: addiu $2, $zero, 1
; O32-R6-PIC-NEXT: sw $2, 0($1)
; O32-R6-PIC-NEXT: $BB0_4: # %end
; O32-R6-PIC-NEXT: jrc $ra
;
; O32-R6-STATIC-LABEL: test1:
; O32-R6-STATIC: # %bb.0: # %entry
; O32-R6-STATIC-NEXT: bnezc $4, $BB0_2
; O32-R6-STATIC-NEXT: nop
; O32-R6-STATIC-NEXT: # %bb.1: # %entry
; O32-R6-STATIC-NEXT: bc $BB0_3
; O32-R6-STATIC-NEXT: $BB0_2: # %then
; O32-R6-STATIC-NEXT: lui $1, %hi(x)
; O32-R6-STATIC-NEXT: addiu $2, $zero, 1
; O32-R6-STATIC-NEXT: sw $2, %lo(x)($1)
; O32-R6-STATIC-NEXT: $BB0_3: # %end
; O32-R6-STATIC-NEXT: jrc $ra
;
; MIPS4-LABEL: test1:
; MIPS4: # %bb.0: # %entry
; MIPS4-NEXT: lui $1, %hi(%neg(%gp_rel(test1)))
; MIPS4-NEXT: bnez $4, .LBB0_3
; MIPS4-NEXT: daddu $2, $1, $25
; MIPS4-NEXT: # %bb.1: # %entry
; MIPS4-NEXT: daddiu $sp, $sp, -16
; MIPS4-NEXT: sd $ra, 0($sp)
; MIPS4-NEXT: daddiu $1, $zero, %hi(.LBB0_4-.LBB0_2)
; MIPS4-NEXT: dsll $1, $1, 16
; MIPS4-NEXT: bal .LBB0_2
; MIPS4-NEXT: daddiu $1, $1, %lo(.LBB0_4-.LBB0_2)
; MIPS4-NEXT: .LBB0_2: # %entry
; MIPS4-NEXT: daddu $1, $ra, $1
; MIPS4-NEXT: ld $ra, 0($sp)
; MIPS4-NEXT: jr $1
; MIPS4-NEXT: daddiu $sp, $sp, 16
; MIPS4-NEXT: .LBB0_3: # %then
; MIPS4-NEXT: daddiu $1, $2, %lo(%neg(%gp_rel(test1)))
; MIPS4-NEXT: addiu $2, $zero, 1
; MIPS4-NEXT: ld $1, %got_disp(x)($1)
; MIPS4-NEXT: sw $2, 0($1)
; MIPS4-NEXT: .LBB0_4: # %end
; MIPS4-NEXT: jr $ra
; MIPS4-NEXT: nop
;
; MIPS64-LABEL: test1:
; MIPS64: # %bb.0: # %entry
; MIPS64-NEXT: lui $1, %hi(%neg(%gp_rel(test1)))
; MIPS64-NEXT: bnez $4, .LBB0_3
; MIPS64-NEXT: daddu $2, $1, $25
; MIPS64-NEXT: # %bb.1: # %entry
; MIPS64-NEXT: daddiu $sp, $sp, -16
; MIPS64-NEXT: sd $ra, 0($sp)
; MIPS64-NEXT: daddiu $1, $zero, %hi(.LBB0_4-.LBB0_2)
; MIPS64-NEXT: dsll $1, $1, 16
; MIPS64-NEXT: bal .LBB0_2
; MIPS64-NEXT: daddiu $1, $1, %lo(.LBB0_4-.LBB0_2)
; MIPS64-NEXT: .LBB0_2: # %entry
; MIPS64-NEXT: daddu $1, $ra, $1
; MIPS64-NEXT: ld $ra, 0($sp)
; MIPS64-NEXT: jr $1
; MIPS64-NEXT: daddiu $sp, $sp, 16
; MIPS64-NEXT: .LBB0_3: # %then
; MIPS64-NEXT: daddiu $1, $2, %lo(%neg(%gp_rel(test1)))
; MIPS64-NEXT: addiu $2, $zero, 1
; MIPS64-NEXT: ld $1, %got_disp(x)($1)
; MIPS64-NEXT: sw $2, 0($1)
; MIPS64-NEXT: .LBB0_4: # %end
; MIPS64-NEXT: jr $ra
; MIPS64-NEXT: nop
;
; N64-R6-LABEL: test1:
; N64-R6: # %bb.0: # %entry
; N64-R6-NEXT: lui $1, %hi(%neg(%gp_rel(test1)))
; N64-R6-NEXT: bnez $4, .LBB0_3
; N64-R6-NEXT: daddu $2, $1, $25
; N64-R6-NEXT: # %bb.1: # %entry
; N64-R6-NEXT: daddiu $sp, $sp, -16
; N64-R6-NEXT: sd $ra, 0($sp)
; N64-R6-NEXT: daddiu $1, $zero, %hi(.LBB0_4-.LBB0_2)
; N64-R6-NEXT: dsll $1, $1, 16
; N64-R6-NEXT: daddiu $1, $1, %lo(.LBB0_4-.LBB0_2)
; N64-R6-NEXT: balc .LBB0_2
; N64-R6-NEXT: .LBB0_2: # %entry
; N64-R6-NEXT: daddu $1, $ra, $1
; N64-R6-NEXT: ld $ra, 0($sp)
; N64-R6-NEXT: daddiu $sp, $sp, 16
; N64-R6-NEXT: jrc $1
; N64-R6-NEXT: .LBB0_3: # %then
; N64-R6-NEXT: daddiu $1, $2, %lo(%neg(%gp_rel(test1)))
; N64-R6-NEXT: addiu $2, $zero, 1
; N64-R6-NEXT: ld $1, %got_disp(x)($1)
; N64-R6-NEXT: sw $2, 0($1)
; N64-R6-NEXT: .LBB0_4: # %end
; N64-R6-NEXT: jrc $ra
;
; MICROMIPS-LABEL: test1:
; MICROMIPS: # %bb.0: # %entry
; MICROMIPS-NEXT: lui $2, %hi(_gp_disp)
; MICROMIPS-NEXT: addiu $2, $2, %lo(_gp_disp)
; MICROMIPS-NEXT: bnez $4, $BB0_3
; MICROMIPS-NEXT: addu $2, $2, $25
; MICROMIPS-NEXT: # %bb.1: # %entry
; MICROMIPS-NEXT: addiu $sp, $sp, -8
; MICROMIPS-NEXT: sw $ra, 0($sp)
; MICROMIPS-NEXT: lui $1, %hi(($BB0_4)-($BB0_2))
; MICROMIPS-NEXT: bal $BB0_2
; MICROMIPS-NEXT: addiu $1, $1, %lo(($BB0_4)-($BB0_2))
; MICROMIPS-NEXT: $BB0_2: # %entry
; MICROMIPS-NEXT: addu $1, $ra, $1
; MICROMIPS-NEXT: lw $ra, 0($sp)
; MICROMIPS-NEXT: jr $1
; MICROMIPS-NEXT: addiu $sp, $sp, 8
; MICROMIPS-NEXT: $BB0_3: # %then
; MICROMIPS-NEXT: lw $2, %got(x)($2)
; MICROMIPS-NEXT: li16 $3, 1
; MICROMIPS-NEXT: sw16 $3, 0($2)
; MICROMIPS-NEXT: $BB0_4: # %end
; MICROMIPS-NEXT: jrc $ra
;
; MICROMIPSSTATIC-LABEL: test1:
; MICROMIPSSTATIC: # %bb.0: # %entry
; MICROMIPSSTATIC-NEXT: bnezc $4, $BB0_2
; MICROMIPSSTATIC-NEXT: # %bb.1: # %entry
; MICROMIPSSTATIC-NEXT: j $BB0_3
; MICROMIPSSTATIC-NEXT: nop
[mips] Involves microMIPS's jump in the analyzable branch set Involves microMIPS's jump in the analyzable branch set to reduce some code patterns. Differential revision: https://reviews.llvm.org/D50613 llvm-svn: 340931
2018-08-29 22:53:55 +08:00
; MICROMIPSSTATIC-NEXT: $BB0_2: # %then
[mips] Add partial support for R6 in the long branch pass MIPSR6 introduced several new jump instructions and deprecated the use of the 'j' instruction. For microMIPS32R6, 'j' was removed entirely and it only has non delay slot jumps. This patch adds support for MIPSR6 by using some R6 instructions-- 'bc' instead of 'j', 'jic $reg, 0' instead of 'jalr $zero, $reg'-- and modifies the sequences not to use delay slots for R6. Reviewers: atanasyan Reviewed By: atanasyan Subscribers: dschuff, arichardson, llvm-commits Differential Revision: https://reviews.llvm.org/D40786 llvm-svn: 320703
2017-12-14 22:55:25 +08:00
; MICROMIPSSTATIC-NEXT: lui $1, %hi(x)
; MICROMIPSSTATIC-NEXT: li16 $2, 1
; MICROMIPSSTATIC-NEXT: sw $2, %lo(x)($1)
[mips] Involves microMIPS's jump in the analyzable branch set Involves microMIPS's jump in the analyzable branch set to reduce some code patterns. Differential revision: https://reviews.llvm.org/D50613 llvm-svn: 340931
2018-08-29 22:53:55 +08:00
; MICROMIPSSTATIC-NEXT: $BB0_3: # %end
[mips] Add partial support for R6 in the long branch pass MIPSR6 introduced several new jump instructions and deprecated the use of the 'j' instruction. For microMIPS32R6, 'j' was removed entirely and it only has non delay slot jumps. This patch adds support for MIPSR6 by using some R6 instructions-- 'bc' instead of 'j', 'jic $reg, 0' instead of 'jalr $zero, $reg'-- and modifies the sequences not to use delay slots for R6. Reviewers: atanasyan Reviewed By: atanasyan Subscribers: dschuff, arichardson, llvm-commits Differential Revision: https://reviews.llvm.org/D40786 llvm-svn: 320703
2017-12-14 22:55:25 +08:00
; MICROMIPSSTATIC-NEXT: jrc $ra
;
; MICROMIPSR6STATIC-LABEL: test1:
; MICROMIPSR6STATIC: # %bb.0: # %entry
; MICROMIPSR6STATIC-NEXT: bnezc $4, $BB0_2
; MICROMIPSR6STATIC-NEXT: # %bb.1: # %entry
; MICROMIPSR6STATIC-NEXT: bc $BB0_3
[mips] Analyze and provide selection patterns microMIPSR6 branches These branches were previously unanalyzable and unselectable. Add them and recognize how to generate their inverses. Reviewers: smaksimovic, atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D46113 llvm-svn: 331050
2018-04-27 23:49:49 +08:00
; MICROMIPSR6STATIC-NEXT: $BB0_2: # %then
[mips] Add partial support for R6 in the long branch pass MIPSR6 introduced several new jump instructions and deprecated the use of the 'j' instruction. For microMIPS32R6, 'j' was removed entirely and it only has non delay slot jumps. This patch adds support for MIPSR6 by using some R6 instructions-- 'bc' instead of 'j', 'jic $reg, 0' instead of 'jalr $zero, $reg'-- and modifies the sequences not to use delay slots for R6. Reviewers: atanasyan Reviewed By: atanasyan Subscribers: dschuff, arichardson, llvm-commits Differential Revision: https://reviews.llvm.org/D40786 llvm-svn: 320703
2017-12-14 22:55:25 +08:00
; MICROMIPSR6STATIC-NEXT: lui $1, %hi(x)
; MICROMIPSR6STATIC-NEXT: li16 $2, 1
; MICROMIPSR6STATIC-NEXT: sw $2, %lo(x)($1)
[mips] Analyze and provide selection patterns microMIPSR6 branches These branches were previously unanalyzable and unselectable. Add them and recognize how to generate their inverses. Reviewers: smaksimovic, atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D46113 llvm-svn: 331050
2018-04-27 23:49:49 +08:00
; MICROMIPSR6STATIC-NEXT: $BB0_3: # %end
[mips] Add partial support for R6 in the long branch pass MIPSR6 introduced several new jump instructions and deprecated the use of the 'j' instruction. For microMIPS32R6, 'j' was removed entirely and it only has non delay slot jumps. This patch adds support for MIPSR6 by using some R6 instructions-- 'bc' instead of 'j', 'jic $reg, 0' instead of 'jalr $zero, $reg'-- and modifies the sequences not to use delay slots for R6. Reviewers: atanasyan Reviewed By: atanasyan Subscribers: dschuff, arichardson, llvm-commits Differential Revision: https://reviews.llvm.org/D40786 llvm-svn: 320703
2017-12-14 22:55:25 +08:00
; MICROMIPSR6STATIC-NEXT: jrc $ra
;
; MICROMIPSR6PIC-LABEL: test1:
; MICROMIPSR6PIC: # %bb.0: # %entry
; MICROMIPSR6PIC-NEXT: lui $2, %hi(_gp_disp)
; MICROMIPSR6PIC-NEXT: addiu $2, $2, %lo(_gp_disp)
; MICROMIPSR6PIC-NEXT: addu $2, $2, $25
; MICROMIPSR6PIC-NEXT: bnezc $4, $BB0_3
; MICROMIPSR6PIC-NEXT: # %bb.1: # %entry
; MICROMIPSR6PIC-NEXT: addiu $sp, $sp, -8
; MICROMIPSR6PIC-NEXT: sw $ra, 0($sp)
; MICROMIPSR6PIC-NEXT: lui $1, %hi(($BB0_4)-($BB0_2))
; MICROMIPSR6PIC-NEXT: addiu $1, $1, %lo(($BB0_4)-($BB0_2))
; MICROMIPSR6PIC-NEXT: balc $BB0_2
; MICROMIPSR6PIC-NEXT: $BB0_2: # %entry
; MICROMIPSR6PIC-NEXT: addu $1, $ra, $1
; MICROMIPSR6PIC-NEXT: lw $ra, 0($sp)
; MICROMIPSR6PIC-NEXT: addiu $sp, $sp, 8
; MICROMIPSR6PIC-NEXT: jic $1, 0
; MICROMIPSR6PIC-NEXT: $BB0_3: # %then
; MICROMIPSR6PIC-NEXT: lw $2, %got(x)($2)
; MICROMIPSR6PIC-NEXT: li16 $3, 1
; MICROMIPSR6PIC-NEXT: sw16 $3, 0($2)
; MICROMIPSR6PIC-NEXT: $BB0_4: # %end
; MICROMIPSR6PIC-NEXT: jrc $ra
; NACL-LABEL: test1:
; NACL: # %bb.0:
; NACL-NEXT: lui $2, %hi(_gp_disp)
; NACL-NEXT: addiu $2, $2, %lo(_gp_disp)
; NACL-NEXT: bnez $4, $BB0_3
; NACL-NEXT: addu $2, $2, $25
; NACL-NEXT: # %bb.1:
; NACL-NEXT: addiu $sp, $sp, -8
; NACL-NEXT: sw $ra, 0($sp)
; NACL-NEXT: lui $1, %hi(($BB0_4)-($BB0_2))
; NACL-NEXT: bal $BB0_2
; NACL-NEXT: addiu $1, $1, %lo(($BB0_4)-($BB0_2))
; NACL-NEXT: $BB0_2:
; NACL-NEXT: addu $1, $ra, $1
; NACL-NEXT: lw $ra, 0($sp)
; NACL-NEXT: addiu $sp, $sp, 8
; NACL-NEXT: jr $1
; NACL-NEXT: nop
; NACL-NEXT: $BB0_3:
; NACL-NEXT: lw $1, %got(x)($2)
; NACL-NEXT: addiu $2, $zero, 1
; NACL-NEXT: sw $2, 0($1)
; NACL-NEXT: .p2align 4
; NACL-NEXT: $BB0_4:
; NACL-NEXT: jr $ra
; NACL-NEXT: nop
; Check the NaCl version. Check that sp change is not in the branch delay slot
; of "jr $1" instruction. Check that target of indirect branch "jr $1" is
; bundle aligned.
Test case for MIPS long branch pass. llvm-svn: 158438
2012-06-14 10:12:21 +08:00
entry:
[mips] Fix MipsLongBranch pass to work when the offset from the branch to the target cannot be determined accurately. This is the case for NaCl where the sandboxing instructions are added in MC layer, after the MipsLongBranch pass. It is also the case when the code has inline assembly. Instead of calculating offset in the MipsLongBranch pass, use %hi(sym1 - sym2) and %lo(sym1 - sym2) expressions that are resolved during the fixup. This patch also deletes microMIPS test file test/CodeGen/Mips/micromips-long-branch.ll and implements microMIPS CHECKs in a much simpler way in a file test/CodeGen/Mips/longbranch.ll, together with MIPS32 and MIPS64. llvm-svn: 207656
2014-04-30 23:06:25 +08:00
%cmp = icmp eq i32 %s, 0
br i1 %cmp, label %end, label %then
then:
store i32 1, i32* @x, align 4
br label %end
end:
Test case for MIPS long branch pass. llvm-svn: 158438
2012-06-14 10:12:21 +08:00
ret void
[mips] Fix MipsLongBranch pass to work when the offset from the branch to the target cannot be determined accurately. This is the case for NaCl where the sandboxing instructions are added in MC layer, after the MipsLongBranch pass. It is also the case when the code has inline assembly. Instead of calculating offset in the MipsLongBranch pass, use %hi(sym1 - sym2) and %lo(sym1 - sym2) expressions that are resolved during the fixup. This patch also deletes microMIPS test file test/CodeGen/Mips/micromips-long-branch.ll and implements microMIPS CHECKs in a much simpler way in a file test/CodeGen/Mips/longbranch.ll, together with MIPS32 and MIPS64. llvm-svn: 207656
2014-04-30 23:06:25 +08:00
}