forked from OSchip/llvm-project
34 lines
1.1 KiB
TableGen
34 lines
1.1 KiB
TableGen
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// RUN: llvm-tblgen -gen-register-info -I %p/../../include -I %p/Common %s | FileCheck %s
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include "reg-with-subregs-common.td"
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// CHECK-DAG: GPR32_AND_XR32RegClassID =
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// CHECK-DAG: XR32RegClassID =
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def X0 : Register <"x0">;
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// CHECK-LABEL: getRegPressureSetName(unsigned Idx) const {
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// CHECK-NEXT: static const char *const PressureNameTable[] = {
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// CHECK-NEXT: "GPR32",
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// CHECK-NEXT: };
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// CHECK-NEXT: return PressureNameTable[Idx];
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// CHECK-NEXT: }
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// CHECK: unsigned TestTargetGenRegisterInfo::
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// CHECK-NEXT: getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
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// CHECK-NEXT: static const uint16_t PressureLimitTable[] = {
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// CHECK-NEXT: {{[0-9]+}}, // 0: GPR32
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// CHECK-NEXT: };
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// CHECK-NEXT: return PressureLimitTable[Idx];
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// CHECK-NEXT:}
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// CHECK: static const int RCSetsTable[] = {
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// CHECK-NEXT: /* 0 */ 0, -1,
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// CHECK-NEXT: };
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def XR32 : RegisterClass<"TestTarget", [i32], 32, (add X0)> {
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let GeneratePressureSet = 0;
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}
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def GPR32_AND_XR32 : RegisterClass<"TestTarget", [i32], 32, (add GPR32, X0)>;
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