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llvm-project/llvm/test/CodeGen/Mips/micromips-delay-slot.ll

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[mips][microMIPS] Fix issue with delay slot filler and microMIPS Differential Revision: http://reviews.llvm.org/D6193 llvm-svn: 221612
2014-11-11 01:27:56 +08:00
; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \
[mips][micromips] Use call instructions with short delay slots Differential Revision: http://reviews.llvm.org/D6338 llvm-svn: 222752
2014-11-25 18:50:00 +08:00
; RUN: -relocation-model=static -O2 < %s | FileCheck %s
[mips][microMIPS] Delay slot filler modifications Differential Revision: http://reviews.llvm.org/D18181 llvm-svn: 264147
2016-03-23 18:29:38 +08:00
; RUN: llc -march=mipsel -mcpu=mips32r6 -mattr=+micromips \
; RUN: -relocation-model=static -O2 < %s | FileCheck %s -check-prefix=CHECK-MMR6
[mips][microMIPS] Fix issue with delay slot filler and microMIPS Differential Revision: http://reviews.llvm.org/D6193 llvm-svn: 221612
2014-11-11 01:27:56 +08:00
[mips][micromips] Use call instructions with short delay slots Differential Revision: http://reviews.llvm.org/D6338 llvm-svn: 222752
2014-11-25 18:50:00 +08:00
; Function Attrs: nounwind
define i32 @foo(i32 signext %a) #0 {
[mips][microMIPS] Fix issue with delay slot filler and microMIPS Differential Revision: http://reviews.llvm.org/D6193 llvm-svn: 221612
2014-11-11 01:27:56 +08:00
entry:
%a.addr = alloca i32, align 4
store i32 %a, i32* %a.addr, align 4
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%0 = load i32, i32* %a.addr, align 4
[mips][microMIPS] Fix issue with delay slot filler and microMIPS Differential Revision: http://reviews.llvm.org/D6193 llvm-svn: 221612
2014-11-11 01:27:56 +08:00
%shl = shl i32 %0, 2
[mips][micromips] Use call instructions with short delay slots Differential Revision: http://reviews.llvm.org/D6338 llvm-svn: 222752
2014-11-25 18:50:00 +08:00
%call = call i32 @bar(i32 signext %shl)
[mips][microMIPS] Fix issue with delay slot filler and microMIPS Differential Revision: http://reviews.llvm.org/D6193 llvm-svn: 221612
2014-11-11 01:27:56 +08:00
ret i32 %call
}
[mips][micromips] Use call instructions with short delay slots Differential Revision: http://reviews.llvm.org/D6338 llvm-svn: 222752
2014-11-25 18:50:00 +08:00
declare i32 @bar(i32 signext) #1
[mips][microMIPS] Fix issue with delay slot filler and microMIPS Differential Revision: http://reviews.llvm.org/D6193 llvm-svn: 221612
2014-11-11 01:27:56 +08:00
[mips][micromips] Use call instructions with short delay slots Differential Revision: http://reviews.llvm.org/D6338 llvm-svn: 222752
2014-11-25 18:50:00 +08:00
; CHECK: jals
; CHECK-NEXT: sll16
[mips] Fix JmpLink to texternalsym and tglobaladdr on mcroMIPS R6 There is not match for the `MipsJmpLink texternalsym` and `MipsJmpLink tglobaladdr` patterns for microMIPS R6. As a result LLVM incorrectly selects the `JALRC16` compact 2-byte instruction which takes a target instruction address from a register only and assign `R_MIPS_32` relocation for this instruction. This relocation completely overwrites `JALRC16` and nearby instructions. This patch adds missed matching patterns, selects `BALC` instruction and assign a correct `R_MICROMIPS_PC26_S1` relocation. Differential Revision: https://reviews.llvm.org/D64552 llvm-svn: 365870
2019-07-12 12:58:45 +08:00
; CHECK-MMR6: balc
[mips][microMIPS] Delay slot filler modifications Differential Revision: http://reviews.llvm.org/D18181 llvm-svn: 264147
2016-03-23 18:29:38 +08:00
; CHECK-MMR6-NOT: sll16