forked from OSchip/llvm-project
31 lines
793 B
LLVM
31 lines
793 B
LLVM
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; RUN: llc -O2 -march=hexagon < %s | FileCheck %s
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; Hexagon's vsplatb/vsplath only consider the lower 8/16 bits of the source
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; register. Any extension of the source is not necessary.
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; CHECK-NOT: zxtb
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; CHECK-NOT: zxth
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target triple = "hexagon"
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; Function Attrs: nounwind readnone
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define i64 @f0(i64 %a0) #0 {
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b0:
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%v0 = trunc i64 %a0 to i32
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%v1 = and i32 %v0, 65535
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%v2 = tail call i64 @llvm.hexagon.S2.vsplatrh(i32 %v1)
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%v3 = and i32 %v0, 255
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%v4 = tail call i32 @llvm.hexagon.S2.vsplatrb(i32 %v3)
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%v5 = sext i32 %v4 to i64
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%v6 = add nsw i64 %v5, %v2
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ret i64 %v6
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}
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; Function Attrs: nounwind readnone
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declare i64 @llvm.hexagon.S2.vsplatrh(i32) #0
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; Function Attrs: nounwind readnone
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declare i32 @llvm.hexagon.S2.vsplatrb(i32) #0
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attributes #0 = { nounwind readnone }
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