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llvm-project/llvm/test/CodeGen/Hexagon/newvaluejump-kill2.mir

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[Hexagon] Update kills in hexagon-nvj even more properly than before Account for the fact that both, the feeder and the compare can be moved over instructions that kill registers. llvm-svn: 306443
2017-06-28 02:37:16 +08:00
# RUN: llc -march=hexagon -run-pass hexagon-nvj -verify-machineinstrs %s -o - | FileCheck %s
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-02-01 06:04:26 +08:00
# CHECK: J4_cmpgtu_t_jumpnv_t killed $r3, killed $r1, %bb.1, implicit-def $pc
[Hexagon] Update kills in hexagon-nvj even more properly than before Account for the fact that both, the feeder and the compare can be moved over instructions that kill registers. llvm-svn: 306443
2017-06-28 02:37:16 +08:00
---
name: fred
tracksRegLiveness: true
body: |
bb.0:
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-02-01 06:04:26 +08:00
liveins: $r0
$r1 = A2_addi $r0, -1
$r2 = A2_tfrsi -1431655765
$r3 = A2_tfrsi 2
$p0 = C2_cmpgtu killed $r3, $r1
$r2 = S4_subaddi killed $r1, 1, killed $r2
J2_jumpt killed $p0, %bb.1, implicit-def $pc
[Hexagon] Update kills in hexagon-nvj even more properly than before Account for the fact that both, the feeder and the compare can be moved over instructions that kill registers. llvm-svn: 306443
2017-06-28 02:37:16 +08:00
bb.1:
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