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llvm-project/llvm/test/CodeGen/ARM/2012-08-04-DtripleSpillRelo...

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Add stack spill / reload instructions for DTriple and DQuad register classes, which were missed for no reason. This fixes PR13377 llvm-svn: 161299
2012-08-04 21:16:12 +08:00
; RUN: llc < %s
; PR13377
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:64-n32-S64"
target triple = "armv7-none-linux-gnueabi"
%0 = type { <4 x float> }
define arm_aapcs_vfpcc void @foo(float, i1 zeroext, i1 zeroext) nounwind uwtable {
br i1 undef, label %4, label %5
; <label>:4 ; preds = %3
unreachable
; <label>:5 ; preds = %3
br i1 undef, label %7, label %6
; <label>:6 ; preds = %5
unreachable
; <label>:7 ; preds = %5
br i1 undef, label %8, label %10
; <label>:8 ; preds = %7
br i1 undef, label %9, label %10
; <label>:9 ; preds = %8
br i1 undef, label %11, label %10
; <label>:10 ; preds = %9, %8, %7
unreachable
; <label>:11 ; preds = %9
br i1 undef, label %13, label %12
; <label>:12 ; preds = %11
unreachable
; <label>:13 ; preds = %11
br i1 undef, label %15, label %14
; <label>:14 ; preds = %13
unreachable
; <label>:15 ; preds = %13
br i1 undef, label %18, label %16
; <label>:16 ; preds = %15
br i1 undef, label %17, label %18
; <label>:17 ; preds = %16
unreachable
; <label>:18 ; preds = %16, %15
br i1 undef, label %68, label %19
; <label>:19 ; preds = %18
br label %20
; <label>:20 ; preds = %20, %19
br i1 undef, label %21, label %20
; <label>:21 ; preds = %20
br i1 undef, label %22, label %68
; <label>:22 ; preds = %21
br i1 undef, label %23, label %24
; <label>:23 ; preds = %22
unreachable
; <label>:24 ; preds = %22
br i1 undef, label %26, label %25
; <label>:25 ; preds = %24
unreachable
; <label>:26 ; preds = %24
br i1 undef, label %28, label %27
; <label>:27 ; preds = %26
unreachable
; <label>:28 ; preds = %26
br i1 undef, label %29, label %30, !prof !0
; <label>:29 ; preds = %28
br label %30
; <label>:30 ; preds = %29, %28
br i1 undef, label %31, label %32, !prof !0
; <label>:31 ; preds = %30
br label %32
; <label>:32 ; preds = %31, %30
br i1 undef, label %34, label %33
; <label>:33 ; preds = %32
unreachable
; <label>:34 ; preds = %32
br i1 undef, label %35, label %36, !prof !0
; <label>:35 ; preds = %34
br label %36
; <label>:36 ; preds = %35, %34
br i1 undef, label %37, label %38, !prof !0
; <label>:37 ; preds = %36
br label %38
; <label>:38 ; preds = %37, %36
br i1 undef, label %39, label %67
; <label>:39 ; preds = %38
br i1 undef, label %40, label %41
; <label>:40 ; preds = %39
br i1 undef, label %64, label %41
; <label>:41 ; preds = %40, %39
br i1 undef, label %64, label %42
; <label>:42 ; preds = %41
%43 = fadd <4 x float> undef, undef
%44 = fadd <4 x float> undef, undef
%45 = fmul <4 x float> undef, undef
%46 = fmul <4 x float> %45, %43
%47 = fmul <4 x float> undef, %44
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%48 = load <4 x float>, <4 x float>* undef, align 8
Add stack spill / reload instructions for DTriple and DQuad register classes, which were missed for no reason. This fixes PR13377 llvm-svn: 161299
2012-08-04 21:16:12 +08:00
%49 = bitcast <4 x float> %48 to <2 x i64>
%50 = shufflevector <2 x i64> %49, <2 x i64> undef, <1 x i32> <i32 1>
%51 = bitcast <1 x i64> %50 to <2 x float>
%52 = shufflevector <2 x float> %51, <2 x float> undef, <4 x i32> zeroinitializer
%53 = bitcast <4 x float> %52 to <2 x i64>
%54 = shufflevector <2 x i64> %53, <2 x i64> undef, <1 x i32> zeroinitializer
%55 = bitcast <1 x i64> %54 to <2 x float>
%56 = extractelement <2 x float> %55, i32 0
%57 = insertelement <4 x float> undef, float %56, i32 2
%58 = insertelement <4 x float> %57, float 1.000000e+00, i32 3
%59 = fsub <4 x float> %47, %58
%60 = fmul <4 x float> undef, undef
%61 = fmul <4 x float> %59, %60
%62 = fmul <4 x float> %61, <float 6.000000e+01, float 6.000000e+01, float 6.000000e+01, float 6.000000e+01>
%63 = fadd <4 x float> %47, %62
TBAA: remove !tbaa from testing cases if not used. This will make it easier to turn on struct-path aware TBAA since the metadata format will change. llvm-svn: 180745
2013-04-30 06:58:55 +08:00
store <4 x float> %46, <4 x float>* undef, align 8
Add stack spill / reload instructions for DTriple and DQuad register classes, which were missed for no reason. This fixes PR13377 llvm-svn: 161299
2012-08-04 21:16:12 +08:00
call arm_aapcs_vfpcc void @bar(%0* undef, float 0.000000e+00) nounwind
call arm_aapcs_vfpcc void @bar(%0* undef, float 0.000000e+00) nounwind
TBAA: remove !tbaa from testing cases if not used. This will make it easier to turn on struct-path aware TBAA since the metadata format will change. llvm-svn: 180745
2013-04-30 06:58:55 +08:00
store <4 x float> %63, <4 x float>* undef, align 8
Add stack spill / reload instructions for DTriple and DQuad register classes, which were missed for no reason. This fixes PR13377 llvm-svn: 161299
2012-08-04 21:16:12 +08:00
unreachable
; <label>:64 ; preds = %41, %40
br i1 undef, label %65, label %66
; <label>:65 ; preds = %64
unreachable
; <label>:66 ; preds = %64
unreachable
; <label>:67 ; preds = %38
unreachable
; <label>:68 ; preds = %21, %18
ret void
}
declare arm_aapcs_vfpcc void @bar(%0*, float)
IR: Make metadata typeless in assembly Now that `Metadata` is typeless, reflect that in the assembly. These are the matching assembly changes for the metadata/value split in r223802. - Only use the `metadata` type when referencing metadata from a call intrinsic -- i.e., only when it's used as a `Value`. - Stop pretending that `ValueAsMetadata` is wrapped in an `MDNode` when referencing it from call intrinsics. So, assembly like this: define @foo(i32 %v) { call void @llvm.foo(metadata !{i32 %v}, metadata !0) call void @llvm.foo(metadata !{i32 7}, metadata !0) call void @llvm.foo(metadata !1, metadata !0) call void @llvm.foo(metadata !3, metadata !0) call void @llvm.foo(metadata !{metadata !3}, metadata !0) ret void, !bar !2 } !0 = metadata !{metadata !2} !1 = metadata !{i32* @global} !2 = metadata !{metadata !3} !3 = metadata !{} turns into this: define @foo(i32 %v) { call void @llvm.foo(metadata i32 %v, metadata !0) call void @llvm.foo(metadata i32 7, metadata !0) call void @llvm.foo(metadata i32* @global, metadata !0) call void @llvm.foo(metadata !3, metadata !0) call void @llvm.foo(metadata !{!3}, metadata !0) ret void, !bar !2 } !0 = !{!2} !1 = !{i32* @global} !2 = !{!3} !3 = !{} I wrote an upgrade script that handled almost all of the tests in llvm and many of the tests in cfe (even handling many `CHECK` lines). I've attached it (or will attach it in a moment if you're speedy) to PR21532 to help everyone update their out-of-tree testcases. This is part of PR21532. llvm-svn: 224257
2014-12-16 03:07:53 +08:00
!0 = !{!"branch_weights", i32 64, i32 4}