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llvm-project/llvm/test/MC/Mips/mips64r2/valid.s

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[mips] Added a full set of instruction test cases for all ISA's (but not ASE's). Summary: Where those ISA's are not currently supported, the test is run with the smallest superset of that ISA. Some instructions are valid but don't pass yet. These have been placed in the valid-xfail.s's which will XPASS if _any_ instruction starts working. The valid.s's do not verify the encoding yet. There are also no tests checking that instructions from neighbouring ISA's are not accepted. Reviewers: matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3214 llvm-svn: 205180
2014-03-31 20:13:12 +08:00
# Instructions that are valid
#
[mips] Correct the predicates for special nops, tlb ctrl instrs, software breakpoint and prefx. Reviewers: atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D44436 llvm-svn: 329905
2018-04-12 20:37:02 +08:00
# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -show-inst -mcpu=mips64r2 | FileCheck %s
[mips] [IAS] Remove AssemblerPredicate's from RelocPIC and RelocStatic. Summary: These AssemblerPredicate's are unnecessary and actually make some instructions unusable when assembling pre-MIPS32 ISAs. For example, this was causing the IAS to reject the 'j' instruction for MIPS I-V. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8300 llvm-svn: 234398
2015-04-08 18:06:45 +08:00
a:
[mips] Added a full set of instruction test cases for all ISA's (but not ASE's). Summary: Where those ISA's are not currently supported, the test is run with the smallest superset of that ISA. Some instructions are valid but don't pass yet. These have been placed in the valid-xfail.s's which will XPASS if _any_ instruction starts working. The valid.s's do not verify the encoding yet. There are also no tests checking that instructions from neighbouring ISA's are not accepted. Reviewers: matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3214 llvm-svn: 205180
2014-03-31 20:13:12 +08:00
.set noat
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
abs.d $f7,$f25 # CHECK: encoding:
abs.s $f9,$f16
add $s7,$s2,$a1
[mips] Marked the ADDi instruction aliases as not available in Mips32R6 and Mips64R6. Patch by Vasileios Kalintiris. Differential Revision: http://reviews.llvm.org/D5242 llvm-svn: 217867
2014-09-16 17:26:09 +08:00
add $9,$14,15176 # CHECK: addi $9, $14, 15176 # encoding: [0x21,0xc9,0x3b,0x48]
add $24,-7193 # CHECK: addi $24, $24, -7193 # encoding: [0x23,0x18,0xe3,0xe7]
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
add.d $f1,$f7,$f29
[mips] Implement add.ps, mul.ps and sub.ps Differential revision: https://reviews.llvm.org/D90321
2020-10-30 15:57:22 +08:00
add.ps $f25,$f27,$f13 # CHECK: add.ps $f25, $f27, $f13 # encoding: [0x46,0xcd,0xde,0x40]
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
add.s $f8,$f21,$f24
addi $13,$9,26322
[mips] Update MipsAsmParser so that it's possible to handle immediates that start with the binary operator NOT (~). Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D4158 llvm-svn: 211163
2014-06-18 21:55:18 +08:00
addi $8,$8,~1 # CHECK: addi $8, $8, -2 # encoding: [0x21,0x08,0xff,0xfe]
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
addu $9,$a0,$a2
[mips] Move 32-bit ADDiu instruction alias from Mips64InstrInfo.td to MipsInstrInfo.td. Patch by Vasileios Kalintiris. Differential Revision: http://reviews.llvm.org/D5244 llvm-svn: 217868
2014-09-16 18:19:03 +08:00
addu $9,10 # CHECK: addiu $9, $9, 10 # encoding: [0x25,0x29,0x00,0x0a]
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
and $s7,$v0,$12
[mips] Implement alias for 'and' and 'or' instructions for all ISAs. Summary: Examples: and $2, 4 <=> andi $2, $2, 4 or $2, 4 <=> ori $2, $2, 4 Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D4155 llvm-svn: 211161
2014-06-18 21:30:57 +08:00
and $2,4 # CHECK: andi $2, $2, 4 # encoding: [0x30,0x42,0x00,0x04]
[mips][mips64r6] bc1[tf] are not available on MIPS32r6/MIPS64r6 Summary: Also tightened up the acceptable condition operand for these instructions on MIPS-I to MIPS-III. Support for $fcc[1-7] was added in MIPS-IV. Prior to that only $fcc0 is acceptable. We currently don't optimize (BEQZ (NOT $a), $target) and similar. It's probably best to do this in InstCombine. Depends on D4111 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4112 llvm-svn: 210787
2014-06-12 23:00:17 +08:00
bc1f $fcc0, 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01]
bc1f $fcc1, 4 # CHECK: bc1f $fcc1, 4 # encoding: [0x45,0x04,0x00,0x01]
bc1f 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01]
[mips] Add support for COP1's Branch-On-Cond-Likely instructions Summary: Depends on D5782 Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5802 llvm-svn: 220042
2014-10-17 22:08:28 +08:00
bc1fl $fcc0,4688 # CHECK: bc1fl 4688 # encoding: [0x45,0x02,0x04,0x94]
bc1fl 4688 # CHECK: bc1fl 4688 # encoding: [0x45,0x02,0x04,0x94]
bc1fl $fcc7,27 # CHECK: bc1fl $fcc7, 27 # encoding: [0x45,0x1e,0x00,0x06]
[mips][mips64r6] bc1[tf] are not available on MIPS32r6/MIPS64r6 Summary: Also tightened up the acceptable condition operand for these instructions on MIPS-I to MIPS-III. Support for $fcc[1-7] was added in MIPS-IV. Prior to that only $fcc0 is acceptable. We currently don't optimize (BEQZ (NOT $a), $target) and similar. It's probably best to do this in InstCombine. Depends on D4111 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4112 llvm-svn: 210787
2014-06-12 23:00:17 +08:00
bc1t $fcc0, 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01]
bc1t $fcc1, 4 # CHECK: bc1t $fcc1, 4 # encoding: [0x45,0x05,0x00,0x01]
bc1t 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01]
[mips] Add support for COP1's Branch-On-Cond-Likely instructions Summary: Depends on D5782 Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5802 llvm-svn: 220042
2014-10-17 22:08:28 +08:00
bc1tl $fcc0,4688 # CHECK: bc1tl 4688 # encoding: [0x45,0x03,0x04,0x94]
bc1tl 4688 # CHECK: bc1tl 4688 # encoding: [0x45,0x03,0x04,0x94]
bc1tl $fcc7,27 # CHECK: bc1tl $fcc7, 27 # encoding: [0x45,0x1f,0x00,0x06]
[mips][mips64r6] b(ge|lt)zal are not available on MIPS32r6/MIPS64r6 and bal is a normal instruction Summary: b(ge|lt)zal have been removed in MIPS32r6/MIPS64r6. However, bal (an alias for 'bgezal $zero, $offset') still remains with the same encoding it had prior to MIPS32r6/MIPS64r6. Updated the MipsNaCLELFStreamer, and MipsLongBranch to correctly handle the MIPS32r6/MIPS64r6 BAL instruction in addition to the existing BAL_BR pseudo. No changes were required to the CodeGen test that looks for BAL (test/CodeGen/Mips/longbranch.ll) since the new instruction has the same syntax. Depends on D4113 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4114 llvm-svn: 210898
2014-06-13 21:02:52 +08:00
bal 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b]
bgezal $0, 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b]
bgezal $6, 21100 # CHECK: bgezal $6, 21100 # encoding: [0x04,0xd1,0x14,0x9b]
bltzal $6, 21100 # CHECK: bltzal $6, 21100 # encoding: [0x04,0xd0,0x14,0x9b]
[mips] Add support for COP0's Branch-On-Cond-Likely instructions Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5782 llvm-svn: 220036
2014-10-17 20:38:35 +08:00
beql $14,$s3,12544 # CHECK: beql $14, $19, 12544 # encoding: [0x51,0xd3,0x0c,0x40]
bgezall $12,7293 # CHECK: bgezall $12, 7293 # encoding: [0x05,0x93,0x07,0x1f]
bgezl $4,-6858 # CHECK: bgezl $4, -6858 # encoding: [0x04,0x83,0xf9,0x4d]
bgtzl $10,-3738 # CHECK: bgtzl $10, -3738 # encoding: [0x5d,0x40,0xfc,0x59]
blezl $6,2974 # CHECK: blezl $6, 2974 # encoding: [0x58,0xc0,0x02,0xe7]
bltzall $6,488 # CHECK: bltzall $6, 488 # encoding: [0x04,0xd2,0x00,0x7a]
bltzl $s1,-9964 # CHECK: bltzl $17, -9964 # encoding: [0x06,0x22,0xf6,0x45]
bnel $gp,$s4,5107 # CHECK: bnel $gp, $20, 5107 # encoding: [0x57,0x94,0x04,0xfc]
[mips] Added support for various EVA ASE instructions. Summary: Added support for the following instructions: CACHEE, LBE, LBUE, LHE, LHUE, LWE, LLE, LWLE, LWRE, PREFE, SBE, SHE, SWE, SCE, SWLE, SWRE, TLBINV, TLBINVF This required adding some infrastructure for the EVA ASE. Patch by Scott Egerton. Reviewers: vkalintiris, dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11139 llvm-svn: 247669
2015-09-15 18:02:16 +08:00
cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0xbc,0xa1,0x00,0x08]
[mips] Correct c.cond.fmt instruction definition. Permit explicit $fcc<X> operand in c.cond.fmt instruction. Add c.cond.fmt to the MIPS to microMIPS instruction mapping table. Check that $fcc1 - $fcc7 are unusable for MIPS-I to MIPS-III for c.cond.fmt, bc1t, bc1f. Reviewers: seanbruno, zoran.jovanovic, vkalintiris Differential Revision: https://reviews.llvm.org/D24510 llvm-svn: 292117
2017-01-16 21:55:58 +08:00
c.eq.d $fcc1, $f14, $f14 # CHECK: c.eq.d $fcc1, $f14, $f14 # encoding: [0x46,0x2e,0x71,0x32]
c.eq.s $fcc5, $f24, $f17 # CHECK: c.eq.s $fcc5, $f24, $f17 # encoding: [0x46,0x11,0xc5,0x32]
c.f.d $fcc4, $f10, $f20 # CHECK: c.f.d $fcc4, $f10, $f20 # encoding: [0x46,0x34,0x54,0x30]
c.f.s $fcc4, $f30, $f7 # CHECK: c.f.s $fcc4, $f30, $f7 # encoding: [0x46,0x07,0xf4,0x30]
c.le.d $fcc4, $f18, $f0 # CHECK: c.le.d $fcc4, $f18, $f0 # encoding: [0x46,0x20,0x94,0x3e]
c.le.s $fcc6, $f24, $f4 # CHECK: c.le.s $fcc6, $f24, $f4 # encoding: [0x46,0x04,0xc6,0x3e]
c.lt.d $fcc3, $f8, $f2 # CHECK: c.lt.d $fcc3, $f8, $f2 # encoding: [0x46,0x22,0x43,0x3c]
c.lt.s $fcc2, $f17, $f14 # CHECK: c.lt.s $fcc2, $f17, $f14 # encoding: [0x46,0x0e,0x8a,0x3c]
c.nge.d $fcc5, $f20, $f16 # CHECK: c.nge.d $fcc5, $f20, $f16 # encoding: [0x46,0x30,0xa5,0x3d]
c.nge.s $fcc3, $f11, $f8 # CHECK: c.nge.s $fcc3, $f11, $f8 # encoding: [0x46,0x08,0x5b,0x3d]
c.ngl.s $fcc2, $f31, $f23 # CHECK: c.ngl.s $fcc2, $f31, $f23 # encoding: [0x46,0x17,0xfa,0x3b]
c.ngle.s $fcc2, $f18, $f23 # CHECK: c.ngle.s $fcc2, $f18, $f23 # encoding: [0x46,0x17,0x92,0x39]
c.ngl.d $f28, $f28 # CHECK: c.ngl.d $f28, $f28 # encoding: [0x46,0x3c,0xe0,0x3b]
c.ngle.d $f0, $f16 # CHECK: c.ngle.d $f0, $f16 # encoding: [0x46,0x30,0x00,0x39]
c.ngt.d $fcc4, $f24, $f6 # CHECK: c.ngt.d $fcc4, $f24, $f6 # encoding: [0x46,0x26,0xc4,0x3f]
c.ngt.s $fcc5, $f8, $f13 # CHECK: c.ngt.s $fcc5, $f8, $f13 # encoding: [0x46,0x0d,0x45,0x3f]
c.ole.d $fcc2, $f16, $f30 # CHECK: c.ole.d $fcc2, $f16, $f30 # encoding: [0x46,0x3e,0x82,0x36]
c.ole.s $fcc3, $f7, $f20 # CHECK: c.ole.s $fcc3, $f7, $f20 # encoding: [0x46,0x14,0x3b,0x36]
c.olt.d $fcc4, $f18, $f28 # CHECK: c.olt.d $fcc4, $f18, $f28 # encoding: [0x46,0x3c,0x94,0x34]
c.olt.s $fcc6, $f20, $f7 # CHECK: c.olt.s $fcc6, $f20, $f7 # encoding: [0x46,0x07,0xa6,0x34]
c.seq.d $fcc4, $f30, $f6 # CHECK: c.seq.d $fcc4, $f30, $f6 # encoding: [0x46,0x26,0xf4,0x3a]
c.seq.s $fcc7, $f1, $f25 # CHECK: c.seq.s $fcc7, $f1, $f25 # encoding: [0x46,0x19,0x0f,0x3a]
c.sf.d $f30, $f0 # CHECK: c.sf.d $f30, $f0 # encoding: [0x46,0x20,0xf0,0x38]
c.sf.s $f14, $f22 # CHECK: c.sf.s $f14, $f22 # encoding: [0x46,0x16,0x70,0x38]
c.ueq.d $fcc4, $f12, $f24 # CHECK: c.ueq.d $fcc4, $f12, $f24 # encoding: [0x46,0x38,0x64,0x33]
c.ueq.s $fcc6, $f3, $f30 # CHECK: c.ueq.s $fcc6, $f3, $f30 # encoding: [0x46,0x1e,0x1e,0x33]
c.ule.d $fcc7, $f24, $f18 # CHECK: c.ule.d $fcc7, $f24, $f18 # encoding: [0x46,0x32,0xc7,0x37]
c.ule.s $fcc7, $f21, $f30 # CHECK: c.ule.s $fcc7, $f21, $f30 # encoding: [0x46,0x1e,0xaf,0x37]
c.ult.d $fcc6, $f6, $f16 # CHECK: c.ult.d $fcc6, $f6, $f16 # encoding: [0x46,0x30,0x36,0x35]
c.ult.s $fcc7, $f24, $f10 # CHECK: c.ult.s $fcc7, $f24, $f10 # encoding: [0x46,0x0a,0xc7,0x35]
c.un.d $fcc6, $f22, $f24 # CHECK: c.un.d $fcc6, $f22, $f24 # encoding: [0x46,0x38,0xb6,0x31]
c.un.s $fcc1, $f30, $f4 # CHECK: c.un.s $fcc1, $f30, $f4 # encoding: [0x46,0x04,0xf1,0x31]
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
ceil.l.d $f1,$f3
ceil.l.s $f18,$f13
[mips] Fix the predicates of round, ceiling, floor and trunc. Reviewers: atanasyan, abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D46691 llvm-svn: 332258
2018-05-15 00:26:50 +08:00
ceil.w.d $f11,$f25 # CHECK: ceil.w.d $f11, $f25 # encoding: [0x46,0x20,0xca,0xce]
# CHECK: # <MCInst #{{.*}} CEIL_W_D64
ceil.w.s $f6,$f20 # CHECK: ceil.w.s $f6, $f20 # encoding: [0x46,0x00,0xa1,0x8e]
# CHECK: # <MCInst #{{.*}} CEIL_W_S
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
cfc1 $s1,$21
[mips][mips64r6] cl[oz], and dcl[oz] are re-encoded in MIPS32r6/MIPS64r6 Summary: There is no change to the restrictions, just the result register is stored once in the encoding rather than twice. The rt field is zero in MIPS32r6/MIPS64r6. Depends on D4119 Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4120 llvm-svn: 211019
2014-06-16 21:18:59 +08:00
clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x70,0xab,0x58,0x21]
clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x73,0x9d,0xe8,0x20]
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
ctc1 $a2,$26
[mips] Correct the predicates of cvt.fmt.fmt instructions Reviewers: atanasyan, smaksimovic, abeserminji Differential Revision: https://reviews.llvm.org/D46390 llvm-svn: 331969
2018-05-10 18:42:30 +08:00
cvt.d.l $f4,$f16 # CHECK: cvt.d.l $f4, $f16 # encoding: [0x46,0xa0,0x81,0x21]
# CHECK: # <MCInst #{{[0-9]+}} CVT_D64_L
cvt.d.s $f22,$f28 # CHECK: cvt.d.s $f22, $f28 # encoding: [0x46,0x00,0xe5,0xa1]
# CHECK: # <MCInst #{{[0-9]+}} CVT_D64_S
cvt.d.w $f26,$f11 # CHECK: cvt.d.w $f26, $f11 # encoding: [0x46,0x80,0x5e,0xa1]
# CHECK: # <MCInst #{{[0-9]+}} CVT_D64_W
cvt.l.d $f24,$f15 # CHECK: cvt.l.d $f24, $f15 # encoding: [0x46,0x20,0x7e,0x25]
# CHECK: # <MCInst #{{[0-9]+}} CVT_L_D64
cvt.l.s $f11,$f29 # CHECK: cvt.l.s $f11, $f29 # encoding: [0x46,0x00,0xea,0xe5]
# CHECK: # <MCInst #{{[0-9]+}} CVT_L_S
cvt.s.d $f26,$f8 # CHECK: cvt.s.d $f26, $f8 # encoding: [0x46,0x20,0x46,0xa0]
# CHECK: # <MCInst #{{[0-9]+}} CVT_S_D64
cvt.s.l $f15,$f30 # CHECK: cvt.s.l $f15, $f30 # encoding: [0x46,0xa0,0xf3,0xe0]
# CHECK: # <MCInst #{{[0-9]+}} CVT_S_L
cvt.s.w $f22,$f15 # CHECK: cvt.s.w $f22, $f15 # encoding: [0x46,0x80,0x7d,0xa0]
# CHECK: # <MCInst #{{[0-9]+}} CVT_S_W
cvt.w.d $f20,$f14 # CHECK: cvt.w.d $f20, $f14 # encoding: [0x46,0x20,0x75,0x24]
# CHECK: # <MCInst #{{[0-9]+}} CVT_W_D64
cvt.w.s $f20,$f24 # CHECK: cvt.w.s $f20, $f24 # encoding: [0x46,0x00,0xc5,0x24]
# CHECK: # <MCInst #{{[0-9]+}} CVT_W_S
[mips] Add missing instructions Add pll.ps, plu.ps, cvt.s.pu, cvt.s.pl, cvt.ps instructions for FP64. Differential Revision: https://reviews.llvm.org/D50437 llvm-svn: 340920
2018-08-29 19:35:03 +08:00
cvt.ps.s $f4,$f18,$f20 # CHECK: cvt.ps.s $f4, $f18, $f20 # encoding: [0x46,0x14,0x91,0x26]
# CHECK: # <MCInst #{{[0-9]+}} CVT_PS_S64
cvt.s.pl $f30,$f2 # CHECK: cvt.s.pl $f30, $f2 # encoding: [0x46,0xc0,0x17,0xa8]
# CHECK: # <MCInst #{{[0-9]+}} CVT_S_PL64
cvt.s.pu $f14,$f26 # CHECK: cvt.s.pu $f14, $f26 # encoding: [0x46,0xc0,0xd3,0xa0]
# CHECK: # <MCInst #{{[0-9]+}} CVT_S_PU64
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
dadd $s3,$at,$ra
[mips][mips64r6] daddi is not available on MIPS64r6 Summary: It's not emitted by the code generator so we only need assembler tests. Also added missing daddi aliases from dsub mnemonics, and removed a couple duplicate dsub tests. Depends on D4112 Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4113 llvm-svn: 210897
2014-06-13 20:49:06 +08:00
dadd $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7]
dadd $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7]
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
daddi $sp,$s4,-27705
[mips][mips64r6] daddi is not available on MIPS64r6 Summary: It's not emitted by the code generator so we only need assembler tests. Also added missing daddi aliases from dsub mnemonics, and removed a couple duplicate dsub tests. Depends on D4112 Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4113 llvm-svn: 210897
2014-06-13 20:49:06 +08:00
daddi $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7]
daddi $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7]
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
daddiu $k0,$s6,-4586
[mips] Added missing daddu test to the valid instruction tests. Summary: Depends on D3673 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3674 llvm-svn: 208398
2014-05-09 17:32:01 +08:00
daddu $s3,$at,$ra
[mips] Marked the DADDiu instruction aliases as MIPS III. Patch by Vasileios Kalintiris. Differential Revision: http://reviews.llvm.org/D5239 llvm-svn: 217770
2014-09-15 22:47:46 +08:00
daddu $24,$2,18079 # CHECK: daddiu $24, $2, 18079 # encoding: [0x64,0x58,0x46,0x9f]
daddu $19,26943 # CHECK: daddiu $19, $19, 26943 # encoding: [0x66,0x73,0x69,0x3f]
[mips][mips64r6] cl[oz], and dcl[oz] are re-encoded in MIPS32r6/MIPS64r6 Summary: There is no change to the restrictions, just the result register is stored once in the encoding rather than twice. The rt field is zero in MIPS32r6/MIPS64r6. Depends on D4119 Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4120 llvm-svn: 211019
2014-06-16 21:18:59 +08:00
dclo $s2,$a2 # CHECK: dclo $18, $6 # encoding: [0x70,0xd2,0x90,0x25]
dclz $s0,$25 # CHECK: dclz $16, $25 # encoding: [0x73,0x30,0x80,0x24]
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
deret
[mips] Add test cases for dext/dins family of instructions Add missing test cases for dext, dextm, dextu, dins, dinsm and dinsu instructions. Differential Revision: https://reviews.llvm.org/D37741 llvm-svn: 314503
2017-09-29 17:53:24 +08:00
dext $9,$6,3,7 # CHECK: dext $9, $6, 3, 7 # encoding: [0x7c,0xc9,0x30,0xc3]
dextm $9,$6,3,39 # CHECK: dextm $9, $6, 3, 39 # encoding: [0x7c,0xc9,0x30,0xc1]
dextu $9,$6,35,7 # CHECK: dextu $9, $6, 35, 7 # encoding: [0x7c,0xc9,0x30,0xc2]
[mips] Marked the DI/EI instruction aliases as MIPS32r2 Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5751 llvm-svn: 219927
2014-10-16 23:23:52 +08:00
di $s8 # CHECK: di $fp # encoding: [0x41,0x7e,0x60,0x00]
di # CHECK: di # encoding: [0x41,0x60,0x60,0x00]
[mips] Add test cases for dext/dins family of instructions Add missing test cases for dext, dextm, dextu, dins, dinsm and dinsu instructions. Differential Revision: https://reviews.llvm.org/D37741 llvm-svn: 314503
2017-09-29 17:53:24 +08:00
dins $2,$3,4,28 # CHECK: dins $2, $3, 4, 28 # encoding: [0x7c,0x62,0xf9,0x07]
[mips] correct operand range for DINSM instruction This patch corrects the definition of the DINSM instruction. Specification for DINSM instruction for Mips64 says that size operand should be 2 <= size <= 64, but it is defined as uimm5_inssize_plus1 which gives range of 1 .. 32. Patch by Aleksandar Beserminji. Differential Revision: https://reviews.llvm.org/D37683 llvm-svn: 313149
2017-09-13 22:09:13 +08:00
dinsm $2,$3,4,34 # CHECK: dinsm $2, $3, 4, 34 # encoding: [0x7c,0x62,0x29,0x05]
[mips] Add test cases for dext/dins family of instructions Add missing test cases for dext, dextm, dextu, dins, dinsm and dinsu instructions. Differential Revision: https://reviews.llvm.org/D37741 llvm-svn: 314503
2017-09-29 17:53:24 +08:00
dinsu $2,$3,34,16 # CHECK: dinsu $2, $3, 34, 16 # encoding: [0x7c,0x62,0x88,0x86]
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
ddiv $zero,$k0,$s3
ddivu $zero,$s0,$s1
div $zero,$25,$11
div.d $f29,$f20,$f27
div.s $f4,$f5,$f15
divu $zero,$25,$15
[mips] Add COP0 register class and use it in M[FT]C0/DM[FT]C0. Summary: Previously it (incorrectly) used GPR's. Patch by Simon Dardis. A couple small corrections by myself. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10567 llvm-svn: 240883
2015-06-27 23:39:19 +08:00
dmfc0 $10,$16,2 # CHECK: dmfc0 $10, $16, 2 # encoding: [0x40,0x2a,0x80,0x02]
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
dmfc1 $12,$f13
[mips] Add COP0 register class and use it in M[FT]C0/DM[FT]C0. Summary: Previously it (incorrectly) used GPR's. Patch by Simon Dardis. A couple small corrections by myself. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10567 llvm-svn: 240883
2015-06-27 23:39:19 +08:00
dmtc0 $4,$10,0 # CHECK: dmtc0 $4, $10, 0 # encoding: [0x40,0xa4,0x50,0x00]
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
dmtc1 $s0,$f14
dmult $s7,$9
dmultu $a1,$a2
[mips][msa] Test basic operations for the N32 ABI too. Summary: This required adding instruction aliases for dneg. N64 will be enabled shortly but requires additional bugfixes. Reviewers: vkalintiris Reviewed By: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9341 llvm-svn: 236489
2015-05-05 16:48:35 +08:00
dneg $2 # CHECK: dneg $2, $2 # encoding: [0x00,0x02,0x10,0x2e]
dneg $2,$3 # CHECK: dneg $2, $3 # encoding: [0x00,0x03,0x10,0x2e]
dnegu $2,$3 # CHECK: dnegu $2, $3 # encoding: [0x00,0x03,0x10,0x2f]
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
drotr $1,15 # CHECK: drotr $1, $1, 15 # encoding: [0x00,0x21,0x0b,0xfa]
drotr $1,$14,15 # CHECK: drotr $1, $14, 15 # encoding: [0x00,0x2e,0x0b,0xfa]
drotr32 $1,15 # CHECK: drotr32 $1, $1, 15 # encoding: [0x00,0x21,0x0b,0xfe]
drotr32 $1,$14,15 # CHECK: drotr32 $1, $14, 15 # encoding: [0x00,0x2e,0x0b,0xfe]
drotrv $1,$14,$15 # CHECK: drotrv $1, $14, $15 # encoding: [0x01,0xee,0x08,0x56]
dsbh $v1,$14
dshd $v0,$sp
dsll $zero,18 # CHECK: dsll $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xb8]
dsll $zero,$s4,18 # CHECK: dsll $zero, $20, 18 # encoding: [0x00,0x14,0x04,0xb8]
dsll $zero,$s4,$12 # CHECK: dsllv $zero, $20, $12 # encoding: [0x01,0x94,0x00,0x14]
[mips] Add instruction aliases for ds(r|l)l. Add the instruction aliases for ds(r|l)l for the two operand alias of ds(r|l)lv and the aliases ds(r|l)l with the three register operands. llvm-svn: 306405
2017-06-27 21:35:17 +08:00
dsll $4, $5 # CHECK: dsllv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x14]
dsll $4, $5, $5 # CHECK: dsllv $4, $5, $5 # encoding: [0x00,0xa5,0x20,0x14]
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
dsll32 $zero,18 # CHECK: dsll32 $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xbc]
dsll32 $zero,$zero,18 # CHECK: dsll32 $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xbc]
dsllv $zero,$s4,$12 # CHECK: dsllv $zero, $20, $12 # encoding: [0x01,0x94,0x00,0x14]
dsra $gp,10 # CHECK: dsra $gp, $gp, 10 # encoding: [0x00,0x1c,0xe2,0xbb]
dsra $gp,$s2,10 # CHECK: dsra $gp, $18, 10 # encoding: [0x00,0x12,0xe2,0xbb]
[mips] Added missing dsra -> dsrav and sra -> srav aliases. Summary: dsll, dsrl, sll, and srl already exist. Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3673 llvm-svn: 208397
2014-05-09 17:24:49 +08:00
dsra $gp,$s2,$s3 # CHECK: dsrav $gp, $18, $19 # encoding: [0x02,0x72,0xe0,0x17]
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
dsra32 $gp,10 # CHECK: dsra32 $gp, $gp, 10 # encoding: [0x00,0x1c,0xe2,0xbf]
dsra32 $gp,$s2,10 # CHECK: dsra32 $gp, $18, 10 # encoding: [0x00,0x12,0xe2,0xbf]
dsrav $gp,$s2,$s3 # CHECK: dsrav $gp, $18, $19 # encoding: [0x02,0x72,0xe0,0x17]
dsrl $s3,23 # CHECK: dsrl $19, $19, 23 # encoding: [0x00,0x13,0x9d,0xfa]
dsrl $s3,$6,23 # CHECK: dsrl $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfa]
dsrl $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16]
[mips] Add instruction aliases for ds(r|l)l. Add the instruction aliases for ds(r|l)l for the two operand alias of ds(r|l)lv and the aliases ds(r|l)l with the three register operands. llvm-svn: 306405
2017-06-27 21:35:17 +08:00
dsrl $4, $5 # CHECK: dsrlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x16]
dsrl $4, $4, $5 # CHECK: dsrlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x16]
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
dsrl32 $s3,23 # CHECK: dsrl32 $19, $19, 23 # encoding: [0x00,0x13,0x9d,0xfe]
dsrl32 $s3,$6,23 # CHECK: dsrl32 $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfe]
dsrlv $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16]
dsub $a3,$s6,$8
dsub $a3,$s6,$8
[mips][mips64r6] daddi is not available on MIPS64r6 Summary: It's not emitted by the code generator so we only need assembler tests. Also added missing daddi aliases from dsub mnemonics, and removed a couple duplicate dsub tests. Depends on D4112 Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4113 llvm-svn: 210897
2014-06-13 20:49:06 +08:00
dsub $sp,$s4,-27705 # CHECK: daddi $sp, $20, 27705 # encoding: [0x62,0x9d,0x6c,0x39]
dsub $sp,-27705 # CHECK: daddi $sp, $sp, 27705 # encoding: [0x63,0xbd,0x6c,0x39]
dsubi $sp,$s4,-27705 # CHECK: daddi $sp, $20, 27705 # encoding: [0x62,0x9d,0x6c,0x39]
dsubi $sp,-27705 # CHECK: daddi $sp, $sp, 27705 # encoding: [0x63,0xbd,0x6c,0x39]
dsubu $a1,$a1,$k0
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
dsubu $a1,$a1,$k0
[mips] Marked the DADDiu instruction aliases as MIPS III. Patch by Vasileios Kalintiris. Differential Revision: http://reviews.llvm.org/D5239 llvm-svn: 217770
2014-09-15 22:47:46 +08:00
dsubu $15,$11,5025 # CHECK: daddiu $15, $11, -5025 # encoding: [0x65,0x6f,0xec,0x5f]
dsubu $14,-4586 # CHECK: daddiu $14, $14, 4586 # encoding: [0x65,0xce,0x11,0xea]
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0]
[mips] Marked the DI/EI instruction aliases as MIPS32r2 Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D5751 llvm-svn: 219927
2014-10-16 23:23:52 +08:00
ei $14 # CHECK: ei $14 # encoding: [0x41,0x6e,0x60,0x20]
ei # CHECK: ei # encoding: [0x41,0x60,0x60,0x20]
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
eret
floor.l.d $f26,$f7
floor.l.s $f12,$f5
[mips] Fix the predicates of round, ceiling, floor and trunc. Reviewers: atanasyan, abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D46691 llvm-svn: 332258
2018-05-15 00:26:50 +08:00
floor.w.d $f14,$f11 # CHECK: floor.w.d $f14, $f11 # encoding: [0x46,0x20,0x5b,0x8f]
# CHECK: # <MCInst #{{.*}} FLOOR_W_D64
floor.w.s $f8,$f9 # CHECK: floor.w.s $f8, $f9 # encoding: [0x46,0x00,0x4a,0x0f]
# CHECK: # <MCInst #{{.*}} FLOOR_W_S
[mips] Correct label prefixes for N32 and N64. Summary: N32 and N64 follow the standard ELF conventions (.L) whereas O32 uses its own ($). This fixes the majority of object differences between -fintegrated-as and -fno-integrated-as. Reviewers: sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: https://reviews.llvm.org/D22412 llvm-svn: 275967
2016-07-19 18:49:03 +08:00
j 1f # CHECK: j .Ltmp0 # encoding: [0b000010AA,A,A,A]
# CHECK: # fixup A - offset: 0, value: .Ltmp0, kind: fixup_Mips_26
[mips] [IAS] Remove AssemblerPredicate's from RelocPIC and RelocStatic. Summary: These AssemblerPredicate's are unnecessary and actually make some instructions unusable when assembling pre-MIPS32 ISAs. For example, this was causing the IAS to reject the 'j' instruction for MIPS I-V. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8300 llvm-svn: 234398
2015-04-08 18:06:45 +08:00
j a # CHECK: j a # encoding: [0b000010AA,A,A,A]
# CHECK: # fixup A - offset: 0, value: a, kind: fixup_Mips_26
j 1328 # CHECK: j 1328 # encoding: [0x08,0x00,0x01,0x4c]
[mips] Never select JAL for calls to an absolute immediate address. Summary: It actually takes an offset into the current PC-region. This fixes the 'expr' command in lldb. Reviewers: vkalintiris, jaydeep, bhushan Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D16054 llvm-svn: 257339
2016-01-11 23:57:46 +08:00
jal 21100 # CHECK: jal 21100 # encoding: [0x0c,0x00,0x14,0x9b]
[mips] Implement jr.hb and jalr.hb (Jump Register and Jump and Link Register with Hazard Barrier). Summary: These instructions are available in ISAs >= mips32/mips64. For mips32r6/mips64r6, jr.hb has a new encoding format. Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D4019 llvm-svn: 210654
2014-06-11 23:05:56 +08:00
jr.hb $4 # CHECK: jr.hb $4 # encoding: [0x00,0x80,0x04,0x08]
jalr.hb $4 # CHECK: jalr.hb $4 # encoding: [0x00,0x80,0xfc,0x09]
jalr.hb $4, $5 # CHECK: jalr.hb $4, $5 # encoding: [0x00,0xa0,0x24,0x09]
[mips] Add l.[sd] and s.[sd] instruction aliases Reviewers: dsanders, vkalintiris Differential Review: https://reviews.llvm.org/D23121 llvm-svn: 278930
2016-08-17 22:45:09 +08:00
l.s $f2, 8($3) # CHECK: lwc1 $f2, 8($3) # encoding: [0xc4,0x62,0x00,0x08]
l.d $f2, 8($3) # CHECK: ldc1 $f2, 8($3) # encoding: [0xd4,0x62,0x00,0x08]
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
lb $24,-14515($10)
lbu $8,30195($v1)
ld $sp,-28645($s1)
ldc1 $f11,16391($s0)
[mips][mips64r6] [ls][wd]c2 were re-encoded with 11-bit signed immediates rather than 16-bit in MIPS32r6/MIPS64r6 Summary: The error message for the invalid.s cases isn't very helpful. It happens because there is an instruction with a wider immediate that would have matched if the NotMips32r6 predicate were true. I have some WIP to improve the message but it affects most error messages for removed/re-encoded instructions on MIPS32r6/MIPS64r6 and should therefore be a separate commit. Depens on D4115 Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4117 llvm-svn: 211012
2014-06-16 18:00:45 +08:00
ldc2 $8,-21181($at) # CHECK: ldc2 $8, -21181($1) # encoding: [0xd8,0x28,0xad,0x43]
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
ldl $24,-4167($24)
ldr $14,-30358($s4)
ldxc1 $f8,$s7($15)
lh $11,-8556($s5)
lhu $s3,-22851($v0)
li $at,-29773
li $zero,-29889
[mips][mips64r6] ll, sc, lld, and scd are re-encoded on MIPS32r6/MIPS64r6. Summary: The linked-load, store-conditional operations have been re-encoded such that have a 9-bit offset instead of the 16-bit offset they have prior to MIPS32r6/MIPS64r6. While implementing this, I noticed that the atomic load/store pseudos always emit a sign extension using sll and sra. I have improved this to use seb/seh when they are available (MIPS32r2/MIPS64r2 and above). Depends on D4118 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4119 llvm-svn: 211018
2014-06-16 21:13:03 +08:00
ll $v0,-7321($s2) # CHECK: ll $2, -7321($18) # encoding: [0xc2,0x42,0xe3,0x67]
lld $zero,-14736($ra) # CHECK: lld $zero, -14736($ra) # encoding: [0xd3,0xe0,0xc6,0x70]
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
luxc1 $f19,$s6($s5)
lw $8,5674($a1)
lwc1 $f16,10225($k0)
[mips][mips64r6] [ls][wd]c2 were re-encoded with 11-bit signed immediates rather than 16-bit in MIPS32r6/MIPS64r6 Summary: The error message for the invalid.s cases isn't very helpful. It happens because there is an instruction with a wider immediate that would have matched if the NotMips32r6 predicate were true. I have some WIP to improve the message but it affects most error messages for removed/re-encoded instructions on MIPS32r6/MIPS64r6 and should therefore be a separate commit. Depens on D4115 Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4117 llvm-svn: 211012
2014-06-16 18:00:45 +08:00
lwc2 $18,-841($a2) # CHECK: lwc2 $18, -841($6) # encoding: [0xc8,0xd2,0xfc,0xb7]
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
lwl $s4,-4231($15)
lwr $zero,-19147($gp)
lwu $s3,-24086($v1)
lwxc1 $f12,$s1($s8)
madd $s6,$13
madd $zero,$9
madd.s $f1,$f31,$f19,$f25
maddu $s3,$gp
maddu $24,$s2
[mips] Add COP0 register class and use it in M[FT]C0/DM[FT]C0. Summary: Previously it (incorrectly) used GPR's. Patch by Simon Dardis. A couple small corrections by myself. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10567 llvm-svn: 240883
2015-06-27 23:39:19 +08:00
mfc0 $8,$15,1 # CHECK: mfc0 $8, $15, 1 # encoding: [0x40,0x08,0x78,0x01]
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
mfc1 $a3,$f27
mfhc1 $s8,$f24
mfhi $s3
mfhi $sp
mflo $s1
mov.d $f20,$f14
mov.s $f2,$f27
[mips] Remap move as or. Summary: This patch remaps the assembly idiom 'move' to 'or' instead of 'daddu' or 'addu'. The use of addu/daddu instead of or as move was highlighted as a performance issue during the analysis of a recent 64bit design. Originally move was encoded as 'or' by binutils but was changed for the r10k cpu family due to their pipeline which had 2 arithmetic units and a single logical unit, and so could issue multiple (d)addu based moves at the same time but only 1 logical move. This patch preserves the disassembly behaviour so that disassembling a old style (d)addu move still appears as move, but assembling move always gives an or Patch by Simon Dardis. Reviewers: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11796 llvm-svn: 244579
2015-08-11 16:56:25 +08:00
move $a0,$a3 # CHECK: move $4, $7 # encoding: [0x00,0xe0,0x20,0x25]
move $s5,$a0 # CHECK: move $21, $4 # encoding: [0x00,0x80,0xa8,0x25]
move $s8,$a0 # CHECK: move $fp, $4 # encoding: [0x00,0x80,0xf0,0x25]
move $25,$a2 # CHECK: move $25, $6 # encoding: [0x00,0xc0,0xc8,0x25]
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
movf $gp,$8,$fcc7
movf.d $f6,$f11,$fcc5
movf.s $f23,$f5,$fcc6
movn $v1,$s1,$s0
movn.d $f27,$f21,$k0
movn.s $f12,$f0,$s7
movt $zero,$s4,$fcc5
movt.d $f0,$f2,$fcc0
movt.s $f30,$f2,$fcc1
movz $a1,$s6,$9
movz.d $f12,$f29,$9
movz.s $f25,$f7,$v1
msub $s7,$k1
msub.s $f12,$f19,$f10,$f16
msubu $15,$a1
[mips] Add COP0 register class and use it in M[FT]C0/DM[FT]C0. Summary: Previously it (incorrectly) used GPR's. Patch by Simon Dardis. A couple small corrections by myself. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10567 llvm-svn: 240883
2015-06-27 23:39:19 +08:00
mtc0 $9,$15,1 # CHECK: mtc0 $9, $15, 1 # encoding: [0x40,0x89,0x78,0x01]
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
mtc1 $s8,$f9
mthc1 $zero,$f16
mthi $s1
mtlo $sp
mtlo $25
mul $s0,$s4,$at
mul.d $f20,$f20,$f16
[mips] Implement add.ps, mul.ps and sub.ps Differential revision: https://reviews.llvm.org/D90321
2020-10-30 15:57:22 +08:00
mul.ps $f14, $f0, $f16 # CHECK: mul.ps $f14, $f0, $f16 # encoding: [0x46,0xd0,0x03,0x82]
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
mul.s $f30,$f10,$f2
mult $sp,$s4
mult $sp,$v0
multu $gp,$k0
multu $9,$s2
[mips] sgtu, s[rl]l, sra, dnegu, neg instruction aliases Add the instruction alias sgtu (register form only), two operand forms of s[rl]l and sra, and missing single/two operand forms of dnegu/neg. Reviewers: dsanders Differential Revision: https://reviews.llvm.org/D22752 llvm-svn: 276736
2016-07-26 17:13:46 +08:00
neg $2 # CHECK: neg $2, $2 # encoding: [0x00,0x02,0x10,0x22]
neg $2, $3 # CHECK: neg $2, $3 # encoding: [0x00,0x03,0x10,0x22]
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
negu $2 # CHECK: negu $2, $2 # encoding: [0x00,0x02,0x10,0x23]
negu $2,$3 # CHECK: negu $2, $3 # encoding: [0x00,0x03,0x10,0x23]
neg.d $f27,$f18
neg.s $f1,$f15
nmadd.s $f0,$f5,$f25,$f12
nmsub.s $f1,$f24,$f19,$f4
nop
nor $a3,$zero,$a3
[mips] not instruction alias This patch adds the single operand form of the not alias to microMIPS and MIPS along with additional tests. This partially resolves PR/30381. Thanks to Sean Bruno for reporting the issue! llvm-svn: 287097
2016-11-16 19:04:49 +08:00
not $3, $4 # CHECK: not $3, $4 # encoding: [0x00,0x80,0x18,0x27]
not $3 # CHECK: not $3, $3 # encoding: [0x00,0x60,0x18,0x27]
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
or $12,$s0,$sp
[mips] Implement alias for 'and' and 'or' instructions for all ISAs. Summary: Examples: and $2, 4 <=> andi $2, $2, 4 or $2, 4 <=> ori $2, $2, 4 Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D4155 llvm-svn: 211161
2014-06-18 21:30:57 +08:00
or $2, 4 # CHECK: ori $2, $2, 4 # encoding: [0x34,0x42,0x00,0x04]
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
pause # CHECK: pause # encoding: [0x00,0x00,0x01,0x40]
[mips][test] Remove redundant and invalid `CHECK-NOT` directives. NFC 1. It's redundant to explicitly check that string does not contain `PAUSE_MM` token if check that the `PAUSE` token is followed by an angle bracket. 2. The removed `CHECK-NOT` directives do not have trailing colons.
2020-04-03 21:20:09 +08:00
# CHECK-NEXT: # <MCInst #{{[0-9]+}} PAUSE>
[mips] Add missing instructions Add pll.ps, plu.ps, cvt.s.pu, cvt.s.pl, cvt.ps instructions for FP64. Differential Revision: https://reviews.llvm.org/D50437 llvm-svn: 340920
2018-08-29 19:35:03 +08:00
pll.ps $f26,$f10,$f30 # CHECK: pll.ps $f26, $f10, $f30 # encoding: [0x46,0xde,0x56,0xac]
# CHECK: # <MCInst #{{[0-9]+}} PLL_PS64
plu.ps $f2,$f26,$f30 # CHECK: plu.ps $f2, $f26, $f30 # encoding: [0x46,0xde,0xd0,0xad]
# CHECK: # <MCInst #{{[0-9]+}} PLU_PS64
[mips] Add cache and pref instructions Summary: cache and pref were added in MIPS-III, and MIPS32 but were re-encoded in MIPS32r6/MIPS64r6 to use a 9-bit offset rather than the 16-bit offset available to earlier cores. Resolved the decoding conflict between pref and lwc3. Depends on D4115 Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4116 llvm-svn: 210900
2014-06-13 21:15:59 +08:00
pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0xcc,0xa1,0x00,0x08]
[MIPS] Implement PUL.PS and PUU.PS instructions Patch by Michael Roe. Differential Revision: https://reviews.llvm.org/D75812
2020-03-14 00:15:55 +08:00
pul.ps $f9,$f30,$f26 # CHECK: pul.ps $f9, $f30, $f26 # encoding: [0x46,0xda,0xf2,0x6e]
# CHECK: # <MCInst #{{[0-9]+}} PUL_PS64
puu.ps $f24,$f9,$f2 # CHECK: puu.ps $f24, $f9, $f2 # encoding: [0x46,0xc2,0x4e,0x2f]
# CHECK: # <MCInst #{{[0-9]+}} PUU_PS64
Recommit "[mips] Add names and tests for the hardware registers" The original commit r221299 was reverted in r221307. I removed the name "hrw_ulr" ($29) from the original commit because two tests were failing. llvm-svn: 221681
2014-11-11 18:31:31 +08:00
# FIXME: Use the code generator in order to print the .set directives
# instead of the instruction printer.
rdhwr $sp,$11 # CHECK: .set push
# CHECK-NEXT: .set mips32r2
# CHECK-NEXT: rdhwr $sp, $11
# CHECK-NEXT: .set pop # encoding: [0x7c,0x1d,0x58,0x3b]
Recommit: "[mips] Add rsqrt, recip for MIPS" Add rsqrt.[ds], recip.[ds] for MIPS. Correct the microMIPS definitions for architecture support and register usage. Reviewers: vkalintiris, zoran.jovanoic Differential Review: https://reviews.llvm.org/D24499 llvm-svn: 283334
2016-10-06 00:11:01 +08:00
recip.d $f19,$f6 # CHECK: recip.d $f19, $f6 # encoding: [0x46,0x20,0x34,0xd5]
recip.s $f3,$f30 # CHECK: recip.s $f3, $f30 # encoding: [0x46,0x00,0xf0,0xd5]
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
rotr $1,15 # CHECK: rotr $1, $1, 15 # encoding: [0x00,0x21,0x0b,0xc2]
rotr $1,$14,15 # CHECK: rotr $1, $14, 15 # encoding: [0x00,0x2e,0x0b,0xc2]
rotrv $1,$14,$15 # CHECK: rotrv $1, $14, $15 # encoding: [0x01,0xee,0x08,0x46]
round.l.d $f12,$f1
round.l.s $f25,$f5
[mips] Fix the predicates of round, ceiling, floor and trunc. Reviewers: atanasyan, abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D46691 llvm-svn: 332258
2018-05-15 00:26:50 +08:00
round.w.d $f6, $f4 # CHECK: round.w.d $f6, $f4 # encoding: [0x46,0x20,0x21,0x8c]
# CHECK: # <MCInst #{{.*}} ROUND_W_D64
round.w.s $f27,$f28 # CHECK: round.w.s $f27, $f28 # encoding: [0x46,0x00,0xe6,0xcc]
# CHECK: # <MCInst #{{.*}} ROUND_W_S
Recommit: "[mips] Add rsqrt, recip for MIPS" Add rsqrt.[ds], recip.[ds] for MIPS. Correct the microMIPS definitions for architecture support and register usage. Reviewers: vkalintiris, zoran.jovanoic Differential Review: https://reviews.llvm.org/D24499 llvm-svn: 283334
2016-10-06 00:11:01 +08:00
rsqrt.s $f0,$f4 # CHECK: rsqrt.s $f0, $f4 # encoding: [0x46,0x00,0x20,0x16]
rsqrt.d $f2,$f6 # CHECK: rsqrt.d $f2, $f6 # encoding: [0x46,0x20,0x30,0x96]
[mips] Add l.[sd] and s.[sd] instruction aliases Reviewers: dsanders, vkalintiris Differential Review: https://reviews.llvm.org/D23121 llvm-svn: 278930
2016-08-17 22:45:09 +08:00
s.s $f2, 8($3) # CHECK: swc1 $f2, 8($3) # encoding: [0xe4,0x62,0x00,0x08]
s.d $f2, 8($3) # CHECK: sdc1 $f2, 8($3) # encoding: [0xf4,0x62,0x00,0x08]
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
sb $s6,-19857($14)
[mips][mips64r6] ll, sc, lld, and scd are re-encoded on MIPS32r6/MIPS64r6. Summary: The linked-load, store-conditional operations have been re-encoded such that have a 9-bit offset instead of the 16-bit offset they have prior to MIPS32r6/MIPS64r6. While implementing this, I noticed that the atomic load/store pseudos always emit a sign extension using sll and sra. I have improved this to use seb/seh when they are available (MIPS32r2/MIPS64r2 and above). Depends on D4118 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4119 llvm-svn: 211018
2014-06-16 21:13:03 +08:00
sc $15,18904($s3) # CHECK: sc $15, 18904($19) # encoding: [0xe2,0x6f,0x49,0xd8]
scd $15,-8243($sp) # CHECK: scd $15, -8243($sp) # encoding: [0xf3,0xaf,0xdf,0xcd]
[mips] Added support for assembling sdbbp. Summary: This instruction is re-encoded in MIPS32r6/MIPS64r6 without changing the restrictions. We hadn't implemented it for earlier ISA's so it has been added to those too. Differential Revision: http://reviews.llvm.org/D4265 llvm-svn: 211590
2014-06-24 21:00:32 +08:00
sdbbp # CHECK: sdbbp # encoding: [0x70,0x00,0x00,0x3f]
[mips] Correct the predicates for special nops, tlb ctrl instrs, software breakpoint and prefx. Reviewers: atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D44436 llvm-svn: 329905
2018-04-12 20:37:02 +08:00
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SDBBP
# CHECK-NOT: # <MCInst #{{[0-9]+}} SDBBP_MM
[mips] Added support for assembling sdbbp. Summary: This instruction is re-encoded in MIPS32r6/MIPS64r6 without changing the restrictions. We hadn't implemented it for earlier ISA's so it has been added to those too. Differential Revision: http://reviews.llvm.org/D4265 llvm-svn: 211590
2014-06-24 21:00:32 +08:00
sdbbp 34 # CHECK: sdbbp 34 # encoding: [0x70,0x00,0x08,0xbf]
[mips] Correct the predicates for special nops, tlb ctrl instrs, software breakpoint and prefx. Reviewers: atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D44436 llvm-svn: 329905
2018-04-12 20:37:02 +08:00
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SDBBP
# CHECK-NOT: # <MCInst #{{[0-9]+}} SDBBP_MM
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
sd $12,5835($10)
sdc1 $f31,30574($13)
[mips][mips64r6] [ls][wd]c2 were re-encoded with 11-bit signed immediates rather than 16-bit in MIPS32r6/MIPS64r6 Summary: The error message for the invalid.s cases isn't very helpful. It happens because there is an instruction with a wider immediate that would have matched if the NotMips32r6 predicate were true. I have some WIP to improve the message but it affects most error messages for removed/re-encoded instructions on MIPS32r6/MIPS64r6 and should therefore be a separate commit. Depens on D4115 Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4117 llvm-svn: 211012
2014-06-16 18:00:45 +08:00
sdc2 $20,23157($s2) # CHECK: sdc2 $20, 23157($18) # encoding: [0xfa,0x54,0x5a,0x75]
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
sdl $a3,-20961($s8)
sdr $11,-20423($12)
sdxc1 $f11,$10($14)
[mips] seb, seh instruction aliases Add the single operand form. Reviewers: vkalintiris Differential Revision: https://reviews.llvm.org/D26961 llvm-svn: 287681
2016-11-23 03:17:23 +08:00
seb $25, $15 # CHECK: seb $25, $15 # encoding: [0x7c,0x0f,0xcc,0x20]
[mips] Correct the predicates of sign extension instructions And eliminatw the duplication of those instructions for microMIPS32r6. Reviewers: smaksimovic, abeserminji, atanasyan Differential Revision: https://reviews.llvm.org/D46117 llvm-svn: 331526
2018-05-04 23:00:54 +08:00
# CHECK-NOT: # <MCInst #{{[0-9]+}} SEB_MM
[mips] seb, seh instruction aliases Add the single operand form. Reviewers: vkalintiris Differential Revision: https://reviews.llvm.org/D26961 llvm-svn: 287681
2016-11-23 03:17:23 +08:00
seb $25 # CHECK: seb $25, $25 # encoding: [0x7c,0x19,0xcc,0x20]
[mips] Correct the predicates of sign extension instructions And eliminatw the duplication of those instructions for microMIPS32r6. Reviewers: smaksimovic, abeserminji, atanasyan Differential Revision: https://reviews.llvm.org/D46117 llvm-svn: 331526
2018-05-04 23:00:54 +08:00
# CHECK-NOT: # <MCInst #{{[0-9]+}} SEB_MM
[mips] seb, seh instruction aliases Add the single operand form. Reviewers: vkalintiris Differential Revision: https://reviews.llvm.org/D26961 llvm-svn: 287681
2016-11-23 03:17:23 +08:00
seh $3, $12 # CHECK: seh $3, $12 # encoding: [0x7c,0x0c,0x1e,0x20]
[mips] Correct the predicates of sign extension instructions And eliminatw the duplication of those instructions for microMIPS32r6. Reviewers: smaksimovic, abeserminji, atanasyan Differential Revision: https://reviews.llvm.org/D46117 llvm-svn: 331526
2018-05-04 23:00:54 +08:00
# CHECK-NOT: # <MCInst #{{[0-9]+}} SEH_MM
[mips] seb, seh instruction aliases Add the single operand form. Reviewers: vkalintiris Differential Revision: https://reviews.llvm.org/D26961 llvm-svn: 287681
2016-11-23 03:17:23 +08:00
seh $3 # CHECK: seh $3, $3 # encoding: [0x7c,0x03,0x1e,0x20]
[mips] Correct the predicates of sign extension instructions And eliminatw the duplication of those instructions for microMIPS32r6. Reviewers: smaksimovic, abeserminji, atanasyan Differential Revision: https://reviews.llvm.org/D46117 llvm-svn: 331526
2018-05-04 23:00:54 +08:00
# CHECK-NOT: # <MCInst #{{[0-9]+}} SEH_MM
[mips] sgtu, s[rl]l, sra, dnegu, neg instruction aliases Add the instruction alias sgtu (register form only), two operand forms of s[rl]l and sra, and missing single/two operand forms of dnegu/neg. Reviewers: dsanders Differential Revision: https://reviews.llvm.org/D22752 llvm-svn: 276736
2016-07-26 17:13:46 +08:00
sgt $4, $5 # CHECK: slt $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2a]
sgt $4, $5, $6 # CHECK: slt $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2a]
sgtu $4, $5 # CHECK: sltu $4, $5, $4 # encoding: [0x00,0xa4,0x20,0x2b]
sgtu $4, $5, $6 # CHECK: sltu $4, $6, $5 # encoding: [0x00,0xc5,0x20,0x2b]
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
sh $14,-6704($15)
[mips] sgtu, s[rl]l, sra, dnegu, neg instruction aliases Add the instruction alias sgtu (register form only), two operand forms of s[rl]l and sra, and missing single/two operand forms of dnegu/neg. Reviewers: dsanders Differential Revision: https://reviews.llvm.org/D22752 llvm-svn: 276736
2016-07-26 17:13:46 +08:00
sll $4, $5 # CHECK: sllv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x04]
[mips] Correct the predicates for shifts. Reviewers: smaksimovic, abeserminji, atanasyan Differential Revision: https://reviews.llvm.org/D46123 llvm-svn: 331341
2018-05-02 17:55:49 +08:00
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
# CHECK-NOT: # <MCInst #{{[0-9]+}} SLL_MM
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80]
[mips] Correct the predicates for shifts. Reviewers: smaksimovic, abeserminji, atanasyan Differential Revision: https://reviews.llvm.org/D46123 llvm-svn: 331341
2018-05-02 17:55:49 +08:00
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
# CHECK-NOT: # <MCInst #{{[0-9]+}} SLL_MM
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80]
[mips] Correct the predicates for shifts. Reviewers: smaksimovic, abeserminji, atanasyan Differential Revision: https://reviews.llvm.org/D46123 llvm-svn: 331341
2018-05-02 17:55:49 +08:00
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
# CHECK-NOT: # <MCInst #{{[0-9]+}} SLL_MM
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
[mips] Correct the predicates for shifts. Reviewers: smaksimovic, abeserminji, atanasyan Differential Revision: https://reviews.llvm.org/D46123 llvm-svn: 331341
2018-05-02 17:55:49 +08:00
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SLL
# CHECK-NOT: # <MCInst #{{[0-9]+}} SLL_MM
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
sllv $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04]
[mips] Correct the predicates for shifts. Reviewers: smaksimovic, abeserminji, atanasyan Differential Revision: https://reviews.llvm.org/D46123 llvm-svn: 331341
2018-05-02 17:55:49 +08:00
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SLLV
# CHECK-NOT: # <MCInst #{{[0-9]+}} SLLV_MM
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
slt $s7,$11,$k1 # CHECK: slt $23, $11, $27 # encoding: [0x01,0x7b,0xb8,0x2a]
slti $s1,$10,9489 # CHECK: slti $17, $10, 9489 # encoding: [0x29,0x51,0x25,0x11]
sltiu $25,$25,-15531 # CHECK: sltiu $25, $25, -15531 # encoding: [0x2f,0x39,0xc3,0x55]
sltu $s4,$s5,$11 # CHECK: sltu $20, $21, $11 # encoding: [0x02,0xab,0xa0,0x2b]
sltu $24,$25,-15531 # CHECK: sltiu $24, $25, -15531 # encoding: [0x2f,0x38,0xc3,0x55]
sqrt.d $f17,$f22
sqrt.s $f0,$f1
[mips] sgtu, s[rl]l, sra, dnegu, neg instruction aliases Add the instruction alias sgtu (register form only), two operand forms of s[rl]l and sra, and missing single/two operand forms of dnegu/neg. Reviewers: dsanders Differential Revision: https://reviews.llvm.org/D22752 llvm-svn: 276736
2016-07-26 17:13:46 +08:00
sra $4, $5 # CHECK: srav $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x07]
[mips] Correct the predicates for shifts. Reviewers: smaksimovic, abeserminji, atanasyan Differential Revision: https://reviews.llvm.org/D46123 llvm-svn: 331341
2018-05-02 17:55:49 +08:00
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
# CHECK-NOT: # <MCInst #{{[0-9]+}} SRA_MM
sra $s1,15 # CHECK: sra $17, $17, 15 # encoding: [0x00,0x11,0x8b,0xc3]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
# CHECK-NOT: # <MCInst #{{[0-9]+}} SRA_MM
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
sra $s1,$s7,15 # CHECK: sra $17, $23, 15 # encoding: [0x00,0x17,0x8b,0xc3]
[mips] Correct the predicates for shifts. Reviewers: smaksimovic, abeserminji, atanasyan Differential Revision: https://reviews.llvm.org/D46123 llvm-svn: 331341
2018-05-02 17:55:49 +08:00
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
# CHECK-NOT: # <MCInst #{{[0-9]+}} SRA_MM
[mips] Added missing dsra -> dsrav and sra -> srav aliases. Summary: dsll, dsrl, sll, and srl already exist. Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3673 llvm-svn: 208397
2014-05-09 17:24:49 +08:00
sra $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
[mips] Correct the predicates for shifts. Reviewers: smaksimovic, abeserminji, atanasyan Differential Revision: https://reviews.llvm.org/D46123 llvm-svn: 331341
2018-05-02 17:55:49 +08:00
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SRA
# CHECK-NOT: # <MCInst #{{[0-9]+}} SRA_MM
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
srav $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07]
[mips] Correct the predicates for shifts. Reviewers: smaksimovic, abeserminji, atanasyan Differential Revision: https://reviews.llvm.org/D46123 llvm-svn: 331341
2018-05-02 17:55:49 +08:00
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SRAV
# CHECK-NOT: # <MCInst #{{[0-9]+}} SRAV_MM
[mips] sgtu, s[rl]l, sra, dnegu, neg instruction aliases Add the instruction alias sgtu (register form only), two operand forms of s[rl]l and sra, and missing single/two operand forms of dnegu/neg. Reviewers: dsanders Differential Revision: https://reviews.llvm.org/D22752 llvm-svn: 276736
2016-07-26 17:13:46 +08:00
srl $4, $5 # CHECK: srlv $4, $4, $5 # encoding: [0x00,0xa4,0x20,0x06]
[mips] Correct the predicates for shifts. Reviewers: smaksimovic, abeserminji, atanasyan Differential Revision: https://reviews.llvm.org/D46123 llvm-svn: 331341
2018-05-02 17:55:49 +08:00
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
# CHECK-NOT: # <MCInst #{{[0-9]+}} SRL_MM
srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
# CHECK-NOT: # <MCInst #{{[0-9]+}} SRL_MM
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2]
[mips] Correct the predicates for shifts. Reviewers: smaksimovic, abeserminji, atanasyan Differential Revision: https://reviews.llvm.org/D46123 llvm-svn: 331341
2018-05-02 17:55:49 +08:00
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
# CHECK-NOT: # <MCInst #{{[0-9]+}} SRL_MM
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
[mips] Correct the predicates for shifts. Reviewers: smaksimovic, abeserminji, atanasyan Differential Revision: https://reviews.llvm.org/D46123 llvm-svn: 331341
2018-05-02 17:55:49 +08:00
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SRL
# CHECK-NOT: # <MCInst #{{[0-9]+}} SRL_MM
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06]
[mips] Correct the predicates for shifts. Reviewers: smaksimovic, abeserminji, atanasyan Differential Revision: https://reviews.llvm.org/D46123 llvm-svn: 331341
2018-05-02 17:55:49 +08:00
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SRLV
# CHECK-NOT: # <MCInst #{{[0-9]+}} SRLV_MM
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40]
sub $s6,$s3,$12
[mips] Marked the ADDi instruction aliases as not available in Mips32R6 and Mips64R6. Patch by Vasileios Kalintiris. Differential Revision: http://reviews.llvm.org/D5242 llvm-svn: 217867
2014-09-16 17:26:09 +08:00
sub $22,$17,-3126 # CHECK: addi $22, $17, 3126 # encoding: [0x22,0x36,0x0c,0x36]
sub $13,6512 # CHECK: addi $13, $13, -6512 # encoding: [0x21,0xad,0xe6,0x90]
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
sub.d $f18,$f3,$f17
[mips] Implement add.ps, mul.ps and sub.ps Differential revision: https://reviews.llvm.org/D90321
2020-10-30 15:57:22 +08:00
sub.ps $f5,$f14,$f26 # CHECK: sub.ps $f5, $f14, $f26 # encoding: [0x46,0xda,0x71,0x41]
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
sub.s $f23,$f22,$f22
subu $sp,$s6,$s6
suxc1 $f12,$k1($13)
sw $ra,-10160($sp)
swc1 $f6,-8465($24)
[mips][mips64r6] [ls][wd]c2 were re-encoded with 11-bit signed immediates rather than 16-bit in MIPS32r6/MIPS64r6 Summary: The error message for the invalid.s cases isn't very helpful. It happens because there is an instruction with a wider immediate that would have matched if the NotMips32r6 predicate were true. I have some WIP to improve the message but it affects most error messages for removed/re-encoded instructions on MIPS32r6/MIPS64r6 and should therefore be a separate commit. Depens on D4115 Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4117 llvm-svn: 211012
2014-06-16 18:00:45 +08:00
swc2 $25,24880($s0) # CHECK: swc2 $25, 24880($16) # encoding: [0xea,0x19,0x61,0x30]
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
swl $15,13694($s3)
swr $s1,-26590($14)
swxc1 $f19,$12($k0)
[mips] SYNC $stype instruction was added in Mips32 but SYNC with an implied operand ($stype = 0) is valid since Mips2. llvm-svn: 211185
2014-06-19 01:10:30 +08:00
sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f]
[mips] Fix the definition of sync, synci Also, fix the disassembly of synci for microMIPS. Reviewers: abeserminji, smaksimovic, atanasyan Differential Revision: https://reviews.llvm.org/D45870 llvm-svn: 330810
2018-04-25 18:19:22 +08:00
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SYNC
[mips] SYNC $stype instruction was added in Mips32 but SYNC with an implied operand ($stype = 0) is valid since Mips2. llvm-svn: 211185
2014-06-19 01:10:30 +08:00
sync 1 # CHECK: sync 1 # encoding: [0x00,0x00,0x00,0x4f]
[mips] Fix the definition of sync, synci Also, fix the disassembly of synci for microMIPS. Reviewers: abeserminji, smaksimovic, atanasyan Differential Revision: https://reviews.llvm.org/D45870 llvm-svn: 330810
2018-04-25 18:19:22 +08:00
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SYNC
[mips] Range check uimm20 and fixed a bug this revealed. Summary: The bug was that dextu's operand 3 would print 0-31 instead of 32-63 when printing assembly. This came up when replacing MipsInstPrinter::printUnsignedImm() with a version that could handle arbitrary bit widths. MipsAsmPrinter::printUnsignedImm*() don't seem to be used so they have been removed. Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D15521 llvm-svn: 262231
2016-03-01 00:06:38 +08:00
syscall # CHECK: syscall # encoding: [0x00,0x00,0x00,0x0c]
syscall 256 # CHECK: syscall 256 # encoding: [0x00,0x00,0x40,0x0c]
Reland "[mips] Guard traps for microMIPS correctly" This is part of fixing the instruction predicates for MIPS. Reviewers: atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D44212 This patch relands r327409, hopefully without the problematic part of the tests that cause FileCheck to assert on the windows expensive checks bot. llvm-svn: 330741
2018-04-25 01:11:37 +08:00
teq $zero, $3 # CHECK: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34]
teq $5, $7, 620 # CHECK: teq $5, $7, 620 # encoding: [0x00,0xa7,0x9b,0x34]
teqi $21, -17504 # CHECK: teqi $21, -17504 # encoding: [0x06,0xac,0xbb,0xa0]
tge $7, $10 # CHECK: tge $7, $10 # encoding: [0x00,0xea,0x00,0x30]
tge $5, $19, 340 # CHECK: tge $5, $19, 340 # encoding: [0x00,0xb3,0x55,0x30]
tgei $17, 5025 # CHECK: tgei $17, 5025 # encoding: [0x06,0x28,0x13,0xa1]
tgeiu $sp, -28621 # CHECK: tgeiu $sp, -28621 # encoding: [0x07,0xa9,0x90,0x33]
tgeu $22, $gp # CHECK: tgeu $22, $gp # encoding: [0x02,0xdc,0x00,0x31]
tgeu $20, $14, 379 # CHECK: tgeu $20, $14, 379 # encoding: [0x02,0x8e,0x5e,0xf1]
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08]
[mips] Correct the predicates for special nops, tlb ctrl instrs, software breakpoint and prefx. Reviewers: atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D44436 llvm-svn: 329905
2018-04-12 20:37:02 +08:00
# CHECK-NEXT: # <MCInst #{{[0-9]+}} TLBP
# CHECK-NOT: # <MCInst #{{[0-9]+}} TLBP_MM
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01]
[mips] Correct the predicates for special nops, tlb ctrl instrs, software breakpoint and prefx. Reviewers: atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D44436 llvm-svn: 329905
2018-04-12 20:37:02 +08:00
# CHECK-NEXT: # <MCInst #{{[0-9]+}} TLBR
# CHECK-NOT: # <MCInst #{{[0-9]+}} TLBR_MM
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
tlbwi # CHECK: tlbwi # encoding: [0x42,0x00,0x00,0x02]
[mips] Correct the predicates for special nops, tlb ctrl instrs, software breakpoint and prefx. Reviewers: atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D44436 llvm-svn: 329905
2018-04-12 20:37:02 +08:00
# CHECK-NEXT: # <MCInst #{{[0-9]+}} TLBWI
# CHECK-NOT: # <MCInst #{{[0-9]+}} TLBWI_MM
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
tlbwr # CHECK: tlbwr # encoding: [0x42,0x00,0x00,0x06]
[mips] Correct the predicates for special nops, tlb ctrl instrs, software breakpoint and prefx. Reviewers: atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D44436 llvm-svn: 329905
2018-04-12 20:37:02 +08:00
# CHECK-NEXT: # <MCInst #{{[0-9]+}} TLBWR
# CHECK-NOT: # <MCInst #{{[0-9]+}} TLBWR_MM
Reland "[mips] Guard traps for microMIPS correctly" This is part of fixing the instruction predicates for MIPS. Reviewers: atanasyan, abeserminji Differential Revision: https://reviews.llvm.org/D44212 This patch relands r327409, hopefully without the problematic part of the tests that cause FileCheck to assert on the windows expensive checks bot. llvm-svn: 330741
2018-04-25 01:11:37 +08:00
tlt $15, $13 # CHECK: tlt $15, $13 # encoding: [0x01,0xed,0x00,0x32]
tlt $2, $19, 133 # CHECK: tlt $2, $19, 133 # encoding: [0x00,0x53,0x21,0x72]
tlti $14, -21059 # CHECK: tlti $14, -21059 # encoding: [0x05,0xca,0xad,0xbd]
tltiu $ra, -5076 # CHECK: tltiu $ra, -5076 # encoding: [0x07,0xeb,0xec,0x2c]
tltu $11, $16 # CHECK: tltu $11, $16 # encoding: [0x01,0x70,0x00,0x33]
tltu $16, $sp, 1016 # CHECK: tltu $16, $sp, 1016 # encoding: [0x02,0x1d,0xfe,0x33]
tne $6, $17 # CHECK: tne $6, $17 # encoding: [0x00,0xd1,0x00,0x36]
tne $7, $8, 885 # CHECK: tne $7, $8, 885 # encoding: [0x00,0xe8,0xdd,0x76]
tnei $12, -29647 # CHECK: tnei $12, -29647 # encoding: [0x05,0x8e,0x8c,0x31]
[mips] added support for trunc macro Author: obucina Reviewers: dsanders Differential Revision: http://reviews.llvm.org/D15745 llvm-svn: 261529
2016-02-23 00:00:23 +08:00
trunc.l.d $f23,$f23 # CHECK: trunc.l.d $f23, $f23 # encoding: [0x46,0x20,0xbd,0xc9]
trunc.l.s $f28,$f31 # CHECK: trunc.l.s $f28, $f31 # encoding: [0x46,0x00,0xff,0x09]
trunc.w.d $f22,$f15 # CHECK: trunc.w.d $f22, $f15 # encoding: [0x46,0x20,0x7d,0x8d]
[mips] Fix the predicates of round, ceiling, floor and trunc. Reviewers: atanasyan, abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D46691 llvm-svn: 332258
2018-05-15 00:26:50 +08:00
# CHECK: <MCInst #{{.*}} TRUNC_W_D64
[mips] added support for trunc macro Author: obucina Reviewers: dsanders Differential Revision: http://reviews.llvm.org/D15745 llvm-svn: 261529
2016-02-23 00:00:23 +08:00
trunc.w.s $f28,$f30 # CHECK: trunc.w.s $f28, $f30 # encoding: [0x46,0x00,0xf7,0x0d]
[mips] Fix the predicates of round, ceiling, floor and trunc. Reviewers: atanasyan, abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D46691 llvm-svn: 332258
2018-05-15 00:26:50 +08:00
# CHECK: <MCInst #{{.*}} TRUNC_W_S
[mips] added support for trunc macro Author: obucina Reviewers: dsanders Differential Revision: http://reviews.llvm.org/D15745 llvm-svn: 261529
2016-02-23 00:00:23 +08:00
trunc.w.d $f4,$f6,$4 # CHECK: trunc.w.d $f4, $f6 # encoding: [0x46,0x20,0x31,0x0d]
trunc.w.s $f4,$f6,$4 # CHECK: trunc.w.s $f4, $f6 # encoding: [0x46,0x00,0x31,0x0d]
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
xor $s2,$a0,$s8
[mips] [IAS] Add support for the XOR $reg,imm pseudo-instruction. Summary: This adds a MipsInstAlias which expands to XORi $reg,$reg,imm. For example, "xor $6, 0x3A" should be expanded to "xori $6, $6, 58". This should work for all MIPS ISAs. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8284 llvm-svn: 232473
2015-03-17 21:17:44 +08:00
xor $2, 4 # CHECK: xori $2, $2, 4 # encoding: [0x38,0x42,0x00,0x04]
[mips] Correct tests that are meant to test valid assembly. They were actually rejected by GAS. Summary: I've noticed a bug in my test generator script that caused 64-bit objects to be disassembled as if it were using the O32 ABI, giving the wrong register names. As a result, it generated assembly files that are rejected by GAS when assembling for the correct ABI. This was caused by the generator setting the ELF e_flags incorrectly before disassembling the object. This patch corrects the invalid tests that have already been committed by replacing the ABI-dependent register names with numeric registers. In addition to fixing the tests this allows the 32-bit and 64-bit ISA tests to be easily diffed to produce the invalid-*.s tests which test that instructions defined in later ISA's are not accepted. Depends on D3648 Reviewers: vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3649 llvm-svn: 208327
2014-05-08 23:17:29 +08:00
wsbh $k1,$9
[mips] Fix the definition of sync, synci Also, fix the disassembly of synci for microMIPS. Reviewers: abeserminji, smaksimovic, atanasyan Differential Revision: https://reviews.llvm.org/D45870 llvm-svn: 330810
2018-04-25 18:19:22 +08:00
synci -15842($a2) # CHECK: synci -15842($6) # encoding: [0x04,0xdf,0xc2,0x1e]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} SYNC
[mips] [IAS] Remove AssemblerPredicate's from RelocPIC and RelocStatic. Summary: These AssemblerPredicate's are unnecessary and actually make some instructions unusable when assembling pre-MIPS32 ISAs. For example, this was causing the IAS to reject the 'j' instruction for MIPS I-V. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8300 llvm-svn: 234398
2015-04-08 18:06:45 +08:00
1:
[mips] Weaken asm predicate for memory offsets The isMemWithSimmOffset predicate rejects relocations which is incorrect behaviour. Linkers and other tools should handle|warn|error when the field overflows. Reviewers: dsanders, vkalintiris Differential Revision: http://reviews.llvm.org/D20727 llvm-svn: 270995
2016-05-27 21:56:36 +08:00
# Check that we accept traditional %relocation(symbol) offsets for stores
# and loads, not just a sign 16 bit offset.
lui $2, %hi(g_8) # CHECK: encoding: [0x3c,0x02,A,A]
lb $3, %lo(g_8)($2) # CHECK: encoding: [0x80,0x43,A,A]
lh $3, %lo(g_8)($2) # CHECK: encoding: [0x84,0x43,A,A]
lhu $3, %lo(g_8)($2) # CHECK: encoding: [0x94,0x43,A,A]
lw $3, %lo(g_8)($2) # CHECK: encoding: [0x8c,0x43,A,A]
sb $3, %lo(g_8)($2) # CHECK: encoding: [0xa0,0x43,A,A]
sh $3, %lo(g_8)($2) # CHECK: encoding: [0xa4,0x43,A,A]
sw $3, %lo(g_8)($2) # CHECK: encoding: [0xac,0x43,A,A]
lwl $3, %lo(g_8)($2) # CHECK: encoding: [0x88,0x43,A,A]
lwr $3, %lo(g_8)($2) # CHECK: encoding: [0x98,0x43,A,A]
swl $3, %lo(g_8)($2) # CHECK: encoding: [0xa8,0x43,A,A]
swr $3, %lo(g_8)($2) # CHECK: encoding: [0xb8,0x43,A,A]
lwc1 $f0, %lo(g_8)($2) # CHECK: encoding: [0xc4,0x40,A,A]
ldc1 $f0, %lo(g_8)($2) # CHECK: encoding: [0xd4,0x40,A,A]
swc1 $f0, %lo(g_8)($2) # CHECK: encoding: [0xe4,0x40,A,A]
sdc1 $f0, %lo(g_8)($2) # CHECK: encoding: [0xf4,0x40,A,A]
lwu $3, %lo(g_8)($2) # CHECK: encoding: [0x9c,0x43,A,A]
ld $3, %lo(g_8)($2) # CHECK: encoding: [0xdc,0x43,A,A]
sd $3, %lo(g_8)($2) # CHECK: encoding: [0xfc,0x43,A,A]
ldl $3, %lo(g_8)($2) # CHECK: encoding: [0x68,0x43,A,A]
ldr $3, %lo(g_8)($2) # CHECK: encoding: [0x6c,0x43,A,A]
sdl $3, %lo(g_8)($2) # CHECK: encoding: [0xb0,0x43,A,A]
sdr $3, %lo(g_8)($2) # CHECK: encoding: [0xb4,0x43,A,A]
.type g_8,@object
.comm g_8,16,16