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llvm-project/llvm/test/MC/AArch64/ete-sysregs.s

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[AArch64] Define ETE and TRBE system registers Embedded Trace Extension and Trace Buffer Extension are optional future architecture extensions. (cf. https://developer.arm.com/architectures/cpu-architecture/a-profile/exploration-tools) Their system registers are documented here: https://developer.arm.com/docs/ddi0601/a ETE shares register names with ETM. One exception is the ETE TRCEXTINSELR0 register, which has the same encoding as the ETM TRCEXTINSELR register (but different semantics). This patch treats them as aliases: the assembler will accept both names, emitting identical encoding, and the disassembler will keep disassembling to TRCEXRINSELR. Differential Revision: https://reviews.llvm.org/D63707 llvm-svn: 367093
2019-07-26 17:19:08 +08:00
// ETE System registers
//
// RUN: llvm-mc -triple aarch64 -show-encoding < %s | FileCheck %s
// Read from system register
mrs x0, TRCRSR
mrs x0, TRCEXTINSELR
mrs x0, TRCEXTINSELR0
mrs x0, TRCEXTINSELR1
mrs x0, TRCEXTINSELR2
mrs x0, TRCEXTINSELR3
// CHECK: mrs x0, TRCRSR // encoding: [0x00,0x0a,0x31,0xd5]
[AArch64] Predictably disassemble system registers with the same encoding The registers TRCEXTINSELR and TRCEXTINSELR0 are distinct registers, defined by separate extension specifications (ETM and ETE, respectively), yet they use the same encoding in MSR/MRS. When performing a system register lookup by encoding, we would essentially return a random one, depending on the number, relative position in the TableGen file, whether the TableGen records for system registers are named or not, and, if they are named, depending on record (not register!) name as well. This patch works around the issue by explictly checking for the TRCEXTINSELR/TRCEXTINSELR0 encoding and always returning TRCEXTINSELR. Differential Revision: https://reviews.llvm.org/D74074
2020-02-07 19:38:46 +08:00
// CHECK: mrs x0, TRCEXTINSELR // encoding: [0x80,0x08,0x31,0xd5]
// CHECK: mrs x0, TRCEXTINSELR // encoding: [0x80,0x08,0x31,0xd5]
[AArch64] Define ETE and TRBE system registers Embedded Trace Extension and Trace Buffer Extension are optional future architecture extensions. (cf. https://developer.arm.com/architectures/cpu-architecture/a-profile/exploration-tools) Their system registers are documented here: https://developer.arm.com/docs/ddi0601/a ETE shares register names with ETM. One exception is the ETE TRCEXTINSELR0 register, which has the same encoding as the ETM TRCEXTINSELR register (but different semantics). This patch treats them as aliases: the assembler will accept both names, emitting identical encoding, and the disassembler will keep disassembling to TRCEXRINSELR. Differential Revision: https://reviews.llvm.org/D63707 llvm-svn: 367093
2019-07-26 17:19:08 +08:00
// CHECK: mrs x0, TRCEXTINSELR1 // encoding: [0x80,0x09,0x31,0xd5]
// CHECK: mrs x0, TRCEXTINSELR2 // encoding: [0x80,0x0a,0x31,0xd5]
// CHECK: mrs x0, TRCEXTINSELR3 // encoding: [0x80,0x0b,0x31,0xd5]
// Write to system register
msr TRCRSR, x0
msr TRCEXTINSELR, x0
msr TRCEXTINSELR0, x0
msr TRCEXTINSELR1, x0
msr TRCEXTINSELR2, x0
msr TRCEXTINSELR3, x0
// CHECK: msr TRCRSR, x0 // encoding: [0x00,0x0a,0x11,0xd5]
[AArch64] Predictably disassemble system registers with the same encoding The registers TRCEXTINSELR and TRCEXTINSELR0 are distinct registers, defined by separate extension specifications (ETM and ETE, respectively), yet they use the same encoding in MSR/MRS. When performing a system register lookup by encoding, we would essentially return a random one, depending on the number, relative position in the TableGen file, whether the TableGen records for system registers are named or not, and, if they are named, depending on record (not register!) name as well. This patch works around the issue by explictly checking for the TRCEXTINSELR/TRCEXTINSELR0 encoding and always returning TRCEXTINSELR. Differential Revision: https://reviews.llvm.org/D74074
2020-02-07 19:38:46 +08:00
// CHECK: msr TRCEXTINSELR, x0 // encoding: [0x80,0x08,0x11,0xd5]
// CHECK: msr TRCEXTINSELR, x0 // encoding: [0x80,0x08,0x11,0xd5]
[AArch64] Define ETE and TRBE system registers Embedded Trace Extension and Trace Buffer Extension are optional future architecture extensions. (cf. https://developer.arm.com/architectures/cpu-architecture/a-profile/exploration-tools) Their system registers are documented here: https://developer.arm.com/docs/ddi0601/a ETE shares register names with ETM. One exception is the ETE TRCEXTINSELR0 register, which has the same encoding as the ETM TRCEXTINSELR register (but different semantics). This patch treats them as aliases: the assembler will accept both names, emitting identical encoding, and the disassembler will keep disassembling to TRCEXRINSELR. Differential Revision: https://reviews.llvm.org/D63707 llvm-svn: 367093
2019-07-26 17:19:08 +08:00
// CHECK: msr TRCEXTINSELR1, x0 // encoding: [0x80,0x09,0x11,0xd5]
// CHECK: msr TRCEXTINSELR2, x0 // encoding: [0x80,0x0a,0x11,0xd5]
// CHECK: msr TRCEXTINSELR3, x0 // encoding: [0x80,0x0b,0x11,0xd5]