2018-12-06 23:39:17 +08:00
|
|
|
// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.3a -o - %s 2>&1 | \
|
|
|
|
// RUN: FileCheck --check-prefixes=CHECK,ALL %s
|
2017-08-11 21:14:00 +08:00
|
|
|
|
[AArch64] Emit HINT instead of PAC insns in Armv8.2-A or below
Summary:
The Pointer Authentication Extension (PAC) was added in Armv8.3-A. Some
instructions are implemented in the HINT space to allow compiling code
common to CPUs regardless of whether they feature PAC or not, and still
benefit from PAC protection in the PAC-enabled CPUs.
The 8.3-specific mnemonics were currently enabled in any architecture, and
LLVM was emitting them in assembly files when PAC code generation was
enabled. This was ok for compilations where both LLVM codegen and the
integrated assembler were used. However, the LLVM codegen was not
compatible with other assemblers (e.g. GAS). Given the fact that the
approach from these assemblers (i.e. to disallow Armv8.3-A mnemonics if
compiling for Armv8.2-A or lower) is entirely reasonable, this patch makes
LLVM to emit HINT when building for Armv8.2-A and below, instead of
PACIASP, AUTIASP and friends. Then, LLVM assembly should be compatible
with other assemblers.
Reviewers: samparker, chill, LukeCheeseman
Subscribers: kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D71658
2020-01-11 01:51:21 +08:00
|
|
|
// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding %s -o - > %t.1 2>%t.2
|
[AArch64] Allow PAC mnemonics in the HINT space with PAC disabled
Summary:
It is important to emit HINT instructions instead of PAC ones when
PAC is disabled. This allows compatibility with other assemblers
(e.g. GAS). This was implemented in commit da33762de853.
Still, developers of assembly code will want to write code that is
compatible with both pre- and post-PAC CPUs. They could use HINT
mnemonics, but the new mnemonics are a lot more readable (e.g.
paciaz instead of hint #24), and they will result in the same
encodings. So, while LLVM should not *emit* the new mnemonics when
PAC is disabled, this patch will at least make LLVM *accept*
assembly code that uses them.
Reviewers: danielkiss, chill, olista01, LukeCheeseman, simon_tatham
Subscribers: kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D78372
2020-03-10 23:05:49 +08:00
|
|
|
// RUN: FileCheck --check-prefixes=NO83,ALL %s < %t.1
|
2018-12-06 23:39:17 +08:00
|
|
|
// RUN: FileCheck --check-prefix=CHECK-REQ %s < %t.2
|
|
|
|
|
|
|
|
// ALL: .text
|
2017-08-11 21:14:00 +08:00
|
|
|
mrs x0, apiakeylo_el1
|
|
|
|
mrs x0, apiakeyhi_el1
|
|
|
|
mrs x0, apibkeylo_el1
|
|
|
|
mrs x0, apibkeyhi_el1
|
|
|
|
mrs x0, apdakeylo_el1
|
|
|
|
mrs x0, apdakeyhi_el1
|
|
|
|
mrs x0, apdbkeylo_el1
|
|
|
|
mrs x0, apdbkeyhi_el1
|
|
|
|
mrs x0, apgakeylo_el1
|
|
|
|
mrs x0, apgakeyhi_el1
|
2018-12-06 23:39:17 +08:00
|
|
|
// ALL-EMPTY:
|
|
|
|
// ALL-EMPTY:
|
|
|
|
// CHECK-NEXT: mrs x0, APIAKeyLo_EL1 // encoding: [0x00,0x21,0x38,0xd5]
|
|
|
|
// CHECK-NEXT: mrs x0, APIAKeyHi_EL1 // encoding: [0x20,0x21,0x38,0xd5]
|
|
|
|
// CHECK-NEXT: mrs x0, APIBKeyLo_EL1 // encoding: [0x40,0x21,0x38,0xd5]
|
|
|
|
// CHECK-NEXT: mrs x0, APIBKeyHi_EL1 // encoding: [0x60,0x21,0x38,0xd5]
|
|
|
|
// CHECK-NEXT: mrs x0, APDAKeyLo_EL1 // encoding: [0x00,0x22,0x38,0xd5]
|
|
|
|
// CHECK-NEXT: mrs x0, APDAKeyHi_EL1 // encoding: [0x20,0x22,0x38,0xd5]
|
|
|
|
// CHECK-NEXT: mrs x0, APDBKeyLo_EL1 // encoding: [0x40,0x22,0x38,0xd5]
|
|
|
|
// CHECK-NEXT: mrs x0, APDBKeyHi_EL1 // encoding: [0x60,0x22,0x38,0xd5]
|
|
|
|
// CHECK-NEXT: mrs x0, APGAKeyLo_EL1 // encoding: [0x00,0x23,0x38,0xd5]
|
|
|
|
// CHECK-NEXT: mrs x0, APGAKeyHi_EL1 // encoding: [0x20,0x23,0x38,0xd5]
|
2017-08-11 21:14:00 +08:00
|
|
|
|
|
|
|
// CHECK-REQ: error: expected readable system register
|
2018-12-06 23:39:17 +08:00
|
|
|
// CHECK-REQ-NEXT: mrs x0, apiakeylo_el1
|
2017-08-11 21:14:00 +08:00
|
|
|
// CHECK-REQ: error: expected readable system register
|
2018-12-06 23:39:17 +08:00
|
|
|
// CHECK-REQ-NEXT: mrs x0, apiakeyhi_el1
|
2017-08-11 21:14:00 +08:00
|
|
|
// CHECK-REQ: error: expected readable system register
|
2018-12-06 23:39:17 +08:00
|
|
|
// CHECK-REQ-NEXT: mrs x0, apibkeylo_el1
|
2017-08-11 21:14:00 +08:00
|
|
|
// CHECK-REQ: error: expected readable system register
|
2018-12-06 23:39:17 +08:00
|
|
|
// CHECK-REQ-NEXT: mrs x0, apibkeyhi_el1
|
2017-08-11 21:14:00 +08:00
|
|
|
// CHECK-REQ: error: expected readable system register
|
2018-12-06 23:39:17 +08:00
|
|
|
// CHECK-REQ-NEXT: mrs x0, apdakeylo_el1
|
2017-08-11 21:14:00 +08:00
|
|
|
// CHECK-REQ: error: expected readable system register
|
2018-12-06 23:39:17 +08:00
|
|
|
// CHECK-REQ-NEXT: mrs x0, apdakeyhi_el1
|
2017-08-11 21:14:00 +08:00
|
|
|
// CHECK-REQ: error: expected readable system register
|
2018-12-06 23:39:17 +08:00
|
|
|
// CHECK-REQ-NEXT: mrs x0, apdbkeylo_el1
|
2017-08-11 21:14:00 +08:00
|
|
|
// CHECK-REQ: error: expected readable system register
|
2018-12-06 23:39:17 +08:00
|
|
|
// CHECK-REQ-NEXT: mrs x0, apdbkeyhi_el1
|
2017-08-11 21:14:00 +08:00
|
|
|
// CHECK-REQ: error: expected readable system register
|
2018-12-06 23:39:17 +08:00
|
|
|
// CHECK-REQ-NEXT: mrs x0, apgakeylo_el1
|
2017-08-11 21:14:00 +08:00
|
|
|
// CHECK-REQ: error: expected readable system register
|
2018-12-06 23:39:17 +08:00
|
|
|
// CHECK-REQ-NEXT: mrs x0, apgakeyhi_el1
|
2017-08-11 21:14:00 +08:00
|
|
|
|
|
|
|
msr apiakeylo_el1, x0
|
|
|
|
msr apiakeyhi_el1, x0
|
|
|
|
msr apibkeylo_el1, x0
|
|
|
|
msr apibkeyhi_el1, x0
|
|
|
|
msr apdakeylo_el1, x0
|
|
|
|
msr apdakeyhi_el1, x0
|
|
|
|
msr apdbkeylo_el1, x0
|
|
|
|
msr apdbkeyhi_el1, x0
|
|
|
|
msr apgakeylo_el1, x0
|
|
|
|
msr apgakeyhi_el1, x0
|
2018-12-06 23:39:17 +08:00
|
|
|
// ALL-EMPTY:
|
|
|
|
// ALL-EMPTY:
|
|
|
|
// CHECK-NEXT: msr APIAKeyLo_EL1, x0 // encoding: [0x00,0x21,0x18,0xd5]
|
|
|
|
// CHECK-NEXT: msr APIAKeyHi_EL1, x0 // encoding: [0x20,0x21,0x18,0xd5]
|
|
|
|
// CHECK-NEXT: msr APIBKeyLo_EL1, x0 // encoding: [0x40,0x21,0x18,0xd5]
|
|
|
|
// CHECK-NEXT: msr APIBKeyHi_EL1, x0 // encoding: [0x60,0x21,0x18,0xd5]
|
|
|
|
// CHECK-NEXT: msr APDAKeyLo_EL1, x0 // encoding: [0x00,0x22,0x18,0xd5]
|
|
|
|
// CHECK-NEXT: msr APDAKeyHi_EL1, x0 // encoding: [0x20,0x22,0x18,0xd5]
|
|
|
|
// CHECK-NEXT: msr APDBKeyLo_EL1, x0 // encoding: [0x40,0x22,0x18,0xd5]
|
|
|
|
// CHECK-NEXT: msr APDBKeyHi_EL1, x0 // encoding: [0x60,0x22,0x18,0xd5]
|
|
|
|
// CHECK-NEXT: msr APGAKeyLo_EL1, x0 // encoding: [0x00,0x23,0x18,0xd5]
|
|
|
|
// CHECK-NEXT: msr APGAKeyHi_EL1, x0 // encoding: [0x20,0x23,0x18,0xd5]
|
2017-08-11 21:14:00 +08:00
|
|
|
|
|
|
|
// CHECK-REQ: error: expected writable system register or pstate
|
2018-12-06 23:39:17 +08:00
|
|
|
// CHECK-REQ-NEXT: msr apiakeylo_el1, x0
|
2017-08-11 21:14:00 +08:00
|
|
|
// CHECK-REQ: error: expected writable system register or pstate
|
2018-12-06 23:39:17 +08:00
|
|
|
// CHECK-REQ-NEXT: msr apiakeyhi_el1, x0
|
2017-08-11 21:14:00 +08:00
|
|
|
// CHECK-REQ: error: expected writable system register or pstate
|
2018-12-06 23:39:17 +08:00
|
|
|
// CHECK-REQ-NEXT: msr apibkeylo_el1, x0
|
2017-08-11 21:14:00 +08:00
|
|
|
// CHECK-REQ: error: expected writable system register or pstate
|
2018-12-06 23:39:17 +08:00
|
|
|
// CHECK-REQ-NEXT: msr apibkeyhi_el1, x0
|
2017-08-11 21:14:00 +08:00
|
|
|
// CHECK-REQ: error: expected writable system register or pstate
|
2018-12-06 23:39:17 +08:00
|
|
|
// CHECK-REQ-NEXT: msr apdakeylo_el1, x0
|
2017-08-11 21:14:00 +08:00
|
|
|
// CHECK-REQ: error: expected writable system register or pstate
|
2018-12-06 23:39:17 +08:00
|
|
|
// CHECK-REQ-NEXT: msr apdakeyhi_el1, x0
|
2017-08-11 21:14:00 +08:00
|
|
|
// CHECK-REQ: error: expected writable system register or pstate
|
2018-12-06 23:39:17 +08:00
|
|
|
// CHECK-REQ-NEXT: msr apdbkeylo_el1, x0
|
2017-08-11 21:14:00 +08:00
|
|
|
// CHECK-REQ: error: expected writable system register or pstate
|
2018-12-06 23:39:17 +08:00
|
|
|
// CHECK-REQ-NEXT: msr apdbkeyhi_el1, x0
|
2017-08-11 21:14:00 +08:00
|
|
|
// CHECK-REQ: error: expected writable system register or pstate
|
2018-12-06 23:39:17 +08:00
|
|
|
// CHECK-REQ-NEXT: msr apgakeylo_el1, x0
|
2017-08-11 21:14:00 +08:00
|
|
|
// CHECK-REQ: error: expected writable system register or pstate
|
2018-12-06 23:39:17 +08:00
|
|
|
// CHECK-REQ-NEXT: msr apgakeyhi_el1, x0
|
2017-08-11 21:14:00 +08:00
|
|
|
|
2018-12-06 23:39:17 +08:00
|
|
|
// ALL-EMPTY:
|
|
|
|
// ALL-EMPTY:
|
2017-08-11 21:14:00 +08:00
|
|
|
paciasp
|
2018-12-06 23:39:17 +08:00
|
|
|
// CHECK-NEXT: paciasp // encoding: [0x3f,0x23,0x03,0xd5]
|
[AArch64] Allow PAC mnemonics in the HINT space with PAC disabled
Summary:
It is important to emit HINT instructions instead of PAC ones when
PAC is disabled. This allows compatibility with other assemblers
(e.g. GAS). This was implemented in commit da33762de853.
Still, developers of assembly code will want to write code that is
compatible with both pre- and post-PAC CPUs. They could use HINT
mnemonics, but the new mnemonics are a lot more readable (e.g.
paciaz instead of hint #24), and they will result in the same
encodings. So, while LLVM should not *emit* the new mnemonics when
PAC is disabled, this patch will at least make LLVM *accept*
assembly code that uses them.
Reviewers: danielkiss, chill, olista01, LukeCheeseman, simon_tatham
Subscribers: kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D78372
2020-03-10 23:05:49 +08:00
|
|
|
// NO83-NEXT: hint #25 // encoding: [0x3f,0x23,0x03,0xd5]
|
2017-08-11 21:14:00 +08:00
|
|
|
autiasp
|
2018-12-06 23:39:17 +08:00
|
|
|
// CHECK-NEXT: autiasp // encoding: [0xbf,0x23,0x03,0xd5]
|
[AArch64] Allow PAC mnemonics in the HINT space with PAC disabled
Summary:
It is important to emit HINT instructions instead of PAC ones when
PAC is disabled. This allows compatibility with other assemblers
(e.g. GAS). This was implemented in commit da33762de853.
Still, developers of assembly code will want to write code that is
compatible with both pre- and post-PAC CPUs. They could use HINT
mnemonics, but the new mnemonics are a lot more readable (e.g.
paciaz instead of hint #24), and they will result in the same
encodings. So, while LLVM should not *emit* the new mnemonics when
PAC is disabled, this patch will at least make LLVM *accept*
assembly code that uses them.
Reviewers: danielkiss, chill, olista01, LukeCheeseman, simon_tatham
Subscribers: kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D78372
2020-03-10 23:05:49 +08:00
|
|
|
// NO83-NEXT: hint #29 // encoding: [0xbf,0x23,0x03,0xd5]
|
2017-08-11 21:14:00 +08:00
|
|
|
paciaz
|
2018-12-06 23:39:17 +08:00
|
|
|
// CHECK-NEXT: paciaz // encoding: [0x1f,0x23,0x03,0xd5]
|
[AArch64] Allow PAC mnemonics in the HINT space with PAC disabled
Summary:
It is important to emit HINT instructions instead of PAC ones when
PAC is disabled. This allows compatibility with other assemblers
(e.g. GAS). This was implemented in commit da33762de853.
Still, developers of assembly code will want to write code that is
compatible with both pre- and post-PAC CPUs. They could use HINT
mnemonics, but the new mnemonics are a lot more readable (e.g.
paciaz instead of hint #24), and they will result in the same
encodings. So, while LLVM should not *emit* the new mnemonics when
PAC is disabled, this patch will at least make LLVM *accept*
assembly code that uses them.
Reviewers: danielkiss, chill, olista01, LukeCheeseman, simon_tatham
Subscribers: kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D78372
2020-03-10 23:05:49 +08:00
|
|
|
// NO83-NEXT: hint #24 // encoding: [0x1f,0x23,0x03,0xd5]
|
2017-08-11 21:14:00 +08:00
|
|
|
autiaz
|
2018-12-06 23:39:17 +08:00
|
|
|
// CHECK-NEXT: autiaz // encoding: [0x9f,0x23,0x03,0xd5]
|
[AArch64] Allow PAC mnemonics in the HINT space with PAC disabled
Summary:
It is important to emit HINT instructions instead of PAC ones when
PAC is disabled. This allows compatibility with other assemblers
(e.g. GAS). This was implemented in commit da33762de853.
Still, developers of assembly code will want to write code that is
compatible with both pre- and post-PAC CPUs. They could use HINT
mnemonics, but the new mnemonics are a lot more readable (e.g.
paciaz instead of hint #24), and they will result in the same
encodings. So, while LLVM should not *emit* the new mnemonics when
PAC is disabled, this patch will at least make LLVM *accept*
assembly code that uses them.
Reviewers: danielkiss, chill, olista01, LukeCheeseman, simon_tatham
Subscribers: kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D78372
2020-03-10 23:05:49 +08:00
|
|
|
// NO83-NEXT: hint #28 // encoding: [0x9f,0x23,0x03,0xd5]
|
2017-08-11 21:14:00 +08:00
|
|
|
pacia1716
|
2018-12-06 23:39:17 +08:00
|
|
|
// CHECK-NEXT: pacia1716 // encoding: [0x1f,0x21,0x03,0xd5]
|
[AArch64] Allow PAC mnemonics in the HINT space with PAC disabled
Summary:
It is important to emit HINT instructions instead of PAC ones when
PAC is disabled. This allows compatibility with other assemblers
(e.g. GAS). This was implemented in commit da33762de853.
Still, developers of assembly code will want to write code that is
compatible with both pre- and post-PAC CPUs. They could use HINT
mnemonics, but the new mnemonics are a lot more readable (e.g.
paciaz instead of hint #24), and they will result in the same
encodings. So, while LLVM should not *emit* the new mnemonics when
PAC is disabled, this patch will at least make LLVM *accept*
assembly code that uses them.
Reviewers: danielkiss, chill, olista01, LukeCheeseman, simon_tatham
Subscribers: kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D78372
2020-03-10 23:05:49 +08:00
|
|
|
// NO83-NEXT: hint #8 // encoding: [0x1f,0x21,0x03,0xd5]
|
2017-08-11 21:14:00 +08:00
|
|
|
autia1716
|
2018-12-06 23:39:17 +08:00
|
|
|
// CHECK-NEXT: autia1716 // encoding: [0x9f,0x21,0x03,0xd5]
|
[AArch64] Allow PAC mnemonics in the HINT space with PAC disabled
Summary:
It is important to emit HINT instructions instead of PAC ones when
PAC is disabled. This allows compatibility with other assemblers
(e.g. GAS). This was implemented in commit da33762de853.
Still, developers of assembly code will want to write code that is
compatible with both pre- and post-PAC CPUs. They could use HINT
mnemonics, but the new mnemonics are a lot more readable (e.g.
paciaz instead of hint #24), and they will result in the same
encodings. So, while LLVM should not *emit* the new mnemonics when
PAC is disabled, this patch will at least make LLVM *accept*
assembly code that uses them.
Reviewers: danielkiss, chill, olista01, LukeCheeseman, simon_tatham
Subscribers: kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D78372
2020-03-10 23:05:49 +08:00
|
|
|
// NO83-NEXT: hint #12 // encoding: [0x9f,0x21,0x03,0xd5]
|
2017-08-11 21:14:00 +08:00
|
|
|
pacibsp
|
2018-12-06 23:39:17 +08:00
|
|
|
// CHECK-NEXT: pacibsp // encoding: [0x7f,0x23,0x03,0xd5]
|
[AArch64] Allow PAC mnemonics in the HINT space with PAC disabled
Summary:
It is important to emit HINT instructions instead of PAC ones when
PAC is disabled. This allows compatibility with other assemblers
(e.g. GAS). This was implemented in commit da33762de853.
Still, developers of assembly code will want to write code that is
compatible with both pre- and post-PAC CPUs. They could use HINT
mnemonics, but the new mnemonics are a lot more readable (e.g.
paciaz instead of hint #24), and they will result in the same
encodings. So, while LLVM should not *emit* the new mnemonics when
PAC is disabled, this patch will at least make LLVM *accept*
assembly code that uses them.
Reviewers: danielkiss, chill, olista01, LukeCheeseman, simon_tatham
Subscribers: kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D78372
2020-03-10 23:05:49 +08:00
|
|
|
// NO83-NEXT: hint #27 // encoding: [0x7f,0x23,0x03,0xd5]
|
2017-08-11 21:14:00 +08:00
|
|
|
autibsp
|
2018-12-06 23:39:17 +08:00
|
|
|
// CHECK-NEXT: autibsp // encoding: [0xff,0x23,0x03,0xd5]
|
[AArch64] Allow PAC mnemonics in the HINT space with PAC disabled
Summary:
It is important to emit HINT instructions instead of PAC ones when
PAC is disabled. This allows compatibility with other assemblers
(e.g. GAS). This was implemented in commit da33762de853.
Still, developers of assembly code will want to write code that is
compatible with both pre- and post-PAC CPUs. They could use HINT
mnemonics, but the new mnemonics are a lot more readable (e.g.
paciaz instead of hint #24), and they will result in the same
encodings. So, while LLVM should not *emit* the new mnemonics when
PAC is disabled, this patch will at least make LLVM *accept*
assembly code that uses them.
Reviewers: danielkiss, chill, olista01, LukeCheeseman, simon_tatham
Subscribers: kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D78372
2020-03-10 23:05:49 +08:00
|
|
|
// NO83-NEXT: hint #31 // encoding: [0xff,0x23,0x03,0xd5]
|
2017-08-11 21:14:00 +08:00
|
|
|
pacibz
|
2018-12-06 23:39:17 +08:00
|
|
|
// CHECK-NEXT: pacibz // encoding: [0x5f,0x23,0x03,0xd5]
|
[AArch64] Allow PAC mnemonics in the HINT space with PAC disabled
Summary:
It is important to emit HINT instructions instead of PAC ones when
PAC is disabled. This allows compatibility with other assemblers
(e.g. GAS). This was implemented in commit da33762de853.
Still, developers of assembly code will want to write code that is
compatible with both pre- and post-PAC CPUs. They could use HINT
mnemonics, but the new mnemonics are a lot more readable (e.g.
paciaz instead of hint #24), and they will result in the same
encodings. So, while LLVM should not *emit* the new mnemonics when
PAC is disabled, this patch will at least make LLVM *accept*
assembly code that uses them.
Reviewers: danielkiss, chill, olista01, LukeCheeseman, simon_tatham
Subscribers: kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D78372
2020-03-10 23:05:49 +08:00
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|
|
// NO83-NEXT: hint #26 // encoding: [0x5f,0x23,0x03,0xd5]
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2017-08-11 21:14:00 +08:00
|
|
|
autibz
|
2018-12-06 23:39:17 +08:00
|
|
|
// CHECK-NEXT: autibz // encoding: [0xdf,0x23,0x03,0xd5]
|
[AArch64] Allow PAC mnemonics in the HINT space with PAC disabled
Summary:
It is important to emit HINT instructions instead of PAC ones when
PAC is disabled. This allows compatibility with other assemblers
(e.g. GAS). This was implemented in commit da33762de853.
Still, developers of assembly code will want to write code that is
compatible with both pre- and post-PAC CPUs. They could use HINT
mnemonics, but the new mnemonics are a lot more readable (e.g.
paciaz instead of hint #24), and they will result in the same
encodings. So, while LLVM should not *emit* the new mnemonics when
PAC is disabled, this patch will at least make LLVM *accept*
assembly code that uses them.
Reviewers: danielkiss, chill, olista01, LukeCheeseman, simon_tatham
Subscribers: kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D78372
2020-03-10 23:05:49 +08:00
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|
|
// NO83-NEXT: hint #30 // encoding: [0xdf,0x23,0x03,0xd5]
|
2017-08-11 21:14:00 +08:00
|
|
|
pacib1716
|
2018-12-06 23:39:17 +08:00
|
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// CHECK-NEXT: pacib1716 // encoding: [0x5f,0x21,0x03,0xd5]
|
[AArch64] Allow PAC mnemonics in the HINT space with PAC disabled
Summary:
It is important to emit HINT instructions instead of PAC ones when
PAC is disabled. This allows compatibility with other assemblers
(e.g. GAS). This was implemented in commit da33762de853.
Still, developers of assembly code will want to write code that is
compatible with both pre- and post-PAC CPUs. They could use HINT
mnemonics, but the new mnemonics are a lot more readable (e.g.
paciaz instead of hint #24), and they will result in the same
encodings. So, while LLVM should not *emit* the new mnemonics when
PAC is disabled, this patch will at least make LLVM *accept*
assembly code that uses them.
Reviewers: danielkiss, chill, olista01, LukeCheeseman, simon_tatham
Subscribers: kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D78372
2020-03-10 23:05:49 +08:00
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// NO83-NEXT: hint #10 // encoding: [0x5f,0x21,0x03,0xd5]
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2017-08-11 21:14:00 +08:00
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autib1716
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2018-12-06 23:39:17 +08:00
|
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// CHECK-NEXT: autib1716 // encoding: [0xdf,0x21,0x03,0xd5]
|
[AArch64] Allow PAC mnemonics in the HINT space with PAC disabled
Summary:
It is important to emit HINT instructions instead of PAC ones when
PAC is disabled. This allows compatibility with other assemblers
(e.g. GAS). This was implemented in commit da33762de853.
Still, developers of assembly code will want to write code that is
compatible with both pre- and post-PAC CPUs. They could use HINT
mnemonics, but the new mnemonics are a lot more readable (e.g.
paciaz instead of hint #24), and they will result in the same
encodings. So, while LLVM should not *emit* the new mnemonics when
PAC is disabled, this patch will at least make LLVM *accept*
assembly code that uses them.
Reviewers: danielkiss, chill, olista01, LukeCheeseman, simon_tatham
Subscribers: kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D78372
2020-03-10 23:05:49 +08:00
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// NO83-NEXT: hint #14 // encoding: [0xdf,0x21,0x03,0xd5]
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2017-08-11 21:14:00 +08:00
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xpaclri
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[AArch64] Emit HINT instead of PAC insns in Armv8.2-A or below
Summary:
The Pointer Authentication Extension (PAC) was added in Armv8.3-A. Some
instructions are implemented in the HINT space to allow compiling code
common to CPUs regardless of whether they feature PAC or not, and still
benefit from PAC protection in the PAC-enabled CPUs.
The 8.3-specific mnemonics were currently enabled in any architecture, and
LLVM was emitting them in assembly files when PAC code generation was
enabled. This was ok for compilations where both LLVM codegen and the
integrated assembler were used. However, the LLVM codegen was not
compatible with other assemblers (e.g. GAS). Given the fact that the
approach from these assemblers (i.e. to disallow Armv8.3-A mnemonics if
compiling for Armv8.2-A or lower) is entirely reasonable, this patch makes
LLVM to emit HINT when building for Armv8.2-A and below, instead of
PACIASP, AUTIASP and friends. Then, LLVM assembly should be compatible
with other assemblers.
Reviewers: samparker, chill, LukeCheeseman
Subscribers: kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D71658
2020-01-11 01:51:21 +08:00
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// CHECK-NEXT: xpaclri // encoding: [0xff,0x20,0x03,0xd5]
|
[AArch64] Allow PAC mnemonics in the HINT space with PAC disabled
Summary:
It is important to emit HINT instructions instead of PAC ones when
PAC is disabled. This allows compatibility with other assemblers
(e.g. GAS). This was implemented in commit da33762de853.
Still, developers of assembly code will want to write code that is
compatible with both pre- and post-PAC CPUs. They could use HINT
mnemonics, but the new mnemonics are a lot more readable (e.g.
paciaz instead of hint #24), and they will result in the same
encodings. So, while LLVM should not *emit* the new mnemonics when
PAC is disabled, this patch will at least make LLVM *accept*
assembly code that uses them.
Reviewers: danielkiss, chill, olista01, LukeCheeseman, simon_tatham
Subscribers: kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D78372
2020-03-10 23:05:49 +08:00
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|
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// NO83-NEXT: hint #7 // encoding: [0xff,0x20,0x03,0xd5]
|
2017-08-11 21:14:00 +08:00
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2018-12-06 23:39:17 +08:00
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// ALL-EMPTY:
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2017-08-11 21:14:00 +08:00
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pacia x0, x1
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2018-12-06 23:39:17 +08:00
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// CHECK-NEXT: pacia x0, x1 // encoding: [0x20,0x00,0xc1,0xda]
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// CHECK-REQ-NEXT: ^
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// CHECK-REQ-NEXT: error: instruction requires: pa
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// CHECK-REQ-NEXT: pacia x0, x1
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2017-08-11 21:14:00 +08:00
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autia x0, x1
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2018-12-06 23:39:17 +08:00
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// CHECK-NEXT: autia x0, x1 // encoding: [0x20,0x10,0xc1,0xda]
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// CHECK-REQ: error: instruction requires: pa
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// CHECK-REQ-NEXT: autia x0, x1
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2017-08-11 21:14:00 +08:00
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pacda x0, x1
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2018-12-06 23:39:17 +08:00
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// CHECK-NEXT: pacda x0, x1 // encoding: [0x20,0x08,0xc1,0xda]
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// CHECK-REQ: error: instruction requires: pa
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// CHECK-REQ-NEXT: pacda x0, x1
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2017-08-11 21:14:00 +08:00
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autda x0, x1
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2018-12-06 23:39:17 +08:00
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// CHECK-NEXT: autda x0, x1 // encoding: [0x20,0x18,0xc1,0xda]
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// CHECK-REQ: error: instruction requires: pa
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// CHECK-REQ-NEXT: autda x0, x1
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2017-08-11 21:14:00 +08:00
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pacib x0, x1
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2018-12-06 23:39:17 +08:00
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// CHECK-NEXT: pacib x0, x1 // encoding: [0x20,0x04,0xc1,0xda]
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// CHECK-REQ: error: instruction requires: pa
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// CHECK-REQ-NEXT: pacib x0, x1
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2017-08-11 21:14:00 +08:00
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autib x0, x1
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2018-12-06 23:39:17 +08:00
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// CHECK-NEXT: autib x0, x1 // encoding: [0x20,0x14,0xc1,0xda]
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// CHECK-REQ: error: instruction requires: pa
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// CHECK-REQ-NEXT: autib x0, x1
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2017-08-11 21:14:00 +08:00
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pacdb x0, x1
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2018-12-06 23:39:17 +08:00
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// CHECK-NEXT: pacdb x0, x1 // encoding: [0x20,0x0c,0xc1,0xda]
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// CHECK-REQ: error: instruction requires: pa
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// CHECK-REQ-NEXT: pacdb x0, x1
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2017-08-11 21:14:00 +08:00
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autdb x0, x1
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2018-12-06 23:39:17 +08:00
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// CHECK-NEXT: autdb x0, x1 // encoding: [0x20,0x1c,0xc1,0xda]
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// CHECK-REQ: error: instruction requires: pa
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// CHECK-REQ-NEXT: autdb x0, x1
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2017-08-11 21:14:00 +08:00
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pacga x0, x1, x2
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2018-12-06 23:39:17 +08:00
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// CHECK-NEXT: pacga x0, x1, x2 // encoding: [0x20,0x30,0xc2,0x9a]
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// CHECK-REQ: error: instruction requires: pa
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// CHECK-REQ-NEXT: pacga x0, x1, x2
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2017-08-11 21:14:00 +08:00
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paciza x0
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2018-12-06 23:39:17 +08:00
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// CHECK-NEXT: paciza x0 // encoding: [0xe0,0x23,0xc1,0xda]
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// CHECK-REQ: error: instruction requires: pa
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// CHECK-REQ-NEXT: paciza x0
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2017-08-11 21:14:00 +08:00
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autiza x0
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2018-12-06 23:39:17 +08:00
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// CHECK-NEXT: autiza x0 // encoding: [0xe0,0x33,0xc1,0xda]
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// CHECK-REQ: error: instruction requires: pa
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// CHECK-REQ-NEXT: autiza x0
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2017-08-11 21:14:00 +08:00
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pacdza x0
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2018-12-06 23:39:17 +08:00
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// CHECK-NEXT: pacdza x0 // encoding: [0xe0,0x2b,0xc1,0xda]
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// CHECK-REQ: error: instruction requires: pa
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// CHECK-REQ-NEXT: pacdza x0
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2017-08-11 21:14:00 +08:00
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autdza x0
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2018-12-06 23:39:17 +08:00
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// CHECK-NEXT: autdza x0 // encoding: [0xe0,0x3b,0xc1,0xda]
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// CHECK-REQ: error: instruction requires: pa
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// CHECK-REQ-NEXT: autdza x0
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2017-08-11 21:14:00 +08:00
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pacizb x0
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2018-12-06 23:39:17 +08:00
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// CHECK-NEXT: pacizb x0 // encoding: [0xe0,0x27,0xc1,0xda]
|
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// CHECK-REQ: error: instruction requires: pa
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// CHECK-REQ-NEXT: pacizb x0
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2017-08-11 21:14:00 +08:00
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autizb x0
|
2018-12-06 23:39:17 +08:00
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// CHECK-NEXT: autizb x0 // encoding: [0xe0,0x37,0xc1,0xda]
|
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// CHECK-REQ: error: instruction requires: pa
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// CHECK-REQ-NEXT: autizb x0
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2017-08-11 21:14:00 +08:00
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pacdzb x0
|
2018-12-06 23:39:17 +08:00
|
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// CHECK-NEXT: pacdzb x0 // encoding: [0xe0,0x2f,0xc1,0xda]
|
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// CHECK-REQ: error: instruction requires: pa
|
|
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// CHECK-REQ-NEXT: pacdzb x0
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2017-08-11 21:14:00 +08:00
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autdzb x0
|
2018-12-06 23:39:17 +08:00
|
|
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// CHECK-NEXT: autdzb x0 // encoding: [0xe0,0x3f,0xc1,0xda]
|
|
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// CHECK-REQ: error: instruction requires: pa
|
|
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// CHECK-REQ-NEXT: autdzb x0
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2017-08-11 21:14:00 +08:00
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xpaci x0
|
2018-12-06 23:39:17 +08:00
|
|
|
// CHECK-NEXT: xpaci x0 // encoding: [0xe0,0x43,0xc1,0xda]
|
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// CHECK-REQ: error: instruction requires: pa
|
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// CHECK-REQ-NEXT: xpaci x0
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2017-08-11 21:14:00 +08:00
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xpacd x0
|
2018-12-06 23:39:17 +08:00
|
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// CHECK-NEXT: xpacd x0 // encoding: [0xe0,0x47,0xc1,0xda]
|
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// CHECK-REQ: error: instruction requires: pa
|
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// CHECK-REQ-NEXT: xpacd x0
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2017-08-11 21:14:00 +08:00
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braa x0, x1
|
2018-12-06 23:39:17 +08:00
|
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|
// CHECK-EMPTY:
|
|
|
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// CHECK-NEXT: braa x0, x1 // encoding: [0x01,0x08,0x1f,0xd7]
|
|
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|
// CHECK-REQ: error: instruction requires: pa
|
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|
|
// CHECK-REQ-NEXT: braa x0, x1
|
2017-08-11 21:14:00 +08:00
|
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brab x0, x1
|
2018-12-06 23:39:17 +08:00
|
|
|
// CHECK-NEXT: brab x0, x1 // encoding: [0x01,0x0c,0x1f,0xd7]
|
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|
// CHECK-REQ: error: instruction requires: pa
|
|
|
|
// CHECK-REQ-NEXT: brab x0, x1
|
2017-08-11 21:14:00 +08:00
|
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|
blraa x0, x1
|
2018-12-06 23:39:17 +08:00
|
|
|
// CHECK-NEXT: blraa x0, x1 // encoding: [0x01,0x08,0x3f,0xd7]
|
|
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|
// CHECK-REQ: error: instruction requires: pa
|
|
|
|
// CHECK-REQ-NEXT: blraa x0, x1
|
2017-08-11 21:14:00 +08:00
|
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|
blrab x0, x1
|
2018-12-06 23:39:17 +08:00
|
|
|
// CHECK-NEXT: blrab x0, x1 // encoding: [0x01,0x0c,0x3f,0xd7]
|
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|
// CHECK-REQ: error: instruction requires: pa
|
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// CHECK-REQ-NEXT: blrab x0, x1
|
2017-08-11 21:14:00 +08:00
|
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braaz x0
|
2018-12-06 23:39:17 +08:00
|
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// CHECK-EMPTY:
|
|
|
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// CHECK-NEXT: braaz x0 // encoding: [0x1f,0x08,0x1f,0xd6]
|
|
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// CHECK-REQ: error: instruction requires: pa
|
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// CHECK-REQ-NEXT: braaz x0
|
2017-08-11 21:14:00 +08:00
|
|
|
brabz x0
|
2018-12-06 23:39:17 +08:00
|
|
|
// CHECK-NEXT: brabz x0 // encoding: [0x1f,0x0c,0x1f,0xd6]
|
|
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|
// CHECK-REQ: error: instruction requires: pa
|
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|
// CHECK-REQ-NEXT: brabz x0
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2017-08-11 21:14:00 +08:00
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blraaz x0
|
2018-12-06 23:39:17 +08:00
|
|
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// CHECK-NEXT: blraaz x0 // encoding: [0x1f,0x08,0x3f,0xd6]
|
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// CHECK-REQ: error: instruction requires: pa
|
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// CHECK-REQ-NEXT: blraaz x0
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2017-08-11 21:14:00 +08:00
|
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blrabz x0
|
2018-12-06 23:39:17 +08:00
|
|
|
// CHECK-NEXT: blrabz x0 // encoding: [0x1f,0x0c,0x3f,0xd6]
|
|
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|
// CHECK-REQ: error: instruction requires: pa
|
|
|
|
// CHECK-REQ-NEXT: blrabz x0
|
2017-08-11 21:14:00 +08:00
|
|
|
retaa
|
2018-12-06 23:39:17 +08:00
|
|
|
// CHECK-NEXT: retaa // encoding: [0xff,0x0b,0x5f,0xd6]
|
|
|
|
// CHECK-REQ: error: instruction requires: pa
|
|
|
|
// CHECK-REQ-NEXT: retaa
|
2017-08-11 21:14:00 +08:00
|
|
|
retab
|
2018-12-06 23:39:17 +08:00
|
|
|
// CHECK-NEXT: retab // encoding: [0xff,0x0f,0x5f,0xd6]
|
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|
|
// CHECK-REQ: error: instruction requires: pa
|
|
|
|
// CHECK-REQ-NEXT: retab
|
2017-08-11 21:14:00 +08:00
|
|
|
eretaa
|
2018-12-06 23:39:17 +08:00
|
|
|
// CHECK-NEXT: eretaa // encoding: [0xff,0x0b,0x9f,0xd6]
|
|
|
|
// CHECK-REQ: error: instruction requires: pa
|
|
|
|
// CHECK-REQ-NEXT: eretaa
|
2017-08-11 21:14:00 +08:00
|
|
|
eretab
|
2018-12-06 23:39:17 +08:00
|
|
|
// CHECK-NEXT: eretab // encoding: [0xff,0x0f,0x9f,0xd6]
|
|
|
|
// CHECK-REQ: error: instruction requires: pa
|
|
|
|
// CHECK-REQ-NEXT: eretab
|
2017-08-11 21:14:00 +08:00
|
|
|
ldraa x0, [x1, 4088]
|
2018-12-06 23:39:17 +08:00
|
|
|
// CHECK-NEXT: ldraa x0, [x1, #4088] // encoding: [0x20,0xf4,0x3f,0xf8]
|
|
|
|
// CHECK-REQ: error: instruction requires: pa
|
|
|
|
// CHECK-REQ-NEXT: ldraa x0, [x1, 4088]
|
2017-08-11 21:14:00 +08:00
|
|
|
ldraa x0, [x1, -4096]
|
2018-12-06 23:39:17 +08:00
|
|
|
// CHECK-NEXT: ldraa x0, [x1, #-4096] // encoding: [0x20,0x04,0x60,0xf8]
|
|
|
|
// CHECK-REQ: error: instruction requires: pa
|
|
|
|
// CHECK-REQ-NEXT: ldraa x0, [x1, -4096]
|
2017-08-11 21:14:00 +08:00
|
|
|
ldrab x0, [x1, 4088]
|
2018-12-06 23:39:17 +08:00
|
|
|
// CHECK-NEXT: ldrab x0, [x1, #4088] // encoding: [0x20,0xf4,0xbf,0xf8]
|
|
|
|
// CHECK-REQ: error: instruction requires: pa
|
|
|
|
// CHECK-REQ-NEXT: ldrab x0, [x1, 4088]
|
2017-08-11 21:14:00 +08:00
|
|
|
ldrab x0, [x1, -4096]
|
2018-12-06 23:39:17 +08:00
|
|
|
// CHECK-NEXT: ldrab x0, [x1, #-4096] // encoding: [0x20,0x04,0xe0,0xf8]
|
|
|
|
// CHECK-REQ: error: instruction requires: pa
|
|
|
|
// CHECK-REQ-NEXT: ldrab x0, [x1, -4096]
|
2017-08-11 21:14:00 +08:00
|
|
|
ldraa x0, [x1, 4088]!
|
2018-12-06 23:39:17 +08:00
|
|
|
// CHECK-NEXT: ldraa x0, [x1, #4088]! // encoding: [0x20,0xfc,0x3f,0xf8]
|
|
|
|
// CHECK-REQ: error: instruction requires: pa
|
|
|
|
// CHECK-REQ-NEXT: ldraa x0, [x1, 4088]!
|
2017-08-11 21:14:00 +08:00
|
|
|
ldraa x0, [x1, -4096]!
|
2018-12-06 23:39:17 +08:00
|
|
|
// CHECK-NEXT: ldraa x0, [x1, #-4096]! // encoding: [0x20,0x0c,0x60,0xf8]
|
|
|
|
// CHECK-REQ: error: instruction requires: pa
|
|
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// CHECK-REQ-NEXT: ldraa x0, [x1, -4096]!
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2017-08-11 21:14:00 +08:00
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ldrab x0, [x1, 4088]!
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2018-12-06 23:39:17 +08:00
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// CHECK-NEXT: ldrab x0, [x1, #4088]! // encoding: [0x20,0xfc,0xbf,0xf8]
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// CHECK-REQ: error: instruction requires: pa
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// CHECK-REQ-NEXT: ldrab x0, [x1, 4088]!
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2017-08-11 21:14:00 +08:00
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ldrab x0, [x1, -4096]!
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2018-12-06 23:39:17 +08:00
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// CHECK-NEXT: ldrab x0, [x1, #-4096]! // encoding: [0x20,0x0c,0xe0,0xf8]
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// CHECK-REQ: error: instruction requires: pa
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// CHECK-REQ-NEXT: ldrab x0, [x1, -4096]!
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2017-08-11 21:14:00 +08:00
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ldraa x0, [x1]
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2018-12-06 23:39:17 +08:00
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// CHECK-NEXT: ldraa x0, [x1] // encoding: [0x20,0x04,0x20,0xf8]
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// CHECK-REQ: error: instruction requires: pa
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// CHECK-REQ-NEXT: ldraa x0, [x1]
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2017-08-11 21:14:00 +08:00
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ldrab x0, [x1]
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2018-12-06 23:39:17 +08:00
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// CHECK-NEXT: ldrab x0, [x1] // encoding: [0x20,0x04,0xa0,0xf8]
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// CHECK-REQ: error: instruction requires: pa
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// CHECK-REQ-NEXT: ldrab x0, [x1]
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2019-06-26 09:38:20 +08:00
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ldraa x0, [x1]!
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2019-11-28 23:31:41 +08:00
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// CHECK-NEXT: ldraa x0, [x1, #0]! // encoding: [0x20,0x0c,0x20,0xf8]
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2019-06-26 09:38:20 +08:00
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// CHECK-REQ: error: instruction requires: pa
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// CHECK-REQ-NEXT: ldraa x0, [x1]!
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ldrab x0, [x1]!
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2019-11-28 23:31:41 +08:00
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// CHECK-NEXT: ldrab x0, [x1, #0]! // encoding: [0x20,0x0c,0xa0,0xf8]
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2019-06-26 09:38:20 +08:00
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// CHECK-REQ: error: instruction requires: pa
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// CHECK-REQ-NEXT: ldrab x0, [x1]!
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2020-02-19 17:46:50 +08:00
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ldraa xzr, [sp, -4096]!
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// CHECK-NEXT: ldraa xzr, [sp, #-4096]! // encoding: [0xff,0x0f,0x60,0xf8]
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// CHECK-REQ: error: instruction requires: pa
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// CHECK-REQ-NEXT: ldraa xzr, [sp, -4096]!
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ldrab xzr, [sp, -4096]!
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// CHECK-NEXT: ldrab xzr, [sp, #-4096]! // encoding: [0xff,0x0f,0xe0,0xf8]
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// CHECK-REQ: error: instruction requires: pa
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// CHECK-REQ-NEXT: ldrab xzr, [sp, -4096]!
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