[AArch64][SVE2] Asm: support SVE2 Narrowing Group
Summary:
Patch adds support for the following instructions:
SVE2 bitwise shift right narrow:
* SQSHRUNB, SQSHRUNT, SQRSHRUNB, SQRSHRUNT, SHRNB, SHRNT, RSHRNB, RSHRNT,
SQSHRNB, SQSHRNT, SQRSHRNB, SQRSHRNT, UQSHRNB, UQSHRNT, UQRSHRNB,
UQRSHRNT
SVE2 integer add/subtract narrow high part:
* ADDHNB, ADDHNT, RADDHNB, RADDHNT, SUBHNB, SUBHNT, RSUBHNB, RSUBHNT
SVE2 saturating extract narrow:
* SQXTNB, SQXTNT, UQXTNB, UQXTNT, SQXTUNB, SQXTUNT
The specification can be found here:
https://developer.arm.com/docs/ddi0602/latest
Reviewed By: SjoerdMeijer
Differential Revision: https://reviews.llvm.org/D62205
llvm-svn: 361624
2019-05-24 18:22:30 +08:00
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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
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// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
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// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
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// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
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2020-03-16 07:17:52 +08:00
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// RUN: | llvm-objdump -d --mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
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[AArch64][SVE2] Asm: support SVE2 Narrowing Group
Summary:
Patch adds support for the following instructions:
SVE2 bitwise shift right narrow:
* SQSHRUNB, SQSHRUNT, SQRSHRUNB, SQRSHRUNT, SHRNB, SHRNT, RSHRNB, RSHRNT,
SQSHRNB, SQSHRNT, SQRSHRNB, SQRSHRNT, UQSHRNB, UQSHRNT, UQRSHRNB,
UQRSHRNT
SVE2 integer add/subtract narrow high part:
* ADDHNB, ADDHNT, RADDHNB, RADDHNT, SUBHNB, SUBHNT, RSUBHNB, RSUBHNT
SVE2 saturating extract narrow:
* SQXTNB, SQXTNT, UQXTNB, UQXTNT, SQXTUNB, SQXTUNT
The specification can be found here:
https://developer.arm.com/docs/ddi0602/latest
Reviewed By: SjoerdMeijer
Differential Revision: https://reviews.llvm.org/D62205
llvm-svn: 361624
2019-05-24 18:22:30 +08:00
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
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// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
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raddhnt z0.b, z1.h, z31.h
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// CHECK-INST: raddhnt z0.b, z1.h, z31.h
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// CHECK-ENCODING: [0x20,0x6c,0x7f,0x45]
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// CHECK-ERROR: instruction requires: sve2
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// CHECK-UNKNOWN: 20 6c 7f 45 <unknown>
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raddhnt z0.h, z1.s, z31.s
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// CHECK-INST: raddhnt z0.h, z1.s, z31.s
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// CHECK-ENCODING: [0x20,0x6c,0xbf,0x45]
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// CHECK-ERROR: instruction requires: sve2
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// CHECK-UNKNOWN: 20 6c bf 45 <unknown>
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raddhnt z0.s, z1.d, z31.d
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// CHECK-INST: raddhnt z0.s, z1.d, z31.d
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// CHECK-ENCODING: [0x20,0x6c,0xff,0x45]
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// CHECK-ERROR: instruction requires: sve2
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// CHECK-UNKNOWN: 20 6c ff 45 <unknown>
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