2014-06-16 21:18:59 +08:00
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; RUN: llc -march=mips64el -mcpu=mips4 -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=MIPS4 -check-prefix=ACCMULDIV %s
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; RUN: llc -march=mips64el -mcpu=mips64 -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=HAS-DCLO -check-prefix=ACCMULDIV %s
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; RUN: llc -march=mips64el -mcpu=mips64r2 -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=HAS-DCLO -check-prefix=ACCMULDIV %s
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; RUN: llc -march=mips64el -mcpu=mips64r6 -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=HAS-DCLO -check-prefix=GPRMULDIV %s
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2013-10-15 09:06:30 +08:00
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@gll0 = common global i64 0, align 8
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@gll1 = common global i64 0, align 8
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2011-09-30 04:37:56 +08:00
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define i64 @f0(i64 %a0, i64 %a1) nounwind readnone {
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entry:
|
2014-06-11 23:48:00 +08:00
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; ALL-LABEL: f0:
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; ALL: daddu $2, ${{[45]}}, ${{[45]}}
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2011-09-30 04:37:56 +08:00
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%add = add nsw i64 %a1, %a0
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ret i64 %add
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}
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define i64 @f1(i64 %a0, i64 %a1) nounwind readnone {
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entry:
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2014-06-11 23:48:00 +08:00
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; ALL-LABEL: f1:
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; ALL: dsubu $2, $4, $5
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2011-09-30 04:37:56 +08:00
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%sub = sub nsw i64 %a0, %a1
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ret i64 %sub
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}
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define i64 @f4(i64 %a0, i64 %a1) nounwind readnone {
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entry:
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2014-06-11 23:48:00 +08:00
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; ALL-LABEL: f4:
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; ALL: and $2, ${{[45]}}, ${{[45]}}
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2011-09-30 04:37:56 +08:00
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%and = and i64 %a1, %a0
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ret i64 %and
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}
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define i64 @f5(i64 %a0, i64 %a1) nounwind readnone {
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entry:
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2014-06-11 23:48:00 +08:00
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; ALL-LABEL: f5:
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; ALL: or $2, ${{[45]}}, ${{[45]}}
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2011-09-30 04:37:56 +08:00
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%or = or i64 %a1, %a0
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ret i64 %or
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}
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define i64 @f6(i64 %a0, i64 %a1) nounwind readnone {
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entry:
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2014-06-11 23:48:00 +08:00
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; ALL-LABEL: f6:
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; ALL: xor $2, ${{[45]}}, ${{[45]}}
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2011-09-30 04:37:56 +08:00
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%xor = xor i64 %a1, %a0
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ret i64 %xor
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}
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2011-09-30 10:08:54 +08:00
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define i64 @f7(i64 %a0) nounwind readnone {
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entry:
|
2014-06-11 23:48:00 +08:00
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; ALL-LABEL: f7:
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; ALL: daddiu $2, $4, 20
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2011-09-30 10:08:54 +08:00
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%add = add nsw i64 %a0, 20
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ret i64 %add
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}
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define i64 @f8(i64 %a0) nounwind readnone {
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entry:
|
2014-06-11 23:48:00 +08:00
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; ALL-LABEL: f8:
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; ALL: daddiu $2, $4, -20
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2011-09-30 10:08:54 +08:00
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%sub = add nsw i64 %a0, -20
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ret i64 %sub
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}
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define i64 @f9(i64 %a0) nounwind readnone {
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entry:
|
2014-06-11 23:48:00 +08:00
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; ALL-LABEL: f9:
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; ALL: andi $2, $4, 20
|
2011-09-30 10:08:54 +08:00
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%and = and i64 %a0, 20
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ret i64 %and
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}
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define i64 @f10(i64 %a0) nounwind readnone {
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entry:
|
2014-06-11 23:48:00 +08:00
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; ALL-LABEL: f10:
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; ALL: ori $2, $4, 20
|
2011-09-30 10:08:54 +08:00
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%or = or i64 %a0, 20
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ret i64 %or
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}
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define i64 @f11(i64 %a0) nounwind readnone {
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entry:
|
2014-06-11 23:48:00 +08:00
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; ALL-LABEL: f11:
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; ALL: xori $2, $4, 20
|
2011-09-30 10:08:54 +08:00
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|
%xor = xor i64 %a0, 20
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|
ret i64 %xor
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}
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|
2011-10-04 04:01:11 +08:00
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define i64 @f12(i64 %a, i64 %b) nounwind readnone {
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entry:
|
2014-06-11 23:48:00 +08:00
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; ALL-LABEL: f12:
|
2014-06-16 21:18:59 +08:00
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; ACCMULDIV: mult ${{[45]}}, ${{[45]}}
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; GPRMULDIV: dmul $2, ${{[45]}}, ${{[45]}}
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|
2011-10-04 04:01:11 +08:00
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%mul = mul nsw i64 %b, %a
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ret i64 %mul
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}
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define i64 @f13(i64 %a, i64 %b) nounwind readnone {
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entry:
|
2014-06-11 23:48:00 +08:00
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; ALL-LABEL: f13:
|
2014-06-16 21:18:59 +08:00
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; ACCMULDIV: mult ${{[45]}}, ${{[45]}}
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; GPRMULDIV: dmul $2, ${{[45]}}, ${{[45]}}
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|
2011-10-04 04:01:11 +08:00
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%mul = mul i64 %b, %a
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|
ret i64 %mul
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}
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2011-10-04 05:06:13 +08:00
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define i64 @f14(i64 %a, i64 %b) nounwind readnone {
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entry:
|
2014-06-11 23:48:00 +08:00
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; ALL-LABEL: f14:
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; ALL-DAG: ld $[[P0:[0-9]+]], %got_disp(gll0)(
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; ALL-DAG: ld $[[P1:[0-9]+]], %got_disp(gll1)(
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; ALL-DAG: ld $[[T0:[0-9]+]], 0($[[P0]])
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; ALL-DAG: ld $[[T1:[0-9]+]], 0($[[P1]])
|
2014-06-16 21:18:59 +08:00
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; ACCMULDIV: ddiv $zero, $[[T0]], $[[T1]]
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; ACCMULDIV: teq $[[T1]], $zero, 7
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; ACCMULDIV: mflo $2
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; GPRMULDIV: ddiv $2, $[[T0]], $[[T1]]
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; GPRMULDIV: teq $[[T1]], $zero, 7
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|
2015-02-28 05:17:42 +08:00
|
|
|
%0 = load i64, i64* @gll0, align 8
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|
%1 = load i64, i64* @gll1, align 8
|
2013-10-15 09:06:30 +08:00
|
|
|
%div = sdiv i64 %0, %1
|
2011-10-04 05:06:13 +08:00
|
|
|
ret i64 %div
|
|
|
|
}
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|
|
|
|
2013-10-15 09:06:30 +08:00
|
|
|
define i64 @f15() nounwind readnone {
|
2011-10-04 05:06:13 +08:00
|
|
|
entry:
|
2014-06-11 23:48:00 +08:00
|
|
|
; ALL-LABEL: f15:
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|
|
; ALL-DAG: ld $[[P0:[0-9]+]], %got_disp(gll0)(
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|
|
; ALL-DAG: ld $[[P1:[0-9]+]], %got_disp(gll1)(
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|
|
; ALL-DAG: ld $[[T0:[0-9]+]], 0($[[P0]])
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|
|
; ALL-DAG: ld $[[T1:[0-9]+]], 0($[[P1]])
|
2014-06-16 21:18:59 +08:00
|
|
|
|
|
|
|
; ACCMULDIV: ddivu $zero, $[[T0]], $[[T1]]
|
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|
|
; ACCMULDIV: teq $[[T1]], $zero, 7
|
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|
|
; ACCMULDIV: mflo $2
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|
|
; GPRMULDIV: ddivu $2, $[[T0]], $[[T1]]
|
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|
; GPRMULDIV: teq $[[T1]], $zero, 7
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|
|
|
2015-02-28 05:17:42 +08:00
|
|
|
%0 = load i64, i64* @gll0, align 8
|
|
|
|
%1 = load i64, i64* @gll1, align 8
|
2013-10-15 09:06:30 +08:00
|
|
|
%div = udiv i64 %0, %1
|
2011-10-04 05:06:13 +08:00
|
|
|
ret i64 %div
|
|
|
|
}
|
|
|
|
|
|
|
|
define i64 @f16(i64 %a, i64 %b) nounwind readnone {
|
|
|
|
entry:
|
2014-06-11 23:48:00 +08:00
|
|
|
; ALL-LABEL: f16:
|
2014-06-16 21:18:59 +08:00
|
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|
; ACCMULDIV: ddiv $zero, $4, $5
|
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|
; ACCMULDIV: teq $5, $zero, 7
|
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|
|
; ACCMULDIV: mfhi $2
|
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|
|
; GPRMULDIV: dmod $2, $4, $5
|
|
|
|
; GPRMULDIV: teq $5, $zero, 7
|
|
|
|
|
2011-10-04 05:06:13 +08:00
|
|
|
%rem = srem i64 %a, %b
|
|
|
|
ret i64 %rem
|
|
|
|
}
|
|
|
|
|
|
|
|
define i64 @f17(i64 %a, i64 %b) nounwind readnone {
|
|
|
|
entry:
|
2014-06-11 23:48:00 +08:00
|
|
|
; ALL-LABEL: f17:
|
2014-06-16 21:18:59 +08:00
|
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|
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|
|
; ACCMULDIV: ddivu $zero, $4, $5
|
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|
|
; ACCMULDIV: teq $5, $zero, 7
|
|
|
|
; ACCMULDIV: mfhi $2
|
|
|
|
|
|
|
|
; GPRMULDIV: dmodu $2, $4, $5
|
|
|
|
; GPRMULDIV: teq $5, $zero, 7
|
|
|
|
|
2011-10-04 05:06:13 +08:00
|
|
|
%rem = urem i64 %a, %b
|
|
|
|
ret i64 %rem
|
|
|
|
}
|
|
|
|
|
2011-12-12 19:59:10 +08:00
|
|
|
declare i64 @llvm.ctlz.i64(i64, i1) nounwind readnone
|
2011-10-04 05:16:50 +08:00
|
|
|
|
|
|
|
define i64 @f18(i64 %X) nounwind readnone {
|
|
|
|
entry:
|
2014-06-11 23:48:00 +08:00
|
|
|
; ALL-LABEL: f18:
|
2014-04-14 23:44:42 +08:00
|
|
|
|
|
|
|
; The MIPS4 version is too long to reasonably test. At least check we don't get dclz
|
2014-06-11 23:48:00 +08:00
|
|
|
; MIPS4-NOT: dclz
|
2014-04-14 23:44:42 +08:00
|
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|
|
2014-06-16 21:18:59 +08:00
|
|
|
; HAS-DCLO: dclz $2, $4
|
|
|
|
|
2011-12-12 19:59:10 +08:00
|
|
|
%tmp1 = tail call i64 @llvm.ctlz.i64(i64 %X, i1 true)
|
2011-10-04 05:16:50 +08:00
|
|
|
ret i64 %tmp1
|
|
|
|
}
|
|
|
|
|
|
|
|
define i64 @f19(i64 %X) nounwind readnone {
|
|
|
|
entry:
|
2014-06-11 23:48:00 +08:00
|
|
|
; ALL-LABEL: f19:
|
2014-04-14 23:44:42 +08:00
|
|
|
|
|
|
|
; The MIPS4 version is too long to reasonably test. At least check we don't get dclo
|
2014-06-11 23:48:00 +08:00
|
|
|
; MIPS4-NOT: dclo
|
2014-04-14 23:44:42 +08:00
|
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|
|
2014-06-16 21:18:59 +08:00
|
|
|
; HAS-DCLO: dclo $2, $4
|
|
|
|
|
2011-10-04 05:16:50 +08:00
|
|
|
%neg = xor i64 %X, -1
|
2011-12-12 19:59:10 +08:00
|
|
|
%tmp1 = tail call i64 @llvm.ctlz.i64(i64 %neg, i1 true)
|
2011-10-04 05:16:50 +08:00
|
|
|
ret i64 %tmp1
|
|
|
|
}
|
|
|
|
|
2011-10-04 05:23:18 +08:00
|
|
|
define i64 @f20(i64 %a, i64 %b) nounwind readnone {
|
|
|
|
entry:
|
2014-06-11 23:48:00 +08:00
|
|
|
; ALL-LABEL: f20:
|
|
|
|
; ALL: nor $2, ${{[45]}}, ${{[45]}}
|
2011-10-04 05:23:18 +08:00
|
|
|
%or = or i64 %b, %a
|
|
|
|
%neg = xor i64 %or, -1
|
|
|
|
ret i64 %neg
|
|
|
|
}
|