2012-02-18 20:03:15 +08:00
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//===-- Thumb1InstrInfo.cpp - Thumb-1 Instruction Information -------------===//
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2009-06-27 05:28:53 +08:00
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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2009-07-03 06:18:33 +08:00
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// This file contains the Thumb-1 implementation of the TargetInstrInfo class.
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2009-06-27 05:28:53 +08:00
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//
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//===----------------------------------------------------------------------===//
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2009-11-07 07:52:48 +08:00
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#include "Thumb1InstrInfo.h"
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2017-06-06 19:49:48 +08:00
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#include "ARMSubtarget.h"
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2009-06-27 05:28:53 +08:00
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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2009-11-02 06:04:35 +08:00
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#include "llvm/CodeGen/MachineMemOperand.h"
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2012-02-29 07:53:30 +08:00
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#include "llvm/MC/MCInst.h"
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2009-06-27 05:28:53 +08:00
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using namespace llvm;
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2009-11-02 08:10:38 +08:00
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Thumb1InstrInfo::Thumb1InstrInfo(const ARMSubtarget &STI)
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2015-03-12 13:12:31 +08:00
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: ARMBaseInstrInfo(STI), RI() {}
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2009-06-27 05:28:53 +08:00
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2017-04-22 05:48:41 +08:00
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/// Return the noop instruction to use for a noop.
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void Thumb1InstrInfo::getNoop(MCInst &NopInst) const {
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2012-02-29 07:53:30 +08:00
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NopInst.setOpcode(ARM::tMOVr);
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2015-05-14 02:37:00 +08:00
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NopInst.addOperand(MCOperand::createReg(ARM::R8));
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NopInst.addOperand(MCOperand::createReg(ARM::R8));
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NopInst.addOperand(MCOperand::createImm(ARMCC::AL));
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NopInst.addOperand(MCOperand::createReg(0));
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2012-02-29 07:53:30 +08:00
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}
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2009-07-11 14:43:01 +08:00
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unsigned Thumb1InstrInfo::getUnindexedOpcode(unsigned Opc) const {
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2009-07-09 00:09:28 +08:00
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return 0;
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}
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2010-07-11 14:33:54 +08:00
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void Thumb1InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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2016-06-12 23:39:02 +08:00
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MachineBasicBlock::iterator I,
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const DebugLoc &DL, unsigned DestReg,
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unsigned SrcReg, bool KillSrc) const {
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2014-08-21 07:38:50 +08:00
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// Need to check the arch.
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MachineFunction &MF = *MBB.getParent();
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2015-02-20 16:24:37 +08:00
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const ARMSubtarget &st = MF.getSubtarget<ARMSubtarget>();
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2014-08-21 07:38:50 +08:00
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2010-07-11 14:33:54 +08:00
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assert(ARM::GPRRegClass.contains(DestReg, SrcReg) &&
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"Thumb1 can only copy GPR registers");
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2014-08-21 07:38:50 +08:00
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if (st.hasV6Ops() || ARM::hGPRRegClass.contains(SrcReg)
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|| !ARM::tGPRRegClass.contains(DestReg))
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2017-01-13 17:37:56 +08:00
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BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
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.addReg(SrcReg, getKillRegState(KillSrc))
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.add(predOps(ARMCC::AL));
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2014-08-21 07:38:50 +08:00
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else {
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2017-03-07 17:38:16 +08:00
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// FIXME: Can also use 'mov hi, $src; mov $dst, hi',
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// with hi as either r10 or r11.
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const TargetRegisterInfo *RegInfo = st.getRegisterInfo();
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if (MBB.computeRegisterLiveness(RegInfo, ARM::CPSR, I)
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== MachineBasicBlock::LQR_Dead) {
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BuildMI(MBB, I, DL, get(ARM::tMOVSr), DestReg)
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.addReg(SrcReg, getKillRegState(KillSrc))
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->addRegisterDead(ARM::CPSR, RegInfo);
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return;
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}
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2014-08-21 07:38:50 +08:00
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// 'MOV lo, lo' is unpredictable on < v6, so use the stack to do it
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2017-01-13 17:37:56 +08:00
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BuildMI(MBB, I, DL, get(ARM::tPUSH))
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.add(predOps(ARMCC::AL))
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.addReg(SrcReg, getKillRegState(KillSrc));
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BuildMI(MBB, I, DL, get(ARM::tPOP))
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.add(predOps(ARMCC::AL))
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.addReg(DestReg, getDefRegState(true));
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2014-08-21 07:38:50 +08:00
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}
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2009-06-27 05:28:53 +08:00
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}
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2009-07-03 06:18:33 +08:00
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void Thumb1InstrInfo::
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2009-06-27 05:28:53 +08:00
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storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned SrcReg, bool isKill, int FI,
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2010-05-07 03:06:44 +08:00
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const {
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2012-04-20 15:30:17 +08:00
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assert((RC == &ARM::tGPRRegClass ||
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2009-08-13 13:40:51 +08:00
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(TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
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isARMLowRegister(SrcReg))) && "Unknown regclass!");
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2009-06-27 05:28:53 +08:00
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2012-04-20 15:30:17 +08:00
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if (RC == &ARM::tGPRRegClass ||
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2010-01-16 06:21:03 +08:00
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(TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
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isARMLowRegister(SrcReg))) {
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2010-05-07 03:06:44 +08:00
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DebugLoc DL;
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if (I != MBB.end()) DL = I->getDebugLoc();
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2009-11-02 06:04:35 +08:00
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MachineFunction &MF = *MBB.getParent();
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2016-07-29 02:40:00 +08:00
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MachineFrameInfo &MFI = MF.getFrameInfo();
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2015-08-12 07:09:45 +08:00
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MachineMemOperand *MMO = MF.getMachineMemOperand(
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MachinePointerInfo::getFixedStack(MF, FI), MachineMemOperand::MOStore,
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MFI.getObjectSize(FI), MFI.getObjectAlignment(FI));
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2017-01-13 17:37:56 +08:00
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BuildMI(MBB, I, DL, get(ARM::tSTRspi))
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.addReg(SrcReg, getKillRegState(isKill))
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.addFrameIndex(FI)
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.addImm(0)
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.addMemOperand(MMO)
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.add(predOps(ARMCC::AL));
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2009-06-27 05:28:53 +08:00
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}
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}
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2009-07-03 06:18:33 +08:00
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void Thumb1InstrInfo::
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2009-06-27 05:28:53 +08:00
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loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned DestReg, int FI,
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2010-05-07 03:06:44 +08:00
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const {
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2018-01-26 18:20:58 +08:00
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assert((RC->hasSuperClassEq(&ARM::tGPRRegClass) ||
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2009-08-13 13:40:51 +08:00
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(TargetRegisterInfo::isPhysicalRegister(DestReg) &&
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isARMLowRegister(DestReg))) && "Unknown regclass!");
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2009-06-27 05:28:53 +08:00
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2018-01-26 18:20:58 +08:00
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if (RC->hasSuperClassEq(&ARM::tGPRRegClass) ||
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2010-01-16 06:21:03 +08:00
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(TargetRegisterInfo::isPhysicalRegister(DestReg) &&
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isARMLowRegister(DestReg))) {
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2010-05-07 03:06:44 +08:00
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DebugLoc DL;
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if (I != MBB.end()) DL = I->getDebugLoc();
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2009-11-02 06:04:35 +08:00
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MachineFunction &MF = *MBB.getParent();
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2016-07-29 02:40:00 +08:00
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MachineFrameInfo &MFI = MF.getFrameInfo();
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2015-08-12 07:09:45 +08:00
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MachineMemOperand *MMO = MF.getMachineMemOperand(
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MachinePointerInfo::getFixedStack(MF, FI), MachineMemOperand::MOLoad,
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MFI.getObjectSize(FI), MFI.getObjectAlignment(FI));
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2017-01-13 17:37:56 +08:00
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BuildMI(MBB, I, DL, get(ARM::tLDRspi), DestReg)
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.addFrameIndex(FI)
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.addImm(0)
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.addMemOperand(MMO)
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.add(predOps(ARMCC::AL));
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2009-06-27 05:28:53 +08:00
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}
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}
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2014-07-26 03:31:34 +08:00
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2016-06-28 23:18:26 +08:00
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void Thumb1InstrInfo::expandLoadStackGuard(
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MachineBasicBlock::iterator MI) const {
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MachineFunction &MF = *MI->getParent()->getParent();
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const TargetMachine &TM = MF.getTarget();
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if (TM.isPositionIndependent())
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expandLoadStackGuardBase(MI, ARM::tLDRLIT_ga_pcrel, ARM::tLDRi);
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2014-08-02 13:40:40 +08:00
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else
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2016-06-28 23:18:26 +08:00
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expandLoadStackGuardBase(MI, ARM::tLDRLIT_ga_abs, ARM::tLDRi);
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2014-07-26 03:31:34 +08:00
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}
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