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llvm-project/llvm/test/MC/Disassembler/Sparc/sparc.txt

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[Sparc] Add initial implementation of disassembler for sparc llvm-svn: 198591
2014-01-06 16:08:58 +08:00
# RUN: llvm-mc --disassemble %s -triple=sparc-unknown-linux | FileCheck %s
# CHECK: add %g0, %g0, %g0
0x80 0x00 0x00 0x00
# CHECK: add %g1, %g2, %g3
0x86 0x00 0x40 0x02
# CHECK: add %o0, %o1, %l0
0xa0 0x02 0x00 0x09
# CHECK: add %o0, 10, %l0
0xa0 0x02 0x20 0x0a
# CHECK: addcc %g1, %g2, %g3
0x86 0x80 0x40 0x02
# CHECK: addxcc %g1, %g2, %g3
0x86 0xc0 0x40 0x02
# CHECK: udiv %g1, %g2, %g3
0x86 0x70 0x40 0x02
# CHECK: sdiv %g1, %g2, %g3
0x86 0x78 0x40 0x02
# CHECK: and %g1, %g2, %g3
0x86 0x08 0x40 0x02
# CHECK: andn %g1, %g2, %g3
0x86 0x28 0x40 0x02
# CHECK: or %g1, %g2, %g3
0x86 0x10 0x40 0x02
# CHECK: orn %g1, %g2, %g3
0x86 0x30 0x40 0x02
# CHECK: xor %g1, %g2, %g3
0x86 0x18 0x40 0x02
# CHECK: xnor %g1, %g2, %g3
0x86 0x38 0x40 0x02
# CHECK: umul %g1, %g2, %g3
0x86 0x50 0x40 0x02
# CHECK: smul %g1, %g2, %g3
0x86 0x58 0x40 0x02
# CHECK: nop
0x01 0x00 0x00 0x00
# CHECK: sethi 10, %l0
0x21 0x00 0x00 0x0a
# CHECK: sll %g1, %g2, %g3
0x87 0x28 0x40 0x02
# CHECK: sll %g1, 31, %g3
0x87 0x28 0x60 0x1f
# CHECK: srl %g1, %g2, %g3
0x87 0x30 0x40 0x02
# CHECK: srl %g1, 31, %g3
0x87 0x30 0x60 0x1f
# CHECK: sra %g1, %g2, %g3
0x87 0x38 0x40 0x02
# CHECK: sra %g1, 31, %g3
0x87 0x38 0x60 0x1f
# CHECK: sub %g1, %g2, %g3
0x86 0x20 0x40 0x02
# CHECK: subcc %g1, %g2, %g3
0x86 0xa0 0x40 0x02
# CHECK: subxcc %g1, %g2, %g3
0x86 0xe0 0x40 0x02
[Sparc] Add support for parsing branch instructions and conditional moves. llvm-svn: 198738
2014-01-08 14:14:52 +08:00
# CHECK: ba 4194303
0x10 0xbf 0xff 0xff
# CHECK: bne 4194303
0x12 0xbf 0xff 0xff
# CHECK: be 4194303
0x02 0xbf 0xff 0xff
# CHECK: bg 4194303
0x14 0xbf 0xff 0xff
# CHECK: ble 4194303
0x04 0xbf 0xff 0xff
# CHECK: bge 4194303
0x16 0xbf 0xff 0xff
# CHECK: bl 4194303
0x06 0xbf 0xff 0xff
# CHECK: bgu 4194303
0x18 0xbf 0xff 0xff
# CHECK: bleu 4194303
0x08 0xbf 0xff 0xff
# CHECK: bcc 4194303
0x1a 0xbf 0xff 0xff
# CHECK: bcs 4194303
0x0a 0xbf 0xff 0xff
# CHECK: bpos 4194303
0x1c 0xbf 0xff 0xff
# CHECK: bneg 4194303
0x0c 0xbf 0xff 0xff
# CHECK: bvc 4194303
0x1e 0xbf 0xff 0xff
# CHECK: bvs 4194303
0x0e 0xbf 0xff 0xff
# CHECK: fbu 4194303
0x0f 0xbf 0xff 0xff
# CHECK: fbg 4194303
0x0d 0xbf 0xff 0xff
# CHECK: fbug 4194303
0x0b 0xbf 0xff 0xff
# CHECK: fbl 4194303
0x09 0xbf 0xff 0xff
# CHECK: fbul 4194303
0x07 0xbf 0xff 0xff
# CHECK: fblg 4194303
0x05 0xbf 0xff 0xff
# CHECK: fbne 4194303
0x03 0xbf 0xff 0xff
# CHECK: fbe 4194303
0x13 0xbf 0xff 0xff
# CHECK: fbue 4194303
0x15 0xbf 0xff 0xff
# CHECK: fbge 4194303
0x17 0xbf 0xff 0xff
# CHECK: fbuge 4194303
0x19 0xbf 0xff 0xff
# CHECK: fble 4194303
0x1b 0xbf 0xff 0xff
# CHECK: fbule 4194303
0x1d 0xbf 0xff 0xff
# CHECK: fbo 4194303
0x1f 0xbf 0xff 0xff
[Sparc] Emit 'restore' instead of 'restore %g0, %g0, %g0'. This improves the readability of the generated code. llvm-svn: 202563
2014-03-01 09:04:26 +08:00
This change adds co-processor condition branching and conditional traps to the Sparc back-end. This will allow inline assembler code to utilize these features, but no automatic lowering is provided, except for the previously provided @llvm.trap, which lowers to "ta 5". The change also separates out the different assembly language syntaxes for V8 and V9 Sparc. Previously, only V9 Sparc assembly syntax was provided. The change also corrects the selection order of trap disassembly, allowing, e.g. "ta %g0 + 15" to be rendered, more readably, as "ta 15", ignoring the %g0 register. This is per the sparc v8 and v9 manuals. Check-in includes many extra unit tests to check this works correctly on both V8 and V9 Sparc processors. Code Reviewed at http://reviews.llvm.org/D17960. llvm-svn: 263044
2016-03-10 02:20:21 +08:00
# CHECK: cba 4194303
0x11 0xff 0xff 0xff
# CHECK: cbn 4194303
0x01 0xff 0xff 0xff
# CHECK: cb3 4194303
0x0f 0xff 0xff 0xff
# CHECK: cb2 4194303
0x0d 0xff 0xff 0xff
# CHECK: cb23 4194303
0x0b 0xff 0xff 0xff
# CHECK: cb1 4194303
0x09 0xff 0xff 0xff
# CHECK: cb13 4194303
0x07 0xff 0xff 0xff
# CHECK: cb12 4194303
0x05 0xff 0xff 0xff
# CHECK: cb123 4194303
0x03 0xff 0xff 0xff
# CHECK: cb03 4194303
0x15 0xff 0xff 0xff
# CHECK: cb02 4194303
0x17 0xff 0xff 0xff
# CHECK: cb023 4194303
0x19 0xff 0xff 0xff
# CHECK: cb01 4194303
0x1b 0xff 0xff 0xff
# CHECK: cb013 4194303
0x1d 0xff 0xff 0xff
# CHECK: cb012 4194303
0x1f 0xff 0xff 0xff
[Sparc] Emit 'restore' instead of 'restore %g0, %g0, %g0'. This improves the readability of the generated code. llvm-svn: 202563
2014-03-01 09:04:26 +08:00
# CHECK: restore
0x81 0xe8 0x00 0x00
[Sparc] Add support for decoding call instructions in the sparc disassembler. llvm-svn: 202577
2014-03-01 16:30:58 +08:00
# CHECK: call 16
0x40 0x00 0x00 0x04
[Sparc] Add support to decode negative simm13 operands in the sparc disassembler. llvm-svn: 202578
2014-03-01 17:11:57 +08:00
# CHECK: add %g1, -10, %g2
0x84 0x00 0x7f 0xf6
# CHECK: save %sp, -196, %sp
0x9d 0xe3 0xbf 0x3c
# CHECK: cmp %g1, -2
0x80 0xa0 0x7f 0xfe
[Sparc] Add support to decode unimp instruction. llvm-svn: 202581
2014-03-01 17:28:18 +08:00
# CHECK: unimp 12
0x00 0x00 0x00 0x0c
[Sparc] Add support for decoding jmpl/retl/ret instruction. llvm-svn: 202663
2014-03-03 05:17:44 +08:00
# CHECK: jmp %g1+12
This change adds co-processor condition branching and conditional traps to the Sparc back-end. This will allow inline assembler code to utilize these features, but no automatic lowering is provided, except for the previously provided @llvm.trap, which lowers to "ta 5". The change also separates out the different assembly language syntaxes for V8 and V9 Sparc. Previously, only V9 Sparc assembly syntax was provided. The change also corrects the selection order of trap disassembly, allowing, e.g. "ta %g0 + 15" to be rendered, more readably, as "ta 15", ignoring the %g0 register. This is per the sparc v8 and v9 manuals. Check-in includes many extra unit tests to check this works correctly on both V8 and V9 Sparc processors. Code Reviewed at http://reviews.llvm.org/D17960. llvm-svn: 263044
2016-03-10 02:20:21 +08:00
0x81 0xc0 0x60 0x0c
[Sparc] Add support for decoding jmpl/retl/ret instruction. llvm-svn: 202663
2014-03-03 05:17:44 +08:00
# CHECK: retl
0x81 0xc3 0xe0 0x08
# CHECK: ret
This change adds co-processor condition branching and conditional traps to the Sparc back-end. This will allow inline assembler code to utilize these features, but no automatic lowering is provided, except for the previously provided @llvm.trap, which lowers to "ta 5". The change also separates out the different assembly language syntaxes for V8 and V9 Sparc. Previously, only V9 Sparc assembly syntax was provided. The change also corrects the selection order of trap disassembly, allowing, e.g. "ta %g0 + 15" to be rendered, more readably, as "ta 15", ignoring the %g0 register. This is per the sparc v8 and v9 manuals. Check-in includes many extra unit tests to check this works correctly on both V8 and V9 Sparc processors. Code Reviewed at http://reviews.llvm.org/D17960. llvm-svn: 263044
2016-03-10 02:20:21 +08:00
0x81 0xc7 0xe0 0x08
[Sparc] Add return/rett instruction to Sparc backend. llvm-svn: 202666
2014-03-03 06:55:53 +08:00
# CHECK: rett %i7+8
0x81 0xcf 0xe0 0x08
Add support for the Sparc implementation-defined "ASR" registers. (Note that register "Y" is essentially just ASR0). Also added some test cases for divide and multiply, which had none before. Differential Revision: http://reviews.llvm.org/D8670 llvm-svn: 237580
2015-05-19 00:29:48 +08:00
# CHECK: stbar
0x81 0x43 0xc0 0x00
This change adds co-processor condition branching and conditional traps to the Sparc back-end. This will allow inline assembler code to utilize these features, but no automatic lowering is provided, except for the previously provided @llvm.trap, which lowers to "ta 5". The change also separates out the different assembly language syntaxes for V8 and V9 Sparc. Previously, only V9 Sparc assembly syntax was provided. The change also corrects the selection order of trap disassembly, allowing, e.g. "ta %g0 + 15" to be rendered, more readably, as "ta 15", ignoring the %g0 register. This is per the sparc v8 and v9 manuals. Check-in includes many extra unit tests to check this works correctly on both V8 and V9 Sparc processors. Code Reviewed at http://reviews.llvm.org/D17960. llvm-svn: 263044
2016-03-10 02:20:21 +08:00
# CHECK: ta %i5
0x91 0xd0 0x00 0x1d
# CHECK: ta 82
0x91 0xd0 0x20 0x52
# CHECK: ta %g1 + %i2
0x91 0xd0 0x40 0x1a
# CHECK: ta %i5 + 41
0x91 0xd7 0x60 0x29
# CHECK: tn %i5
0x81 0xd0 0x00 0x1d
# CHECK: tne 82
0x93 0xd0 0x20 0x52
# CHECK: te %g1 + %i2
0x83 0xd0 0x40 0x1a
# CHECK: tg %i5 + 41
0x95 0xd7 0x60 0x29
# CHECK: tle %i5
0x85 0xd0 0x00 0x1d
# CHECK: tge 82
0x97 0xd0 0x20 0x52
# CHECK: tl %g1 + %i2
0x87 0xd0 0x40 0x1a
# CHECK: tgu %i5 + 41
0x99 0xd7 0x60 0x29
# CHECK: tleu %i5
0x89 0xd0 0x00 0x1d
# CHECK: tcc 82
0x9b 0xd0 0x20 0x52
# CHECK: tcs %g1 + %i2
0x8b 0xd0 0x40 0x1a
# CHECK: tpos %i5 + 41
0x9d 0xd7 0x60 0x29
# CHECK: tneg %i5
0x8d 0xd0 0x00 0x1d
# CHECK: tvc 82
0x9f 0xd0 0x20 0x52
# CHECK: tvs %g1 + %i2
0x8f 0xd0 0x40 0x1a