llvm-project/llvm/test/MC/X86/mpx-encodings.s

// RUN: llvm-mc -triple x86_64-- --show-encoding %s |\
// RUN:   FileCheck %s --check-prefixes=CHECK,ENCODING

// RUN: llvm-mc -triple x86_64-- -filetype=obj %s |\
// RUN:   llvm-objdump -d - | FileCheck %s

// CHECK: bndmk (%rax), %bnd0
// ENCODING:  encoding: [0xf3,0x0f,0x1b,0x00]
bndmk (%rax), %bnd0

// CHECK: bndmk 1024(%rax), %bnd1
// ENCODING:  encoding: [0xf3,0x0f,0x1b,0x88,0x00,0x04,0x00,0x00]
bndmk 1024(%rax), %bnd1

// CHECK: bndmov  %bnd2, %bnd1
// ENCODING:  encoding: [0x66,0x0f,0x1a,0xca]
bndmov %bnd2, %bnd1

// CHECK: bndmov %bnd1, 1024(%r9)
// ENCODING:  encoding: [0x66,0x41,0x0f,0x1b,0x89,0x00,0x04,0x00,0x00]
bndmov %bnd1, 1024(%r9)

// CHECK: bndstx %bnd1, 1024(%rax)
// ENCODING:  encoding: [0x0f,0x1b,0x88,0x00,0x04,0x00,0x00]
bndstx %bnd1, 1024(%rax)

// CHECK: bndldx 1024(%r8), %bnd1
// ENCODING:  encoding: [0x41,0x0f,0x1a,0x88,0x00,0x04,0x00,0x00]
bndldx 1024(%r8), %bnd1

// CHECK: bndcl 121(%r10), %bnd1
// ENCODING:  encoding: [0xf3,0x41,0x0f,0x1a,0x4a,0x79]
bndcl 121(%r10), %bnd1

// CHECK: bndcn 121(%rcx), %bnd3
// ENCODING:  encoding: [0xf2,0x0f,0x1b,0x59,0x79]
bndcn 121(%rcx), %bnd3

// CHECK: bndcu %rdx, %bnd3
// ENCODING:  encoding: [0xf2,0x0f,0x1a,0xda]
bndcu %rdx, %bnd3
[X86] Remove checks for FeatureAVX512 from the X86 assembly parser. Remove mcpu/mattr from assembly test command lines. Summary: We should always be able to accept AVX512 registers and instructions in llvm-mc. The only subtarget mode that should be checked is 16-bit vs 32-bit vs 64-bit mode. I've also removed all the mattr/mcpu lines from test RUN lines to be consistent with this. Most were due to AVX512, but a few were for other features. Fixes PR36202 Reviewers: RKSimon, echristo, bkramer Reviewed By: echristo Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D42824 llvm-svn: 324106 2018-02-03 01:02:58 +08:00			`// RUN: llvm-mc -triple x86_64-- --show-encoding %s \|\`
[X86] Decode MPX BND registers. We were able to assemble, but not disassemble. Note that fixupRMValue was truncating EA_REG_BND0-3 because we hit the uint8_t max. The control registers were already squarely above it, but I don't think they ever go in .r/m, only in .reg. I also did notice an extra REX.W in our encoding, but I think that's fine. llvm-svn: 275427 2016-07-14 22:53:21 +08:00			`// RUN: FileCheck %s --check-prefixes=CHECK,ENCODING`

[X86] Remove checks for FeatureAVX512 from the X86 assembly parser. Remove mcpu/mattr from assembly test command lines. Summary: We should always be able to accept AVX512 registers and instructions in llvm-mc. The only subtarget mode that should be checked is 16-bit vs 32-bit vs 64-bit mode. I've also removed all the mattr/mcpu lines from test RUN lines to be consistent with this. Most were due to AVX512, but a few were for other features. Fixes PR36202 Reviewers: RKSimon, echristo, bkramer Reviewed By: echristo Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D42824 llvm-svn: 324106 2018-02-03 01:02:58 +08:00			`// RUN: llvm-mc -triple x86_64-- -filetype=obj %s \|\`
			`// RUN: llvm-objdump -d - \| FileCheck %s`
X86-MPX: Implemented encoding for MPX instructions. Added encoding tests. llvm-svn: 239403 2015-06-09 21:02:10 +08:00
			`// CHECK: bndmk (%rax), %bnd0`
[X86] Remove REX.W from 64-bit mode BND instructions. As far as I can tell from the docs, the instructions are automatically 64-bit in 64-bit mode. We don't need REX.W. llvm-svn: 331102 2018-04-28 14:02:40 +08:00			`// ENCODING: encoding: [0xf3,0x0f,0x1b,0x00]`
X86-MPX: Implemented encoding for MPX instructions. Added encoding tests. llvm-svn: 239403 2015-06-09 21:02:10 +08:00			`bndmk (%rax), %bnd0`

			`// CHECK: bndmk 1024(%rax), %bnd1`
[X86] Remove REX.W from 64-bit mode BND instructions. As far as I can tell from the docs, the instructions are automatically 64-bit in 64-bit mode. We don't need REX.W. llvm-svn: 331102 2018-04-28 14:02:40 +08:00			`// ENCODING: encoding: [0xf3,0x0f,0x1b,0x88,0x00,0x04,0x00,0x00]`
X86-MPX: Implemented encoding for MPX instructions. Added encoding tests. llvm-svn: 239403 2015-06-09 21:02:10 +08:00			`bndmk 1024(%rax), %bnd1`

			`// CHECK: bndmov %bnd2, %bnd1`
[X86] Rename BNDMOV instructions and hide redundant instruction encoding from the assembler. Favor the 0x1a encoding for register/register move to match gas. The instructions used RM and MR in their name along with rr/rm/mr at the end. To make more consistent with other instructions remove the RM/MR and use rr/rm/mr/rr_REV. Hide the _REV encoding from the assembler but leave it for the disassembler. llvm-svn: 331101 2018-04-28 14:02:39 +08:00			`// ENCODING: encoding: [0x66,0x0f,0x1a,0xca]`
X86-MPX: Implemented encoding for MPX instructions. Added encoding tests. llvm-svn: 239403 2015-06-09 21:02:10 +08:00			`bndmov %bnd2, %bnd1`

			`// CHECK: bndmov %bnd1, 1024(%r9)`
[X86] Remove REX.W from 64-bit mode BND instructions. As far as I can tell from the docs, the instructions are automatically 64-bit in 64-bit mode. We don't need REX.W. llvm-svn: 331102 2018-04-28 14:02:40 +08:00			`// ENCODING: encoding: [0x66,0x41,0x0f,0x1b,0x89,0x00,0x04,0x00,0x00]`
X86-MPX: Implemented encoding for MPX instructions. Added encoding tests. llvm-svn: 239403 2015-06-09 21:02:10 +08:00			`bndmov %bnd1, 1024(%r9)`

			`// CHECK: bndstx %bnd1, 1024(%rax)`
[X86] Decode MPX BND registers. We were able to assemble, but not disassemble. Note that fixupRMValue was truncating EA_REG_BND0-3 because we hit the uint8_t max. The control registers were already squarely above it, but I don't think they ever go in .r/m, only in .reg. I also did notice an extra REX.W in our encoding, but I think that's fine. llvm-svn: 275427 2016-07-14 22:53:21 +08:00			`// ENCODING: encoding: [0x0f,0x1b,0x88,0x00,0x04,0x00,0x00]`
X86-MPX: Implemented encoding for MPX instructions. Added encoding tests. llvm-svn: 239403 2015-06-09 21:02:10 +08:00			`bndstx %bnd1, 1024(%rax)`

			`// CHECK: bndldx 1024(%r8), %bnd1`
[X86] Decode MPX BND registers. We were able to assemble, but not disassemble. Note that fixupRMValue was truncating EA_REG_BND0-3 because we hit the uint8_t max. The control registers were already squarely above it, but I don't think they ever go in .r/m, only in .reg. I also did notice an extra REX.W in our encoding, but I think that's fine. llvm-svn: 275427 2016-07-14 22:53:21 +08:00			`// ENCODING: encoding: [0x41,0x0f,0x1a,0x88,0x00,0x04,0x00,0x00]`
X86-MPX: Implemented encoding for MPX instructions. Added encoding tests. llvm-svn: 239403 2015-06-09 21:02:10 +08:00			`bndldx 1024(%r8), %bnd1`

			`// CHECK: bndcl 121(%r10), %bnd1`
[X86] Remove REX.W from 64-bit mode BND instructions. As far as I can tell from the docs, the instructions are automatically 64-bit in 64-bit mode. We don't need REX.W. llvm-svn: 331102 2018-04-28 14:02:40 +08:00			`// ENCODING: encoding: [0xf3,0x41,0x0f,0x1a,0x4a,0x79]`
X86-MPX: Implemented encoding for MPX instructions. Added encoding tests. llvm-svn: 239403 2015-06-09 21:02:10 +08:00			`bndcl 121(%r10), %bnd1`

			`// CHECK: bndcn 121(%rcx), %bnd3`
[X86] Remove REX.W from 64-bit mode BND instructions. As far as I can tell from the docs, the instructions are automatically 64-bit in 64-bit mode. We don't need REX.W. llvm-svn: 331102 2018-04-28 14:02:40 +08:00			`// ENCODING: encoding: [0xf2,0x0f,0x1b,0x59,0x79]`
X86-MPX: Implemented encoding for MPX instructions. Added encoding tests. llvm-svn: 239403 2015-06-09 21:02:10 +08:00			`bndcn 121(%rcx), %bnd3`

			`// CHECK: bndcu %rdx, %bnd3`
[X86] Remove REX.W from 64-bit mode BND instructions. As far as I can tell from the docs, the instructions are automatically 64-bit in 64-bit mode. We don't need REX.W. llvm-svn: 331102 2018-04-28 14:02:40 +08:00			`// ENCODING: encoding: [0xf2,0x0f,0x1a,0xda]`
X86-MPX: Implemented encoding for MPX instructions. Added encoding tests. llvm-svn: 239403 2015-06-09 21:02:10 +08:00			`bndcu %rdx, %bnd3`