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llvm-project/llvm/test/MC/AArch64/neon-mov.s

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AArch64/ARM64: move ARM64 into AArch64's place This commit starts with a "git mv ARM64 AArch64" and continues out from there, renaming the C++ classes, intrinsics, and other target-local objects for consistency. "ARM64" test directories are also moved, and tests that began their life in ARM64 use an arm64 triple, those from AArch64 use an aarch64 triple. Both should be equivalent though. This finishes the AArch64 merge, and everyone should feel free to continue committing as normal now. llvm-svn: 209577
2014-05-24 20:50:23 +08:00
// RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
AArch64: add initial NEON support Patch by Ana Pazos. - Completed implementation of instruction formats: AdvSIMD three same AdvSIMD modified immediate AdvSIMD scalar pairwise - Completed implementation of instruction classes (some of the instructions in these classes belong to yet unfinished instruction formats): Vector Arithmetic Vector Immediate Vector Pairwise Arithmetic - Initial implementation of instruction formats: AdvSIMD scalar two-reg misc AdvSIMD scalar three same - Intial implementation of instruction class: Scalar Arithmetic - Initial clang changes to support arm v8 intrinsics. Note: no clang changes for scalar intrinsics function name mangling yet. - Comprehensive test cases for added instructions To verify auto codegen, encoding, decoding, diagnosis, intrinsics. llvm-svn: 187567
2013-08-01 17:20:35 +08:00
// Check that the assembler can handle the documented syntax for AArch64
//----------------------------------------------------------------------
// Vector Move Immediate Shifted
//----------------------------------------------------------------------
movi v0.2s, #1
movi v1.2s, #0
movi v15.2s, #1, lsl #8
movi v16.2s, #1, lsl #16
movi v31.2s, #1, lsl #24
movi v0.4s, #1
movi v0.4s, #1, lsl #8
movi v0.4s, #1, lsl #16
movi v0.4s, #1, lsl #24
movi v0.4h, #1
movi v0.4h, #1, lsl #8
movi v0.8h, #1
movi v0.8h, #1, lsl #8
AArch64/ARM64: run AArch64 NEON MC tests through ARM64 too. This skips a couple of compare ones due to the different syntaxt for floating-point 0.0. AArch64 does it more canonically, and we'll need to fiddle ARM64 to make it work. llvm-svn: 207119
2014-04-24 23:04:20 +08:00
// CHECK: movi v0.2s, #{{0x1|1}} // encoding: [0x20,0x04,0x00,0x0f]
// CHECK: movi v1.2s, #{{0x0|0}} // encoding: [0x01,0x04,0x00,0x0f]
// CHECK: movi v15.2s, #{{0x1|1}}, lsl #8 // encoding: [0x2f,0x24,0x00,0x0f]
// CHECK: movi v16.2s, #{{0x1|1}}, lsl #16 // encoding: [0x30,0x44,0x00,0x0f]
// CHECK: movi v31.2s, #{{0x1|1}}, lsl #24 // encoding: [0x3f,0x64,0x00,0x0f]
// CHECK: movi v0.4s, #{{0x1|1}} // encoding: [0x20,0x04,0x00,0x4f]
// CHECK: movi v0.4s, #{{0x1|1}}, lsl #8 // encoding: [0x20,0x24,0x00,0x4f]
// CHECK: movi v0.4s, #{{0x1|1}}, lsl #16 // encoding: [0x20,0x44,0x00,0x4f]
// CHECK: movi v0.4s, #{{0x1|1}}, lsl #24 // encoding: [0x20,0x64,0x00,0x4f]
// CHECK: movi v0.4h, #{{0x1|1}} // encoding: [0x20,0x84,0x00,0x0f]
// CHECK: movi v0.4h, #{{0x1|1}}, lsl #8 // encoding: [0x20,0xa4,0x00,0x0f]
// CHECK: movi v0.8h, #{{0x1|1}} // encoding: [0x20,0x84,0x00,0x4f]
// CHECK: movi v0.8h, #{{0x1|1}}, lsl #8 // encoding: [0x20,0xa4,0x00,0x4f]
AArch64: add initial NEON support Patch by Ana Pazos. - Completed implementation of instruction formats: AdvSIMD three same AdvSIMD modified immediate AdvSIMD scalar pairwise - Completed implementation of instruction classes (some of the instructions in these classes belong to yet unfinished instruction formats): Vector Arithmetic Vector Immediate Vector Pairwise Arithmetic - Initial implementation of instruction formats: AdvSIMD scalar two-reg misc AdvSIMD scalar three same - Intial implementation of instruction class: Scalar Arithmetic - Initial clang changes to support arm v8 intrinsics. Note: no clang changes for scalar intrinsics function name mangling yet. - Comprehensive test cases for added instructions To verify auto codegen, encoding, decoding, diagnosis, intrinsics. llvm-svn: 187567
2013-08-01 17:20:35 +08:00
//----------------------------------------------------------------------
// Vector Move Inverted Immediate Shifted
//----------------------------------------------------------------------
mvni v0.2s, #1
mvni v1.2s, #0
mvni v0.2s, #1, lsl #8
mvni v0.2s, #1, lsl #16
mvni v0.2s, #1, lsl #24
mvni v0.4s, #1
mvni v15.4s, #1, lsl #8
mvni v16.4s, #1, lsl #16
mvni v31.4s, #1, lsl #24
mvni v0.4h, #1
mvni v0.4h, #1, lsl #8
mvni v0.8h, #1
mvni v0.8h, #1, lsl #8
AArch64/ARM64: run AArch64 NEON MC tests through ARM64 too. This skips a couple of compare ones due to the different syntaxt for floating-point 0.0. AArch64 does it more canonically, and we'll need to fiddle ARM64 to make it work. llvm-svn: 207119
2014-04-24 23:04:20 +08:00
// CHECK: mvni v0.2s, #{{0x1|1}} // encoding: [0x20,0x04,0x00,0x2f]
// CHECK: mvni v1.2s, #{{0x0|0}} // encoding: [0x01,0x04,0x00,0x2f]
// CHECK: mvni v0.2s, #{{0x1|1}}, lsl #8 // encoding: [0x20,0x24,0x00,0x2f]
// CHECK: mvni v0.2s, #{{0x1|1}}, lsl #16 // encoding: [0x20,0x44,0x00,0x2f]
// CHECK: mvni v0.2s, #{{0x1|1}}, lsl #24 // encoding: [0x20,0x64,0x00,0x2f]
// CHECK: mvni v0.4s, #{{0x1|1}} // encoding: [0x20,0x04,0x00,0x6f]
// CHECK: mvni v15.4s, #{{0x1|1}}, lsl #8 // encoding: [0x2f,0x24,0x00,0x6f]
// CHECK: mvni v16.4s, #{{0x1|1}}, lsl #16 // encoding: [0x30,0x44,0x00,0x6f]
// CHECK: mvni v31.4s, #{{0x1|1}}, lsl #24 // encoding: [0x3f,0x64,0x00,0x6f]
// CHECK: mvni v0.4h, #{{0x1|1}} // encoding: [0x20,0x84,0x00,0x2f]
// CHECK: mvni v0.4h, #{{0x1|1}}, lsl #8 // encoding: [0x20,0xa4,0x00,0x2f]
// CHECK: mvni v0.8h, #{{0x1|1}} // encoding: [0x20,0x84,0x00,0x6f]
// CHECK: mvni v0.8h, #{{0x1|1}}, lsl #8 // encoding: [0x20,0xa4,0x00,0x6f]
AArch64: add initial NEON support Patch by Ana Pazos. - Completed implementation of instruction formats: AdvSIMD three same AdvSIMD modified immediate AdvSIMD scalar pairwise - Completed implementation of instruction classes (some of the instructions in these classes belong to yet unfinished instruction formats): Vector Arithmetic Vector Immediate Vector Pairwise Arithmetic - Initial implementation of instruction formats: AdvSIMD scalar two-reg misc AdvSIMD scalar three same - Intial implementation of instruction class: Scalar Arithmetic - Initial clang changes to support arm v8 intrinsics. Note: no clang changes for scalar intrinsics function name mangling yet. - Comprehensive test cases for added instructions To verify auto codegen, encoding, decoding, diagnosis, intrinsics. llvm-svn: 187567
2013-08-01 17:20:35 +08:00
//----------------------------------------------------------------------
// Vector Bitwise Bit Clear (AND NOT) - immediate
//----------------------------------------------------------------------
bic v0.2s, #1
bic v1.2s, #0
bic v0.2s, #1, lsl #8
bic v0.2s, #1, lsl #16
bic v0.2s, #1, lsl #24
bic v0.4s, #1
bic v0.4s, #1, lsl #8
bic v0.4s, #1, lsl #16
bic v0.4s, #1, lsl #24
bic v15.4h, #1
bic v16.4h, #1, lsl #8
bic v0.8h, #1
bic v31.8h, #1, lsl #8
AArch64/ARM64: run AArch64 NEON MC tests through ARM64 too. This skips a couple of compare ones due to the different syntaxt for floating-point 0.0. AArch64 does it more canonically, and we'll need to fiddle ARM64 to make it work. llvm-svn: 207119
2014-04-24 23:04:20 +08:00
// CHECK: bic v0.2s, #{{0x1|1}} // encoding: [0x20,0x14,0x00,0x2f]
// CHECK: bic v1.2s, #{{0x0|0}} // encoding: [0x01,0x14,0x00,0x2f]
// CHECK: bic v0.2s, #{{0x1|1}}, lsl #8 // encoding: [0x20,0x34,0x00,0x2f]
// CHECK: bic v0.2s, #{{0x1|1}}, lsl #16 // encoding: [0x20,0x54,0x00,0x2f]
// CHECK: bic v0.2s, #{{0x1|1}}, lsl #24 // encoding: [0x20,0x74,0x00,0x2f]
// CHECK: bic v0.4s, #{{0x1|1}} // encoding: [0x20,0x14,0x00,0x6f]
// CHECK: bic v0.4s, #{{0x1|1}}, lsl #8 // encoding: [0x20,0x34,0x00,0x6f]
// CHECK: bic v0.4s, #{{0x1|1}}, lsl #16 // encoding: [0x20,0x54,0x00,0x6f]
// CHECK: bic v0.4s, #{{0x1|1}}, lsl #24 // encoding: [0x20,0x74,0x00,0x6f]
// CHECK: bic v15.4h, #{{0x1|1}} // encoding: [0x2f,0x94,0x00,0x2f]
// CHECK: bic v16.4h, #{{0x1|1}}, lsl #8 // encoding: [0x30,0xb4,0x00,0x2f]
// CHECK: bic v0.8h, #{{0x1|1}} // encoding: [0x20,0x94,0x00,0x6f]
// CHECK: bic v31.8h, #{{0x1|1}}, lsl #8 // encoding: [0x3f,0xb4,0x00,0x6f]
AArch64: add initial NEON support Patch by Ana Pazos. - Completed implementation of instruction formats: AdvSIMD three same AdvSIMD modified immediate AdvSIMD scalar pairwise - Completed implementation of instruction classes (some of the instructions in these classes belong to yet unfinished instruction formats): Vector Arithmetic Vector Immediate Vector Pairwise Arithmetic - Initial implementation of instruction formats: AdvSIMD scalar two-reg misc AdvSIMD scalar three same - Intial implementation of instruction class: Scalar Arithmetic - Initial clang changes to support arm v8 intrinsics. Note: no clang changes for scalar intrinsics function name mangling yet. - Comprehensive test cases for added instructions To verify auto codegen, encoding, decoding, diagnosis, intrinsics. llvm-svn: 187567
2013-08-01 17:20:35 +08:00
//----------------------------------------------------------------------
// Vector Bitwise OR - immedidate
//----------------------------------------------------------------------
orr v0.2s, #1
orr v1.2s, #0
orr v0.2s, #1, lsl #8
orr v0.2s, #1, lsl #16
orr v0.2s, #1, lsl #24
orr v0.4s, #1
orr v0.4s, #1, lsl #8
orr v0.4s, #1, lsl #16
orr v0.4s, #1, lsl #24
orr v31.4h, #1
orr v15.4h, #1, lsl #8
orr v0.8h, #1
orr v16.8h, #1, lsl #8
AArch64/ARM64: run AArch64 NEON MC tests through ARM64 too. This skips a couple of compare ones due to the different syntaxt for floating-point 0.0. AArch64 does it more canonically, and we'll need to fiddle ARM64 to make it work. llvm-svn: 207119
2014-04-24 23:04:20 +08:00
// CHECK: orr v0.2s, #{{0x1|1}} // encoding: [0x20,0x14,0x00,0x0f]
// CHECK: orr v1.2s, #{{0x0|0}} // encoding: [0x01,0x14,0x00,0x0f]
// CHECK: orr v0.2s, #{{0x1|1}}, lsl #8 // encoding: [0x20,0x34,0x00,0x0f]
// CHECK: orr v0.2s, #{{0x1|1}}, lsl #16 // encoding: [0x20,0x54,0x00,0x0f]
// CHECK: orr v0.2s, #{{0x1|1}}, lsl #24 // encoding: [0x20,0x74,0x00,0x0f]
// CHECK: orr v0.4s, #{{0x1|1}} // encoding: [0x20,0x14,0x00,0x4f]
// CHECK: orr v0.4s, #{{0x1|1}}, lsl #8 // encoding: [0x20,0x34,0x00,0x4f]
// CHECK: orr v0.4s, #{{0x1|1}}, lsl #16 // encoding: [0x20,0x54,0x00,0x4f]
// CHECK: orr v0.4s, #{{0x1|1}}, lsl #24 // encoding: [0x20,0x74,0x00,0x4f]
// CHECK: orr v31.4h, #{{0x1|1}} // encoding: [0x3f,0x94,0x00,0x0f]
// CHECK: orr v15.4h, #{{0x1|1}}, lsl #8 // encoding: [0x2f,0xb4,0x00,0x0f]
// CHECK: orr v0.8h, #{{0x1|1}} // encoding: [0x20,0x94,0x00,0x4f]
// CHECK: orr v16.8h, #{{0x1|1}}, lsl #8 // encoding: [0x30,0xb4,0x00,0x4f]
AArch64: add initial NEON support Patch by Ana Pazos. - Completed implementation of instruction formats: AdvSIMD three same AdvSIMD modified immediate AdvSIMD scalar pairwise - Completed implementation of instruction classes (some of the instructions in these classes belong to yet unfinished instruction formats): Vector Arithmetic Vector Immediate Vector Pairwise Arithmetic - Initial implementation of instruction formats: AdvSIMD scalar two-reg misc AdvSIMD scalar three same - Intial implementation of instruction class: Scalar Arithmetic - Initial clang changes to support arm v8 intrinsics. Note: no clang changes for scalar intrinsics function name mangling yet. - Comprehensive test cases for added instructions To verify auto codegen, encoding, decoding, diagnosis, intrinsics. llvm-svn: 187567
2013-08-01 17:20:35 +08:00
//----------------------------------------------------------------------
// Vector Move Immediate Masked
//----------------------------------------------------------------------
movi v0.2s, #1, msl #8
movi v1.2s, #1, msl #16
movi v0.4s, #1, msl #8
movi v31.4s, #1, msl #16
AArch64/ARM64: run AArch64 NEON MC tests through ARM64 too. This skips a couple of compare ones due to the different syntaxt for floating-point 0.0. AArch64 does it more canonically, and we'll need to fiddle ARM64 to make it work. llvm-svn: 207119
2014-04-24 23:04:20 +08:00
// CHECK: movi v0.2s, #{{0x1|1}}, msl #8 // encoding: [0x20,0xc4,0x00,0x0f]
// CHECK: movi v1.2s, #{{0x1|1}}, msl #16 // encoding: [0x21,0xd4,0x00,0x0f]
// CHECK: movi v0.4s, #{{0x1|1}}, msl #8 // encoding: [0x20,0xc4,0x00,0x4f]
// CHECK: movi v31.4s, #{{0x1|1}}, msl #16 // encoding: [0x3f,0xd4,0x00,0x4f]
AArch64: add initial NEON support Patch by Ana Pazos. - Completed implementation of instruction formats: AdvSIMD three same AdvSIMD modified immediate AdvSIMD scalar pairwise - Completed implementation of instruction classes (some of the instructions in these classes belong to yet unfinished instruction formats): Vector Arithmetic Vector Immediate Vector Pairwise Arithmetic - Initial implementation of instruction formats: AdvSIMD scalar two-reg misc AdvSIMD scalar three same - Intial implementation of instruction class: Scalar Arithmetic - Initial clang changes to support arm v8 intrinsics. Note: no clang changes for scalar intrinsics function name mangling yet. - Comprehensive test cases for added instructions To verify auto codegen, encoding, decoding, diagnosis, intrinsics. llvm-svn: 187567
2013-08-01 17:20:35 +08:00
//----------------------------------------------------------------------
// Vector Move Inverted Immediate Masked
//----------------------------------------------------------------------
mvni v1.2s, #0x1, msl #8
mvni v0.2s, #0x1, msl #16
mvni v31.4s, #0x1, msl #8
mvni v0.4s, #0x1, msl #16
AArch64/ARM64: run AArch64 NEON MC tests through ARM64 too. This skips a couple of compare ones due to the different syntaxt for floating-point 0.0. AArch64 does it more canonically, and we'll need to fiddle ARM64 to make it work. llvm-svn: 207119
2014-04-24 23:04:20 +08:00
// CHECK: mvni v1.2s, #{{0x1|1}}, msl #8 // encoding: [0x21,0xc4,0x00,0x2f]
// CHECK: mvni v0.2s, #{{0x1|1}}, msl #16 // encoding: [0x20,0xd4,0x00,0x2f]
// CHECK: mvni v31.4s, #{{0x1|1}}, msl #8 // encoding: [0x3f,0xc4,0x00,0x6f]
// CHECK: mvni v0.4s, #{{0x1|1}}, msl #16 // encoding: [0x20,0xd4,0x00,0x6f]
AArch64: add initial NEON support Patch by Ana Pazos. - Completed implementation of instruction formats: AdvSIMD three same AdvSIMD modified immediate AdvSIMD scalar pairwise - Completed implementation of instruction classes (some of the instructions in these classes belong to yet unfinished instruction formats): Vector Arithmetic Vector Immediate Vector Pairwise Arithmetic - Initial implementation of instruction formats: AdvSIMD scalar two-reg misc AdvSIMD scalar three same - Intial implementation of instruction class: Scalar Arithmetic - Initial clang changes to support arm v8 intrinsics. Note: no clang changes for scalar intrinsics function name mangling yet. - Comprehensive test cases for added instructions To verify auto codegen, encoding, decoding, diagnosis, intrinsics. llvm-svn: 187567
2013-08-01 17:20:35 +08:00
//----------------------------------------------------------------------
// Vector Immediate - per byte
//----------------------------------------------------------------------
movi v0.8b, #0
movi v31.8b, #0xff
movi v15.16b, #0xf
movi v31.16b, #0x1f
AArch64/ARM64: run AArch64 NEON MC tests through ARM64 too. This skips a couple of compare ones due to the different syntaxt for floating-point 0.0. AArch64 does it more canonically, and we'll need to fiddle ARM64 to make it work. llvm-svn: 207119
2014-04-24 23:04:20 +08:00
// CHECK: movi v0.8b, #{{0x0|0}} // encoding: [0x00,0xe4,0x00,0x0f]
// CHECK: movi v31.8b, #{{0xff|255}} // encoding: [0xff,0xe7,0x07,0x0f]
// CHECK: movi v15.16b, #{{0xf|15}} // encoding: [0xef,0xe5,0x00,0x4f]
// CHECK: movi v31.16b, #{{0x1f|31}} // encoding: [0xff,0xe7,0x00,0x4f]
AArch64: add initial NEON support Patch by Ana Pazos. - Completed implementation of instruction formats: AdvSIMD three same AdvSIMD modified immediate AdvSIMD scalar pairwise - Completed implementation of instruction classes (some of the instructions in these classes belong to yet unfinished instruction formats): Vector Arithmetic Vector Immediate Vector Pairwise Arithmetic - Initial implementation of instruction formats: AdvSIMD scalar two-reg misc AdvSIMD scalar three same - Intial implementation of instruction class: Scalar Arithmetic - Initial clang changes to support arm v8 intrinsics. Note: no clang changes for scalar intrinsics function name mangling yet. - Comprehensive test cases for added instructions To verify auto codegen, encoding, decoding, diagnosis, intrinsics. llvm-svn: 187567
2013-08-01 17:20:35 +08:00
//----------------------------------------------------------------------
// Vector Move Immediate - bytemask, per doubleword
//---------------------------------------------------------------------
movi v0.2d, #0xff00ff00ff00ff00
// CHECK: movi v0.2d, #0xff00ff00ff00ff00 // encoding: [0x40,0xe5,0x05,0x6f]
//----------------------------------------------------------------------
// Vector Move Immediate - bytemask, one doubleword
//----------------------------------------------------------------------
movi d0, #0xff00ff00ff00ff00
// CHECK: movi d0, #0xff00ff00ff00ff00 // encoding: [0x40,0xe5,0x05,0x2f]
//----------------------------------------------------------------------
// Vector Floating Point Move Immediate
//----------------------------------------------------------------------
fmov v1.2s, #1.0
fmov v15.4s, #1.0
fmov v31.2d, #1.0
AArch64/ARM64: run AArch64 NEON MC tests through ARM64 too. This skips a couple of compare ones due to the different syntaxt for floating-point 0.0. AArch64 does it more canonically, and we'll need to fiddle ARM64 to make it work. llvm-svn: 207119
2014-04-24 23:04:20 +08:00
// CHECK: fmov v1.2s, #{{1.00000000|1.000000e\+00}} // encoding: [0x01,0xf6,0x03,0x0f]
// CHECK: fmov v15.4s, #{{1.00000000|1.000000e\+00}} // encoding: [0x0f,0xf6,0x03,0x4f]
// CHECK: fmov v31.2d, #{{1.00000000|1.000000e\+00}} // encoding: [0x1f,0xf6,0x03,0x6f]
AArch64: add initial NEON support Patch by Ana Pazos. - Completed implementation of instruction formats: AdvSIMD three same AdvSIMD modified immediate AdvSIMD scalar pairwise - Completed implementation of instruction classes (some of the instructions in these classes belong to yet unfinished instruction formats): Vector Arithmetic Vector Immediate Vector Pairwise Arithmetic - Initial implementation of instruction formats: AdvSIMD scalar two-reg misc AdvSIMD scalar three same - Intial implementation of instruction class: Scalar Arithmetic - Initial clang changes to support arm v8 intrinsics. Note: no clang changes for scalar intrinsics function name mangling yet. - Comprehensive test cases for added instructions To verify auto codegen, encoding, decoding, diagnosis, intrinsics. llvm-svn: 187567
2013-08-01 17:20:35 +08:00
//----------------------------------------------------------------------
// Vector Move - register
//----------------------------------------------------------------------
AArch64: use RegisterOperand for NEON registers. Previously we modelled VPR128 and VPR64 as essentially identical register-classes containing V0-V31 (which had Q0-Q31 as "sub_alias" sub-registers). This model is starting to cause significant problems for code generation, particularly writing EXTRACT/INSERT_SUBREG patterns for converting between the two. The change here switches to classifying VPR64 & VPR128 as RegisterOperands, which are essentially aliases for RegisterClasses with different parsing and printing behaviour. This fits almost exactly with their real status (VPR128 == FPR128 printed strangely, VPR64 == FPR64 printed strangely). llvm-svn: 190665
2013-09-13 15:26:52 +08:00
AArch64: add initial NEON support Patch by Ana Pazos. - Completed implementation of instruction formats: AdvSIMD three same AdvSIMD modified immediate AdvSIMD scalar pairwise - Completed implementation of instruction classes (some of the instructions in these classes belong to yet unfinished instruction formats): Vector Arithmetic Vector Immediate Vector Pairwise Arithmetic - Initial implementation of instruction formats: AdvSIMD scalar two-reg misc AdvSIMD scalar three same - Intial implementation of instruction class: Scalar Arithmetic - Initial clang changes to support arm v8 intrinsics. Note: no clang changes for scalar intrinsics function name mangling yet. - Comprehensive test cases for added instructions To verify auto codegen, encoding, decoding, diagnosis, intrinsics. llvm-svn: 187567
2013-08-01 17:20:35 +08:00
mov v0.8b, v31.8b
mov v15.16b, v16.16b
orr v0.8b, v31.8b, v31.8b
orr v15.16b, v16.16b, v16.16b
TableGen/ARM64: print aliases even if they have syntax variants. To get at least one use of the change (and some actual tests) in with its commit, I've enabled the AArch64 & ARM64 NEON mov aliases. llvm-svn: 208867
2014-05-15 19:16:32 +08:00
// CHECK: mov v0.8b, v31.8b // encoding: [0xe0,0x1f,0xbf,0x0e]
// CHECK: mov v15.16b, v16.16b // encoding: [0x0f,0x1e,0xb0,0x4e]
// CHECK: mov v0.8b, v31.8b // encoding: [0xe0,0x1f,0xbf,0x0e]
// CHECK: mov v15.16b, v16.16b // encoding: [0x0f,0x1e,0xb0,0x4e]
AArch64: add initial NEON support Patch by Ana Pazos. - Completed implementation of instruction formats: AdvSIMD three same AdvSIMD modified immediate AdvSIMD scalar pairwise - Completed implementation of instruction classes (some of the instructions in these classes belong to yet unfinished instruction formats): Vector Arithmetic Vector Immediate Vector Pairwise Arithmetic - Initial implementation of instruction formats: AdvSIMD scalar two-reg misc AdvSIMD scalar three same - Intial implementation of instruction class: Scalar Arithmetic - Initial clang changes to support arm v8 intrinsics. Note: no clang changes for scalar intrinsics function name mangling yet. - Comprehensive test cases for added instructions To verify auto codegen, encoding, decoding, diagnosis, intrinsics. llvm-svn: 187567
2013-08-01 17:20:35 +08:00