2018-04-13 22:41:36 +08:00
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// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
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// --------------------------------------------------------------------------//
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// Invalid operand (.h)
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ld1sh z23.h, p0/z, [x13, #1, MUL VL]
|
[AArch64][SVE] Improve diagnostics for vectors with incorrect element-size.
For regular SVE vector operands, this patch introduces a more
sensible diagnostic when the vector has a wrong suffix (e.g. z0.s vs z0.b).
For example:
add z0.s, z1.s, z2.b -> invalid element width
^_____^
mismatch
For the vector-with-shift/extend (e.g. z0.s, uxtw #2) this patch takes
a slightly different approach and instead returns a 'invalid operand'
if the element size is not as expected. This is because the diagnostics
are more specificied to suggest using the right shift/extend suffix. This
is a trade-off not to introduce more operand classes and still provide
useful diagnostics for LD1 and PRF instructions.
For example:
ld1w z1.s, p0/z, [x0, z0.s] -> invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
ld1w z1.d, p0/z, [x0, z0.s] -> invalid operand
^________________^
mismatch
For gather prefetches, both 'z0.s' and 'z0.d' would be allowed:
prfw #0, p0, [x0, z0.s] -> invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #2'
prfw #0, p0, [x0, z0.d] -> invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2'
Without this change, the diagnostic would unnecessarily suggest a
different element size:
prfw #0, p0, [x0, z0.s] -> invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2'
Reviewers: SjoerdMeijer, aemerson, fhahn, samparker, javed.absar
Reviewed By: SjoerdMeijer
Differential Revision: https://reviews.llvm.org/D46688
llvm-svn: 332483
2018-05-16 23:45:17 +08:00
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
|
2018-04-13 22:41:36 +08:00
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// CHECK-NEXT: ld1sh z23.h, p0/z, [x13, #1, MUL VL]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ld1sh z29.h, p0/z, [x3, #1, MUL VL]
|
[AArch64][SVE] Improve diagnostics for vectors with incorrect element-size.
For regular SVE vector operands, this patch introduces a more
sensible diagnostic when the vector has a wrong suffix (e.g. z0.s vs z0.b).
For example:
add z0.s, z1.s, z2.b -> invalid element width
^_____^
mismatch
For the vector-with-shift/extend (e.g. z0.s, uxtw #2) this patch takes
a slightly different approach and instead returns a 'invalid operand'
if the element size is not as expected. This is because the diagnostics
are more specificied to suggest using the right shift/extend suffix. This
is a trade-off not to introduce more operand classes and still provide
useful diagnostics for LD1 and PRF instructions.
For example:
ld1w z1.s, p0/z, [x0, z0.s] -> invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
ld1w z1.d, p0/z, [x0, z0.s] -> invalid operand
^________________^
mismatch
For gather prefetches, both 'z0.s' and 'z0.d' would be allowed:
prfw #0, p0, [x0, z0.s] -> invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #2'
prfw #0, p0, [x0, z0.d] -> invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2'
Without this change, the diagnostic would unnecessarily suggest a
different element size:
prfw #0, p0, [x0, z0.s] -> invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2'
Reviewers: SjoerdMeijer, aemerson, fhahn, samparker, javed.absar
Reviewed By: SjoerdMeijer
Differential Revision: https://reviews.llvm.org/D46688
llvm-svn: 332483
2018-05-16 23:45:17 +08:00
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
|
2018-04-13 22:41:36 +08:00
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// CHECK-NEXT: ld1sh z29.h, p0/z, [x3, #1, MUL VL]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Immediate out of lower bound [-8, 7].
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ld1sh z30.s, p6/z, [x25, #-9, MUL VL]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
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// CHECK-NEXT: ld1sh z30.s, p6/z, [x25, #-9, MUL VL]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ld1sh z29.s, p5/z, [x15, #8, MUL VL]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
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// CHECK-NEXT: ld1sh z29.s, p5/z, [x15, #8, MUL VL]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ld1sh z28.d, p2/z, [x28, #-9, MUL VL]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
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// CHECK-NEXT: ld1sh z28.d, p2/z, [x28, #-9, MUL VL]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ld1sh z27.d, p1/z, [x26, #8, MUL VL]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-8, 7].
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// CHECK-NEXT: ld1sh z27.d, p1/z, [x26, #8, MUL VL]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// restricted predicate has range [0, 7].
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ld1sh z12.s, p8/z, [x13, #1, MUL VL]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
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// CHECK-NEXT: ld1sh z12.s, p8/z, [x13, #1, MUL VL]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ld1sh z4.d, p8/z, [x11, #1, MUL VL]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
|
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// CHECK-NEXT: ld1sh z4.d, p8/z, [x11, #1, MUL VL]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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|
// Invalid vector list.
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ld1sh { }, p0/z, [x1, #1, MUL VL]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
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// CHECK-NEXT: ld1sh { }, p0/z, [x1, #1, MUL VL]
|
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|
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ld1sh { z1.s, z2.s }, p0/z, [x1, #1, MUL VL]
|
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|
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
|
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|
// CHECK-NEXT: ld1sh { z1.s, z2.s }, p0/z, [x1, #1, MUL VL]
|
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|
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ld1sh { v0.2d }, p0/z, [x1, #1, MUL VL]
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|
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
|
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// CHECK-NEXT: ld1sh { v0.2d }, p0/z, [x1, #1, MUL VL]
|
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|
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
2018-04-20 20:52:01 +08:00
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// --------------------------------------------------------------------------//
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// Invalid scalar + scalar addressing modes
|
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|
ld1sh z0.s, p0/z, [x0, x0]
|
[AArch64][SVE] Enable DiagnosticPredicates for SVE LD1 instructions.
This patch extends the PredicateMethod of AsmOperands used in SVE's
LD1 instructions with a DiagnosticPredicate. This makes them 'context
sensitive' to the operand that has been parsed and tells the user to
use the right register (with expected shift/extend), rather than telling
the immediate is out of range when it actually parsed a register.
Patch [2/2] in a series to improve assembler diagnostics for SVE:
- Patch [1/2]: https://reviews.llvm.org/D45879
- Patch [2/2]: https://reviews.llvm.org/D45880
Reviewers: olista01, stoklund, craig.topper, mcrosier, rengolin, echristo, fhahn, SjoerdMeijer, evandro, javed.absar
Reviewed By: fhahn
Differential Revision: https://reviews.llvm.org/D45880
llvm-svn: 330934
2018-04-26 20:54:42 +08:00
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
|
2018-04-20 20:52:01 +08:00
|
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|
// CHECK-NEXT: ld1sh z0.s, p0/z, [x0, x0]
|
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|
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
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|
ld1sh z0.s, p0/z, [x0, xzr]
|
[AArch64][SVE] Enable DiagnosticPredicates for SVE LD1 instructions.
This patch extends the PredicateMethod of AsmOperands used in SVE's
LD1 instructions with a DiagnosticPredicate. This makes them 'context
sensitive' to the operand that has been parsed and tells the user to
use the right register (with expected shift/extend), rather than telling
the immediate is out of range when it actually parsed a register.
Patch [2/2] in a series to improve assembler diagnostics for SVE:
- Patch [1/2]: https://reviews.llvm.org/D45879
- Patch [2/2]: https://reviews.llvm.org/D45880
Reviewers: olista01, stoklund, craig.topper, mcrosier, rengolin, echristo, fhahn, SjoerdMeijer, evandro, javed.absar
Reviewed By: fhahn
Differential Revision: https://reviews.llvm.org/D45880
llvm-svn: 330934
2018-04-26 20:54:42 +08:00
|
|
|
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
|
2018-04-20 20:52:01 +08:00
|
|
|
// CHECK-NEXT: ld1sh z0.s, p0/z, [x0, xzr]
|
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|
|
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
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|
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|
|
|
|
|
|
ld1sh z0.s, p0/z, [x0, x0, lsl #2]
|
[AArch64][SVE] Enable DiagnosticPredicates for SVE LD1 instructions.
This patch extends the PredicateMethod of AsmOperands used in SVE's
LD1 instructions with a DiagnosticPredicate. This makes them 'context
sensitive' to the operand that has been parsed and tells the user to
use the right register (with expected shift/extend), rather than telling
the immediate is out of range when it actually parsed a register.
Patch [2/2] in a series to improve assembler diagnostics for SVE:
- Patch [1/2]: https://reviews.llvm.org/D45879
- Patch [2/2]: https://reviews.llvm.org/D45880
Reviewers: olista01, stoklund, craig.topper, mcrosier, rengolin, echristo, fhahn, SjoerdMeijer, evandro, javed.absar
Reviewed By: fhahn
Differential Revision: https://reviews.llvm.org/D45880
llvm-svn: 330934
2018-04-26 20:54:42 +08:00
|
|
|
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
|
2018-04-20 20:52:01 +08:00
|
|
|
// CHECK-NEXT: ld1sh z0.s, p0/z, [x0, x0, lsl #2]
|
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|
|
|
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
|
|
|
|
|
|
|
|
|
ld1sh z0.s, p0/z, [x0, w0]
|
[AArch64][SVE] Enable DiagnosticPredicates for SVE LD1 instructions.
This patch extends the PredicateMethod of AsmOperands used in SVE's
LD1 instructions with a DiagnosticPredicate. This makes them 'context
sensitive' to the operand that has been parsed and tells the user to
use the right register (with expected shift/extend), rather than telling
the immediate is out of range when it actually parsed a register.
Patch [2/2] in a series to improve assembler diagnostics for SVE:
- Patch [1/2]: https://reviews.llvm.org/D45879
- Patch [2/2]: https://reviews.llvm.org/D45880
Reviewers: olista01, stoklund, craig.topper, mcrosier, rengolin, echristo, fhahn, SjoerdMeijer, evandro, javed.absar
Reviewed By: fhahn
Differential Revision: https://reviews.llvm.org/D45880
llvm-svn: 330934
2018-04-26 20:54:42 +08:00
|
|
|
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
|
2018-04-20 20:52:01 +08:00
|
|
|
// CHECK-NEXT: ld1sh z0.s, p0/z, [x0, w0]
|
|
|
|
|
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
|
|
|
|
|
|
|
|
|
ld1sh z0.s, p0/z, [x0, w0, uxtw]
|
[AArch64][SVE] Enable DiagnosticPredicates for SVE LD1 instructions.
This patch extends the PredicateMethod of AsmOperands used in SVE's
LD1 instructions with a DiagnosticPredicate. This makes them 'context
sensitive' to the operand that has been parsed and tells the user to
use the right register (with expected shift/extend), rather than telling
the immediate is out of range when it actually parsed a register.
Patch [2/2] in a series to improve assembler diagnostics for SVE:
- Patch [1/2]: https://reviews.llvm.org/D45879
- Patch [2/2]: https://reviews.llvm.org/D45880
Reviewers: olista01, stoklund, craig.topper, mcrosier, rengolin, echristo, fhahn, SjoerdMeijer, evandro, javed.absar
Reviewed By: fhahn
Differential Revision: https://reviews.llvm.org/D45880
llvm-svn: 330934
2018-04-26 20:54:42 +08:00
|
|
|
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1'
|
2018-04-20 20:52:01 +08:00
|
|
|
// CHECK-NEXT: ld1sh z0.s, p0/z, [x0, w0, uxtw]
|
|
|
|
|
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
2018-04-26 16:43:22 +08:00
|
|
|
|
|
|
|
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|
|
// --------------------------------------------------------------------------//
|
|
|
|
|
// Invalid scalar + vector addressing modes
|
|
|
|
|
|
|
|
|
|
ld1sh z0.d, p0/z, [x0, z0.h]
|
[AArch64][SVE] Improve diagnostics for vectors with incorrect element-size.
For regular SVE vector operands, this patch introduces a more
sensible diagnostic when the vector has a wrong suffix (e.g. z0.s vs z0.b).
For example:
add z0.s, z1.s, z2.b -> invalid element width
^_____^
mismatch
For the vector-with-shift/extend (e.g. z0.s, uxtw #2) this patch takes
a slightly different approach and instead returns a 'invalid operand'
if the element size is not as expected. This is because the diagnostics
are more specificied to suggest using the right shift/extend suffix. This
is a trade-off not to introduce more operand classes and still provide
useful diagnostics for LD1 and PRF instructions.
For example:
ld1w z1.s, p0/z, [x0, z0.s] -> invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
ld1w z1.d, p0/z, [x0, z0.s] -> invalid operand
^________________^
mismatch
For gather prefetches, both 'z0.s' and 'z0.d' would be allowed:
prfw #0, p0, [x0, z0.s] -> invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #2'
prfw #0, p0, [x0, z0.d] -> invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2'
Without this change, the diagnostic would unnecessarily suggest a
different element size:
prfw #0, p0, [x0, z0.s] -> invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2'
Reviewers: SjoerdMeijer, aemerson, fhahn, samparker, javed.absar
Reviewed By: SjoerdMeijer
Differential Revision: https://reviews.llvm.org/D46688
llvm-svn: 332483
2018-05-16 23:45:17 +08:00
|
|
|
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
|
2018-04-26 16:43:22 +08:00
|
|
|
// CHECK-NEXT: ld1sh z0.d, p0/z, [x0, z0.h]
|
|
|
|
|
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
|
|
|
|
|
|
|
|
|
ld1sh z0.d, p0/z, [x0, z0.s]
|
[AArch64][SVE] Improve diagnostics for vectors with incorrect element-size.
For regular SVE vector operands, this patch introduces a more
sensible diagnostic when the vector has a wrong suffix (e.g. z0.s vs z0.b).
For example:
add z0.s, z1.s, z2.b -> invalid element width
^_____^
mismatch
For the vector-with-shift/extend (e.g. z0.s, uxtw #2) this patch takes
a slightly different approach and instead returns a 'invalid operand'
if the element size is not as expected. This is because the diagnostics
are more specificied to suggest using the right shift/extend suffix. This
is a trade-off not to introduce more operand classes and still provide
useful diagnostics for LD1 and PRF instructions.
For example:
ld1w z1.s, p0/z, [x0, z0.s] -> invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
ld1w z1.d, p0/z, [x0, z0.s] -> invalid operand
^________________^
mismatch
For gather prefetches, both 'z0.s' and 'z0.d' would be allowed:
prfw #0, p0, [x0, z0.s] -> invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #2'
prfw #0, p0, [x0, z0.d] -> invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2'
Without this change, the diagnostic would unnecessarily suggest a
different element size:
prfw #0, p0, [x0, z0.s] -> invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2'
Reviewers: SjoerdMeijer, aemerson, fhahn, samparker, javed.absar
Reviewed By: SjoerdMeijer
Differential Revision: https://reviews.llvm.org/D46688
llvm-svn: 332483
2018-05-16 23:45:17 +08:00
|
|
|
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
|
2018-04-26 16:43:22 +08:00
|
|
|
// CHECK-NEXT: ld1sh z0.d, p0/z, [x0, z0.s]
|
|
|
|
|
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
|
|
|
|
|
|
|
|
|
ld1sh z0.s, p0/z, [x0, z0.s]
|
[AArch64][SVE] Enable DiagnosticPredicates for SVE LD1 instructions.
This patch extends the PredicateMethod of AsmOperands used in SVE's
LD1 instructions with a DiagnosticPredicate. This makes them 'context
sensitive' to the operand that has been parsed and tells the user to
use the right register (with expected shift/extend), rather than telling
the immediate is out of range when it actually parsed a register.
Patch [2/2] in a series to improve assembler diagnostics for SVE:
- Patch [1/2]: https://reviews.llvm.org/D45879
- Patch [2/2]: https://reviews.llvm.org/D45880
Reviewers: olista01, stoklund, craig.topper, mcrosier, rengolin, echristo, fhahn, SjoerdMeijer, evandro, javed.absar
Reviewed By: fhahn
Differential Revision: https://reviews.llvm.org/D45880
llvm-svn: 330934
2018-04-26 20:54:42 +08:00
|
|
|
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'
|
2018-04-26 16:43:22 +08:00
|
|
|
// CHECK-NEXT: ld1sh z0.s, p0/z, [x0, z0.s]
|
|
|
|
|
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
|
|
|
|
|
|
|
|
|
ld1sh z0.s, p0/z, [x0, z0.s, uxtw #2]
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[AArch64][SVE] Asm: Improve diagnostics for gather loads.
This patch extends the 'isSVEVectorRegWithShiftExtend' function to
improve diagnostics for SVE's gather load (scalar + vector) addressing
modes. Instead of always suggesting the 'unscaled' addressing mode,
the use of DiagnosticPredicate enables a more specific error message
in the context where the scaling is incorrect. For example:
ld1h z0.d, p0/z, [x0, z0.d, lsl #2]
^
shift amount should be '1'
Instead of suggesting the packed, unscaled addressing mode:
expected 'z[0..31].d, (uxtw|sxtw)'
the assembler now suggests using the proper scaling:
expected 'z[0..31].d, (lsl|uxtw|sxtw) #1'
Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, javed.absar
Reviewed By: fhahn
Differential Revision: https://reviews.llvm.org/D46124
llvm-svn: 331162
2018-04-30 15:24:38 +08:00
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #1'
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2018-04-26 16:43:22 +08:00
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// CHECK-NEXT: ld1sh z0.s, p0/z, [x0, z0.s, uxtw #2]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ld1sh z0.s, p0/z, [x0, z0.s, lsl #1]
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[AArch64][SVE] Asm: Improve diagnostics for gather loads.
This patch extends the 'isSVEVectorRegWithShiftExtend' function to
improve diagnostics for SVE's gather load (scalar + vector) addressing
modes. Instead of always suggesting the 'unscaled' addressing mode,
the use of DiagnosticPredicate enables a more specific error message
in the context where the scaling is incorrect. For example:
ld1h z0.d, p0/z, [x0, z0.d, lsl #2]
^
shift amount should be '1'
Instead of suggesting the packed, unscaled addressing mode:
expected 'z[0..31].d, (uxtw|sxtw)'
the assembler now suggests using the proper scaling:
expected 'z[0..31].d, (lsl|uxtw|sxtw) #1'
Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, javed.absar
Reviewed By: fhahn
Differential Revision: https://reviews.llvm.org/D46124
llvm-svn: 331162
2018-04-30 15:24:38 +08:00
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #1'
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2018-04-26 16:43:22 +08:00
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// CHECK-NEXT: ld1sh z0.s, p0/z, [x0, z0.s, lsl #1]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ld1sh z0.d, p0/z, [x0, z0.d, lsl #2]
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[AArch64][SVE] Asm: Improve diagnostics for gather loads.
This patch extends the 'isSVEVectorRegWithShiftExtend' function to
improve diagnostics for SVE's gather load (scalar + vector) addressing
modes. Instead of always suggesting the 'unscaled' addressing mode,
the use of DiagnosticPredicate enables a more specific error message
in the context where the scaling is incorrect. For example:
ld1h z0.d, p0/z, [x0, z0.d, lsl #2]
^
shift amount should be '1'
Instead of suggesting the packed, unscaled addressing mode:
expected 'z[0..31].d, (uxtw|sxtw)'
the assembler now suggests using the proper scaling:
expected 'z[0..31].d, (lsl|uxtw|sxtw) #1'
Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, javed.absar
Reviewed By: fhahn
Differential Revision: https://reviews.llvm.org/D46124
llvm-svn: 331162
2018-04-30 15:24:38 +08:00
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #1'
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2018-04-26 16:43:22 +08:00
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// CHECK-NEXT: ld1sh z0.d, p0/z, [x0, z0.d, lsl #2]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ld1sh z0.d, p0/z, [x0, z0.d, sxtw #2]
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[AArch64][SVE] Asm: Improve diagnostics for gather loads.
This patch extends the 'isSVEVectorRegWithShiftExtend' function to
improve diagnostics for SVE's gather load (scalar + vector) addressing
modes. Instead of always suggesting the 'unscaled' addressing mode,
the use of DiagnosticPredicate enables a more specific error message
in the context where the scaling is incorrect. For example:
ld1h z0.d, p0/z, [x0, z0.d, lsl #2]
^
shift amount should be '1'
Instead of suggesting the packed, unscaled addressing mode:
expected 'z[0..31].d, (uxtw|sxtw)'
the assembler now suggests using the proper scaling:
expected 'z[0..31].d, (lsl|uxtw|sxtw) #1'
Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, javed.absar
Reviewed By: fhahn
Differential Revision: https://reviews.llvm.org/D46124
llvm-svn: 331162
2018-04-30 15:24:38 +08:00
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #1'
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2018-04-26 16:43:22 +08:00
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// CHECK-NEXT: ld1sh z0.d, p0/z, [x0, z0.d, sxtw #2]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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2018-04-30 01:33:38 +08:00
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// --------------------------------------------------------------------------//
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// Invalid vector + immediate addressing modes
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ld1sh z0.s, p0/z, [z0.s, #-2]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
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// CHECK-NEXT: ld1sh z0.s, p0/z, [z0.s, #-2]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ld1sh z0.s, p0/z, [z0.s, #-1]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
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// CHECK-NEXT: ld1sh z0.s, p0/z, [z0.s, #-1]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ld1sh z0.s, p0/z, [z0.s, #63]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
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// CHECK-NEXT: ld1sh z0.s, p0/z, [z0.s, #63]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ld1sh z0.s, p0/z, [z0.s, #64]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
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// CHECK-NEXT: ld1sh z0.s, p0/z, [z0.s, #64]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ld1sh z0.s, p0/z, [z0.s, #3]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
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// CHECK-NEXT: ld1sh z0.s, p0/z, [z0.s, #3]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ld1sh z0.d, p0/z, [z0.d, #-2]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
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// CHECK-NEXT: ld1sh z0.d, p0/z, [z0.d, #-2]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ld1sh z0.d, p0/z, [z0.d, #-1]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
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// CHECK-NEXT: ld1sh z0.d, p0/z, [z0.d, #-1]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ld1sh z0.d, p0/z, [z0.d, #63]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
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// CHECK-NEXT: ld1sh z0.d, p0/z, [z0.d, #63]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ld1sh z0.d, p0/z, [z0.d, #64]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
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// CHECK-NEXT: ld1sh z0.d, p0/z, [z0.d, #64]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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ld1sh z0.d, p0/z, [z0.d, #3]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be a multiple of 2 in range [0, 62].
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// CHECK-NEXT: ld1sh z0.d, p0/z, [z0.d, #3]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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2018-07-31 00:05:45 +08:00
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// --------------------------------------------------------------------------//
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// Negative tests for instructions that are incompatible with movprfx
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movprfx z0.d, p0/z, z7.d
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ld1sh { z0.d }, p0/z, [z0.d]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
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// CHECK-NEXT: ld1sh { z0.d }, p0/z, [z0.d]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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movprfx z0, z7
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ld1sh { z0.d }, p0/z, [z0.d]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
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// CHECK-NEXT: ld1sh { z0.d }, p0/z, [z0.d]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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